From nobody Sat Jul 25 04:30:07 2026 Received: from out-182.mta1.migadu.com (out-182.mta1.migadu.com [95.215.58.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2DEC2459E5 for ; Sat, 18 Jul 2026 11:17:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784373480; cv=none; b=EO0N0roHxFanoZQSXfu0VdJRME2yyzMLynQIxkMsXseRrM8QMMOLfw0vftwWQXmAocshlcWpTpSO2ZUxhPnuw18W1IVBMB/RrEAW6DF5Db5gSGc9/rBKM/JmeQe/exSRKKFs/5V3Ayk+XKA2ETFUiizfktaEQ+dA3cF5jiKsv68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784373480; c=relaxed/simple; bh=2LVGL+bxrdFv3YdhMCgGj4Ds6IOsJVU82chnqblVSWg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=J/mlRFJHAPTzFhdgZuzGKTCzs7zrO2U9POCWvXwjLs9MIKfvdiUFBmzznXQ2kGGh/bev6ykjHJhgU+3X0IOlhfO0djcc/M2m3GwnEVsEyutK+02OKpX+EkcbBHLXiMq154vgK1Nj1z2Lh4pFKw9ClvLSM1MYRp0mGO1TuzcU3h4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mieulab.com; spf=pass smtp.mailfrom=mieulab.com; dkim=pass (2048-bit key) header.d=mieulab.com header.i=@mieulab.com header.b=dDvWpZ9C; arc=none smtp.client-ip=95.215.58.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mieulab.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mieulab.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mieulab.com header.i=@mieulab.com header.b="dDvWpZ9C" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mieulab.com; s=key1; t=1784373476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s0L/CvyUhmFHnr8ZdmxcBtUe6vtszqB/KJYG8quybbM=; b=dDvWpZ9C5oZyJar+uUTs4hmEtNIhJMTY6rjb6zyg3K7IDsgqkeaqozlMLWsBBPFAD41QJ8 FTzb3xhfF7CNK2ktGMMIzOCaP03q/LiLBoAFueIozDdt+l9FYq7s7rJ2xzk4Onhe++PZR1 5og3NPL+dwVeB3t0HoLgIxrxeDW/a5xsnQnO5OCKu5Z1NKG+2G1A8kbdwKMnpes6k3nFBx xENiHUDdkjdSQ9drg6slecE+L+/J13/2hsyhZqoE7pX6WXlq2jhGme9MLlNGlXKHU9qQKF 6NwkJw/L794RhfQ4NydNsGCtJRNJxc8LQQMUyxI0uuPf7FwteZYApm6kLnbJIQ== From: Zinan Zhou To: Neil Armstrong Cc: Zinan Zhou , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 1/2] dt-bindings: display: meson-dw-hdmi: add GXLX2 compatible Date: Sat, 18 Jul 2026 20:15:26 +0900 Message-ID: <20260718111527.119231-2-zinan@mieulab.com> In-Reply-To: <20260718111527.119231-1-zinan@mieulab.com> References: <20260718111527.119231-1-zinan@mieulab.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The GXLX2 HDMI transmitter uses the byte-addressed DesignWare controller registers and directly mapped TOP window also present on G12A. Its display pipeline and HDMI PHY programming remain GXL-like, however. Add a dedicated compatible with no fallback. The generic meson-gx-dw-hdmi interface uses indirect address/data registers and cannot operate this hardware, while meson-g12a-dw-hdmi would select incompatible PHY initialization values. The one-resource representation is proposed for RFC review; DWC and TOP occupy one contiguous MMIO range on the tested HG680-LC. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Zinan Zhou --- .../devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdm= i.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.ya= ml index 416fe263ac92..4a17eccabea9 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml @@ -29,8 +29,10 @@ description: | The HDMI TOP block only supports HPD sensing. The Synopsys HDMI Controller interrupt is routed through the TOP Block interrupt. - Communication to the TOP Block and the Synopsys HDMI Controller is done - via a pair of dedicated addr+read/write registers. + Communication with the TOP Block and the Synopsys HDMI Controller uses a= pair + of dedicated address/data registers on GXBB, GXL and GXM. GXLX2 and G12A + instead expose byte-addressed controller registers and a directly mapped= TOP + window. The HDMI PHY is configured by registers in the HHI register block. =20 Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDM= I mux @@ -54,6 +56,7 @@ properties: - amlogic,meson-gxm-dw-hdmi # GXM (S912) - const: amlogic,meson-gx-dw-hdmi - enum: + - amlogic,meson-gxlx2-dw-hdmi # GXLX2 (S905L3) - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2) =20 reg: --=20 2.43.0 From nobody Sat Jul 25 04:30:07 2026 Received: from out-179.mta1.migadu.com (out-179.mta1.migadu.com [95.215.58.179]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58D4B2773C3 for ; Sat, 18 Jul 2026 11:18:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.179 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784373491; cv=none; b=m9hsV/GoWB//Z1rtYoyW200rgvzOAES9vYrpBQdL3AGo8x4DBinv51+mfO2224+sesRiWSl90g1dX/thNsIwQRK+dAZAvGiu5N74n1K3zTmaRmM6tLp4OVk+7teQO6z3Hxj/Dm/cjGnwPlM8CyF47OBii3026kVDbyP8R0NmV10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784373491; c=relaxed/simple; bh=/0f0tHZ1IHioTznWyI0hVTGFtkZLQKRSwDPVVu6rmnc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fUWWR124X2x1Y3tecnjlVoXyjpsBDbQBQm7DRpwcR0DNgrcIqDWfXeRu784s/+LmH2HFhFaEGmTH9Gy8Sn4Qb+aDnW6ih8tKXMjhuA3QuNbPhIbNYvhWH1hfMaktjL5+PvkNkEGChbRz3uFpdBhU5zzGl9oUGeMLiRTgc2reVd8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mieulab.com; spf=pass smtp.mailfrom=mieulab.com; dkim=pass (2048-bit key) header.d=mieulab.com header.i=@mieulab.com header.b=QPMlD6/O; arc=none smtp.client-ip=95.215.58.179 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mieulab.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mieulab.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mieulab.com header.i=@mieulab.com header.b="QPMlD6/O" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mieulab.com; s=key1; t=1784373487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iX+mNcsLzoRlbFysdi2lELSN0lTLQ6Chr+xxoRDbP5k=; b=QPMlD6/O5/Lsvl23y5B4KKBWFZMRIMHic9yi0aOgL8KgoVFqgXC765fppxcTzX/tAlZUsr BWmeHq/uIjJkvjHNlG5xgqUxgd3zu2rdQTWLl2lf1zNyKnN0u/SiWuyif8GwCxVFXtKoHT MZe52lPofJxNEZXBlPHi3XNOH084F5Ypk64LgnlrFGH6icm/iT7OZ8CCBwihHJYoeXv6o1 SlpEy/+K9RSVS9PVcvnkisHCpnMRoNvz0VilZU6fQeiIIg4dCNPIKm2mqYjWEsutAfRXVD FOAHNBF3fxg7NA4KcP094WBjg1jNl53PkRL7V/dmUYUXuQ9xsBLLOYMYX1XQ0w== From: Zinan Zhou To: Neil Armstrong Cc: Zinan Zhou , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , dri-devel@lists.freedesktop.org, linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/2] drm/meson: add GXLX2 HDMI register support Date: Sat, 18 Jul 2026 20:15:27 +0900 Message-ID: <20260718111527.119231-3-zinan@mieulab.com> In-Reply-To: <20260718111527.119231-1-zinan@mieulab.com> References: <20260718111527.119231-1-zinan@mieulab.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" GXLX2 combines a GXL-like display pipeline and HDMI PHY with directly mapped DesignWare and TOP registers. Reusing the indirect GX callbacks returns an invalid HDMI controller ID and prevents the HDMI component from binding. Add GXLX2 match data using the existing direct register callbacks, while retaining the GXL PHY initialization values. Do not enable APB3 fail-on-error through the legacy indirect control-register offsets for a direct-register device. Add the compatible to the VPU component match list and use the GXLX2-specific HHI_HDMI_PHY_CNTL0 value for the 297 MHz pixel-clock bucket. The register layout and the 297 MHz value were determined by analysis of the HG680-LC vendor kernel. Public Amlogic-derived source independently documents the direct access mechanism and the ordinary GXL PHY values; no vendor code is copied by this change. An equivalent Linux 6.6 implementation was tested on an HG680-LC with 1080p HDMI video and two-channel HDMI audio. The Linux 6.12 port boots from eMMC with working Ethernet, 1080p and native 1440p video, and two-channel HDMI audio. This port has passed arm64 compilation; 4K30 physical validation of the 297 MHz branch remains pending. Assisted-by: Codex:gpt-5.6-sol Signed-off-by: Zinan Zhou --- drivers/gpu/drm/meson/meson_drv.c | 1 + drivers/gpu/drm/meson/meson_dw_hdmi.c | 33 +++++++++++++++++++++++---- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meso= n_drv.c index 49ff9f1f16d3..5c136743e60c 100644 --- a/drivers/gpu/drm/meson/meson_drv.c +++ b/drivers/gpu/drm/meson/meson_drv.c @@ -469,6 +469,7 @@ static void meson_drv_shutdown(struct platform_device *= pdev) static const struct of_device_id components_dev_match[] =3D { { .compatible =3D "amlogic,meson-gxbb-dw-hdmi" }, { .compatible =3D "amlogic,meson-gxl-dw-hdmi" }, + { .compatible =3D "amlogic,meson-gxlx2-dw-hdmi" }, { .compatible =3D "amlogic,meson-gxm-dw-hdmi" }, { .compatible =3D "amlogic,meson-g12a-dw-hdmi" }, {} diff --git a/drivers/gpu/drm/meson/meson_dw_hdmi.c b/drivers/gpu/drm/meson/= meson_dw_hdmi.c index 1004108fb7ca..f02d6a513dd3 100644 --- a/drivers/gpu/drm/meson/meson_dw_hdmi.c +++ b/drivers/gpu/drm/meson/meson_dw_hdmi.c @@ -136,6 +136,8 @@ struct meson_dw_hdmi_data { unsigned int addr, unsigned int data); u32 cntl0_init; u32 cntl1_init; + u32 phy_cntl0_3g; + bool uses_direct_regs; }; =20 struct meson_dw_hdmi { @@ -287,7 +289,9 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_h= dmi *dw_hdmi, /* For 420, pixel clock is half unlike venc clock */ if (mode_is_420) pixel_clock /=3D 2; =20 - if (dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || + if (dw_hdmi_is_compatible(dw_hdmi, + "amlogic,meson-gxlx2-dw-hdmi") || + dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(dw_hdmi, "amlogic,meson-gxm-dw-hdmi")) { if (pixel_clock >=3D 371250) { /* 5.94Gbps, 3.7125Gbps */ @@ -295,7 +299,8 @@ static void meson_hdmi_phy_setup_mode(struct meson_dw_h= dmi *dw_hdmi, regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2136315b); } else if (pixel_clock >=3D 297000) { /* 2.97Gbps */ - regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0x33303382); + regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, + dw_hdmi->data->phy_cntl0_3g); regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL3, 0x2036315b); } else if (pixel_clock >=3D 148500) { /* 1.485Gbps */ @@ -586,6 +591,7 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_gx= l_data =3D { .dwc_write =3D dw_hdmi_dwc_write, .cntl0_init =3D 0x0, .cntl1_init =3D PHY_CNTL1_INIT, + .phy_cntl0_3g =3D 0x33303382, }; =20 static const struct meson_dw_hdmi_data meson_dw_hdmi_g12a_data =3D { @@ -595,6 +601,19 @@ static const struct meson_dw_hdmi_data meson_dw_hdmi_g= 12a_data =3D { .dwc_write =3D dw_hdmi_g12a_dwc_write, .cntl0_init =3D 0x000b4242, /* Bandgap */ .cntl1_init =3D PHY_CNTL1_INIT, + .uses_direct_regs =3D true, +}; + +/* GXLX2 uses the direct register layout with the older GXL PHY setup. */ +static const struct meson_dw_hdmi_data meson_dw_hdmi_gxlx2_data =3D { + .top_read =3D dw_hdmi_g12a_top_read, + .top_write =3D dw_hdmi_g12a_top_write, + .dwc_read =3D dw_hdmi_g12a_dwc_read, + .dwc_write =3D dw_hdmi_g12a_dwc_write, + .cntl0_init =3D 0x0, + .cntl1_init =3D PHY_CNTL1_INIT, + .phy_cntl0_3g =3D 0x33353382, + .uses_direct_regs =3D true, }; =20 static void meson_dw_hdmi_init(struct meson_dw_hdmi *meson_dw_hdmi) @@ -612,8 +631,8 @@ static void meson_dw_hdmi_init(struct meson_dw_hdmi *me= son_dw_hdmi) reset_control_reset(meson_dw_hdmi->hdmitx_ctrl); reset_control_reset(meson_dw_hdmi->hdmitx_phy); =20 - /* Enable APB3 fail on error */ - if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { + /* The APB3 control registers exist only with the indirect interface. */ + if (!meson_dw_hdmi->data->uses_direct_regs) { writel_bits_relaxed(BIT(15), BIT(15), meson_dw_hdmi->hdmitx + HDMITX_TOP_CTRL_REG); writel_bits_relaxed(BIT(15), BIT(15), @@ -769,7 +788,9 @@ static int meson_dw_hdmi_bind(struct device *dev, struc= t device *master, dw_plat_data->disable_cec =3D true; dw_plat_data->output_port =3D 1; =20 - if (dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || + if (dw_hdmi_is_compatible(meson_dw_hdmi, + "amlogic,meson-gxlx2-dw-hdmi") || + dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxl-dw-hdmi") || dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-gxm-dw-hdmi") || dw_hdmi_is_compatible(meson_dw_hdmi, "amlogic,meson-g12a-dw-hdmi")) dw_plat_data->use_drm_infoframe =3D true; @@ -854,6 +875,8 @@ static const struct of_device_id meson_dw_hdmi_of_table= [] =3D { .data =3D &meson_dw_hdmi_gxl_data }, { .compatible =3D "amlogic,meson-gxm-dw-hdmi", .data =3D &meson_dw_hdmi_gxl_data }, + { .compatible =3D "amlogic,meson-gxlx2-dw-hdmi", + .data =3D &meson_dw_hdmi_gxlx2_data }, { .compatible =3D "amlogic,meson-g12a-dw-hdmi", .data =3D &meson_dw_hdmi_g12a_data }, { } --=20 2.43.0