From nobody Sat Jul 25 04:30:46 2026 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63D5F23536B for ; Sat, 18 Jul 2026 04:34:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784349288; cv=none; b=RJwOIH5Z5Wj6/GTU5pdhj2x1M8buV6saXlP94zNP9DMM0Mxj7aI9oFxrG0642li9UcR5R3V3SJpKfvPcWGs28AqioRxx9zGbyIK9H34CXy5M/W4XZ+ICVmoWXmP+BL8TY2sutoJhU4XEN1cPkPl1kGZ+GvIN1fYzK+OonI6fzNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784349288; c=relaxed/simple; bh=Pnj8Sb5z4XifBaDJ4G8lPnb9ksfrvSlyv4D/GknX94M=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=d56oYQXe5OlwiGzHVPxd3/6bVOCz+0Yp3VgknbhAr7iLu4iwSfk4PNfI4nhDgeYC3eo0rfV/3uy3lrB9LMm6TUavAg15bsSiDLyXYgqguJ9tygB1SXbJN0VAi3Upz6bwXkD62tmL7m0fQQM0HcbctqG5hp1OTrtcjLTkP50O0Sg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [111.196.245.140]) by APP-03 (Coremail) with SMTP id rQCowADHzz1cAltqKUkuAA--.9207S2; Sat, 18 Jul 2026 12:34:37 +0800 (CST) From: Pengpeng Hou To: Anup Patel Cc: Pengpeng Hou , Thomas Gleixner , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , =?UTF-8?q?Bj=C3=B6rn=20T=C3=B6pel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH] irqchip/riscv-imsic: Use GENMASK for base address masks Date: Sat, 18 Jul 2026 12:34:36 +0800 Message-ID: <20260718040000.004.929c1ef2-caplitmus-rv@iscas.ac.cn> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowADHzz1cAltqKUkuAA--.9207S2 X-Coremail-Antispam: 1UD129KBjvJXoW7KFWfZr4UWFWktw18uF4rZrb_yoW5JF48pF sxCr4SkrW7AFW0vr4IyrnF9342g3WvyFW5GrW7Can0k3sFyrnFq3Z0kFyfZw1kXr4fZry8 AFs8JryDWa18CFUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9214x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr 1j6F4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02 628vn2kIc2xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4 IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1r MI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJV WUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j 6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYx BIdaVFxhVjvjDU0xZFpf9x0JUZYFZUUUUU= X-CM-SenderInfo: pshqw1xhqjqxpvfd2hldfou0/ Content-Type: text/plain; charset="utf-8" The IMSIC DT binding allows riscv,guest-index-bits up to 7 and riscv,hart-index-bits up to 15. On RV32, guest-index-bits=3D7 and hart-index-bits=3D13, together with the 12-bit IMSIC page offset, is a binding-valid layout that consumes a 32-bit low-address mask. The parser accepts this equality case because it rejects only values larger than the remaining bit budget. The base address canonicalization then builds the low-address mask with BIT(sum) - 1. When sum is 32 on RV32, that expression shifts an unsigned long by its full width. Keep the legal equality layout and express the mask with GENMASK(sum - 1, 0) instead. The existing parser bounds guarantee that sum - 1 is below BITS_PER_LONG at both mask sites. Fixes: 21a8f8a0eb35 ("irqchip: Add RISC-V incoming MSI controller early dri= ver") Signed-off-by: Pengpeng Hou Reviewed-by: Anup Patel --- drivers/irqchip/irq-riscv-imsic-state.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-= riscv-imsic-state.c index b8d1bbbf42f73..9505ddbd9eec9 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "riscv-imsic: " fmt #include #include +#include #include #include #include @@ -769,9 +770,9 @@ static int __init imsic_parse_fwnode(struct fwnode_hand= le *fwnode, return -EINVAL; } global->base_addr =3D res.start; - global->base_addr &=3D ~(BIT(global->guest_index_bits + - global->hart_index_bits + - IMSIC_MMIO_PAGE_SHIFT) - 1); + global->base_addr &=3D ~GENMASK(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT - 1, 0); global->base_addr &=3D ~((BIT(global->group_index_bits) - 1) << global->group_index_shift); =20 @@ -850,9 +851,9 @@ int __init imsic_setup_state(struct fwnode_handle *fwno= de, void *opaque) } =20 base_addr =3D mmios[i].start; - base_addr &=3D ~(BIT(global->guest_index_bits + - global->hart_index_bits + - IMSIC_MMIO_PAGE_SHIFT) - 1); + base_addr &=3D ~GENMASK(global->guest_index_bits + + global->hart_index_bits + + IMSIC_MMIO_PAGE_SHIFT - 1, 0); base_addr &=3D ~((BIT(global->group_index_bits) - 1) << global->group_index_shift); if (base_addr !=3D global->base_addr) { --=20 2.43.0