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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231F.mail.protection.outlook.com (10.167.242.235) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Fri, 17 Jul 2026 22:27:24 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Fri, 17 Jul 2026 17:27:23 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 01/13] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register Date: Fri, 17 Jul 2026 17:26:54 -0500 Message-ID: <20260717222706.3540281-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|PH7PR12MB9256:EE_ X-MS-Office365-Filtering-Correlation-Id: fcbe59d6-60ce-44e4-c1ab-08dee4529398 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|23010399003|376014|7416014|82310400026|18002099003|22082099003|56012099006|10067099003|11063799006; X-Microsoft-Antispam-Message-Info: BH5QyqdR/WbWv5osK423qbI2w2bROVXXIf1J94BVceLLQBp5y43XbTKgWhln/CkmW1jLIqsnIwznkYC3/ASOAl6LmPhth6liqAKBJjdLmDvfIoG0OFsMIDYV6RISiDVvyPq0N6WIQkU+XCmT1hSr1Nya1v1+R6Ujf5INngSqjSGLOFqBieOIHkWxQA5YckY/rn9Q1g9h78pZzmYugK8gaow2xyK4d1ezuhZ0lcFOEEHt9OlSM0TRZn+hPNBAZqD4lm48upkKBLo/Lj/6JhyAY9yQz4OT0enm4cO6ggKIZjXvf7XDGQ8MVyHRJ9/JNmXx1eCFniG4fFzzHXv5e5ZSbiVMpyQVCK/TitPXKkRNywt4I36Zo0hAAINVBDM82QwKwQuUnskLZKzZjDlPzhoLPvhKstnAUIAZYoMrzkC0A6lrXXENtk+8dLnSiyQ2QTdsbKEh0wXsdukBtDRj6739F4SMJXbgNP2E2kJ27e+d8MDIDBsJUoGHQ8+YY2JaPJCEEEQclGErFC0DoDSUI5M7Q5Lio35VBuedAQBP7Q5baKT2s88EJXF0CJ7/Oid8vH+pmJUDRhtKC+cItSJMIUR/PflG909mKVxUZ04lQ1I5sF29GgkqDC5tn1fp4mGwbiSi9+Kb+thrfrATXhiPD6q67bzFlTwBIrcC3HhnvC51PMx2lQlcguqQyUbCxZvGykgFL9c7UnTv1MakbQhiBGPAhQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(23010399003)(376014)(7416014)(82310400026)(18002099003)(22082099003)(56012099006)(10067099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KlTuWe52nXAENRbGDWxSwyAISApgj/ghCD9yGarHdsTmBRKlntv84nZ8mnqnXMQuSNCekWh2VKO3bKENl4JEba8CdWqpHP5USsRPjKwVRJsGNkbaxx+TbSWSDA8ebA2M44/ONCnoPYztao+wSbtlmQvis9+uuaZJa6nTHZ4pQkuMJ7SVscIKrHCcF8+F4/vVofGrVelUVlEUra9vc0Gb9pnyehPTPnuLFmDoK8Krcq5cBOcCVSJ+b5fAfaHuZ9HRfcfTUjSXKUVP7s9I9YM3geTW4qv6lFXLsYjG6R0MXY9lKeHhr9JQlwAoMLhyEWAt/Q0RTkwOgfhkbzStUb0+430NA6IkbiIl/OJrTHbxCl6O5zjXOguHSZPMqDd17/Vc3H73bKR/0ZbQSnG/MX7xcG6eyukKNywT4Soc6LhQU04nBtAEeKco3kaLBxn0S71w X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:27:24.6579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fcbe59d6-60ce-44e4-c1ab-08dee4529398 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9256 Content-Type: text/plain; charset="utf-8" cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable errors as fatal or non-fatal by ANDing uncorrectable status with PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a Root Error Status register bit (bit 6), not a severity bit. ANDing it against uncorrectable status tests a reserved bit and produces incorrect severity classification. Fix by ANDing the unmasked uncor_status against uncor_severity. Per PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable Error Severity register indicates whether the corresponding error is fatal (1) or non-fatal (0). Fixes: 6ac07883dbb5 ("cxl/pci: Add RCH downstream port error logging") Cc: stable@vger.kernel.org Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Reviewed-by: Richard Cheng --- Changes in v17 -> v18: - New patch. --- drivers/cxl/core/ras_rch.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 0a8b3b9b63884..44b335d560708 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -80,7 +80,8 @@ static bool cxl_rch_get_aer_severity(struct aer_capabilit= y_regs *aer_regs, int *severity) { if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { - if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) + if ((aer_regs->uncor_status & ~aer_regs->uncor_mask) & + aer_regs->uncor_severity) *severity =3D AER_FATAL; else *severity =3D AER_NONFATAL; --=20 2.34.1 From nobody Sat Jul 25 04:53:43 2026 Received: from SA9PR02CU001.outbound.protection.outlook.com (mail-southcentralusazon11013016.outbound.protection.outlook.com [40.93.196.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CBE13921CD; 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Fri, 17 Jul 2026 17:27:34 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 02/13] acpi/apei/ghes: Use raw_spinlock_t for CXL CPER work locks Date: Fri, 17 Jul 2026 17:26:55 -0500 Message-ID: <20260717222706.3540281-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002318:EE_|DM4PR12MB6181:EE_ X-MS-Office365-Filtering-Correlation-Id: c59320f9-3c93-4663-8153-08dee4529a7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|1800799024|23010399003|7416014|3023799007|6133799003|56012099006|18002099003|22082099003|11063799006|10067099003; X-Microsoft-Antispam-Message-Info: YN5vL81bNGFLQ7bVqw9LLslgx86wOy0mT557wUAK5/l+vRaQcBt4u+y2PIGlP476wZoW43gG8cIa5d3UeaoKe5gVFXqpdN3MiQVyXQJ2C7Jgl6+lghJKvKGptb8x+0nslSHn7/c80GZo0sqdo27y6rzhqAqcCZNDItdMcjKMCWKS/uSTy/B0n6ovzgR8ZV5JHb8gF9ynKa0yKCy+KG8mjzrGDX74/n/VjF334MCHMcvBS4ledM59wIFOarVkoSzyKd72ZSpleESoAKvhXWQrpqaUCncCqwp9KolpmEAhw0n6a1xtB32eFwknfPYAqhWnrlB46O95jl69kG4gayzhWKitszbkoOlTK2rHU7X4x4VWU743OQicBsUp4RRthEwNB1i2aLQFeaGLQQQIZuRiqyXKRl/YNjIbgTB1/Aw6Glbot94LkaNngRrOFJry8apAwxlO0Y7C0WMyG7qb3k/h1foVTONrQvTffeEJ2M0oWLcVrlpvlN3eTRpRHyIfnb5YVxtVMjzRwye95yZR1n2A0osu2q4VqWi04k+h2XpPpxfqejUEEgBX0EwoRM3iVf4Op/Ip8yXglUGd8OCc96OMnfAdRGNyeRe/FEaZmg7ZdSVjCb8h4cIBuumUw6ZbrsHGR8ycQnNjtrFh6AU+EdMZSVCpAh9GRjtiKtJxTptBCgfAVUzYKOsMYCCkiAZzAAoTg0GYywR496rZ8fqNNnC60Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(376014)(1800799024)(23010399003)(7416014)(3023799007)(6133799003)(56012099006)(18002099003)(22082099003)(11063799006)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wVGK2H80e+/1b70v2F6MTddiKCUgdTmJWWEmnZIUeopDeaThWJdWcN+2ah4xn4Ogqded42ACb+1YqCjrk39k+L/uExDLdxOnUYP56lh6PZEQjb3mxrp1K9JF9reAnimG/3c1ZfvH99XjlBdaHOfIoGwotUq8eSntp6dc/xbhzWadgEHPgXoSDNNMi/iA2TXqdGP55uTUhVgtWA3AGeiZDF7YlNpLeeQAraZbZ876dA0cCJ4LKs9kNxk5w4Aps5WZIkeJfpiPWgy6lp6oI1aotkwMWjA2ugBvvestlZY+8NJzBLJMQ6tjdzuhyJV3nV8fCDIdGMovkF1SeKDhpOgQQU9Ghy/9GpFfVp+ErHhp9xPl4BjOOktlddW71pYTW7xbDklPLHiyv4KCrvKO2c3VdCphZba9pwtHuzDD3gvWIIoKJN9s4pKf1NQYbNLcB63o X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:27:36.2164 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c59320f9-3c93-4663-8153-08dee4529a7b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002318.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6181 Content-Type: text/plain; charset="utf-8" The CXL CPER work registration and unregistration helpers in drivers/acpi/apei/ghes.c acquire cxl_cper_work_lock and cxl_cper_prot_err_work_lock with guard(spinlock), which leaves local interrupts enabled. The corresponding post paths (cxl_cper_post_event(), cxl_cper_post_prot_err()) execute in hard IRQ context (they are called from the GHES error notification path) and acquire the same locks via guard(spinlock_irqsave). If a CPU is holding one of these locks via guard(spinlock) when a GHES interrupt arrives on the same CPU, the IRQ handler spins on the held lock waiting for it to release, while the lock holder is preempted by the IRQ. The result is a deadlock. Convert both locks from spinlock_t to raw_spinlock_t and use guard(raw_spinlock_irqsave) at all call sites. On PREEMPT_RT kernels spinlock_t is backed by rt_mutex and sleeping from hard IRQ context is not permitted; raw_spinlock_t is safe in both contexts. Add WARN_ONCE to both register functions to surface double-registration bugs at runtime. Restructure both unregister functions to clear the global work pointer under the lock before calling cancel_work_sync(), closing the window where a CPER interrupt could schedule work on a pointer about to be freed. Add kfifo_reset() after cancel_work_sync() so stale entries are not replayed on next module load. Both kfifos are single-consumer: only one work_struct is registered at a time, enforced by the WARN_ONCE guard in the register functions. kfifo_reset() is safe outside the lock because cancel_work_sync() has already quiesced the consumer, and no new consumer can register until the current module exit completes and a fresh module init runs. Remove the now-redundant cancel_work_sync() call from cxl_pci_driver_exit() - cxl_cper_unregister_work() handles quiescing internally. Reported-by: Sashiko Signed-off-by: Terry Bowman Fixes: 5e4a264bf8b5 ("acpi/ghes: Process CXL Component Events") Fixes: 36f257e3b0ba ("acpi/ghes, cxl/pci: Process CXL CPER Protocol Errors") Cc: stable@vger.kernel.org Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v17 -> v18: - New patch. --- drivers/acpi/apei/ghes.c | 50 ++++++++++++++++++++++++++-------------- drivers/cxl/pci.c | 1 - 2 files changed, 33 insertions(+), 18 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index 3236a3ce79d6b..ca7a138c1ff2e 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -749,7 +749,7 @@ static DEFINE_KFIFO(cxl_cper_prot_err_fifo, struct cxl_= cper_prot_err_work_data, CXL_CPER_PROT_ERR_FIFO_DEPTH); =20 /* Synchronize schedule_work() with cxl_cper_prot_err_work changes */ -static DEFINE_SPINLOCK(cxl_cper_prot_err_work_lock); +static DEFINE_RAW_SPINLOCK(cxl_cper_prot_err_work_lock); struct work_struct *cxl_cper_prot_err_work; =20 static void cxl_cper_post_prot_err(struct cxl_cper_sec_prot_err *prot_err, @@ -761,7 +761,7 @@ static void cxl_cper_post_prot_err(struct cxl_cper_sec_= prot_err *prot_err, if (cxl_cper_sec_prot_err_valid(prot_err)) return; =20 - guard(spinlock_irqsave)(&cxl_cper_prot_err_work_lock); + guard(raw_spinlock_irqsave)(&cxl_cper_prot_err_work_lock); =20 if (!cxl_cper_prot_err_work) return; @@ -780,10 +780,11 @@ static void cxl_cper_post_prot_err(struct cxl_cper_se= c_prot_err *prot_err, =20 int cxl_cper_register_prot_err_work(struct work_struct *work) { - if (cxl_cper_prot_err_work) - return -EINVAL; + guard(raw_spinlock_irqsave)(&cxl_cper_prot_err_work_lock); =20 - guard(spinlock)(&cxl_cper_prot_err_work_lock); + if (WARN_ONCE(cxl_cper_prot_err_work, + "CPER-CXL kfifo consumer already registered\n")) + return -EINVAL; cxl_cper_prot_err_work =3D work; return 0; } @@ -791,11 +792,18 @@ EXPORT_SYMBOL_NS_GPL(cxl_cper_register_prot_err_work,= "CXL"); =20 int cxl_cper_unregister_prot_err_work(struct work_struct *work) { - if (cxl_cper_prot_err_work !=3D work) - return -EINVAL; + scoped_guard(raw_spinlock_irqsave, &cxl_cper_prot_err_work_lock) { + if (WARN_ONCE(cxl_cper_prot_err_work !=3D work, + "CPER-CXL kfifo consumer mismatch on unregister\n")) + return -EINVAL; + cxl_cper_prot_err_work =3D NULL; + } + + cancel_work_sync(work); + + /* Discard stale entries so they are not replayed on next module load */ + kfifo_reset(&cxl_cper_prot_err_fifo); =20 - guard(spinlock)(&cxl_cper_prot_err_work_lock); - cxl_cper_prot_err_work =3D NULL; return 0; } EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_prot_err_work, "CXL"); @@ -811,7 +819,7 @@ EXPORT_SYMBOL_NS_GPL(cxl_cper_prot_err_kfifo_get, "CXL"= ); DEFINE_KFIFO(cxl_cper_fifo, struct cxl_cper_work_data, CXL_CPER_FIFO_DEPTH= ); =20 /* Synchronize schedule_work() with cxl_cper_work changes */ -static DEFINE_SPINLOCK(cxl_cper_work_lock); +static DEFINE_RAW_SPINLOCK(cxl_cper_work_lock); struct work_struct *cxl_cper_work; =20 static void cxl_cper_post_event(enum cxl_event_type event_type, @@ -831,7 +839,7 @@ static void cxl_cper_post_event(enum cxl_event_type eve= nt_type, return; } =20 - guard(spinlock_irqsave)(&cxl_cper_work_lock); + guard(raw_spinlock_irqsave)(&cxl_cper_work_lock); =20 if (!cxl_cper_work) return; @@ -849,10 +857,11 @@ static void cxl_cper_post_event(enum cxl_event_type e= vent_type, =20 int cxl_cper_register_work(struct work_struct *work) { - if (cxl_cper_work) + guard(raw_spinlock_irqsave)(&cxl_cper_work_lock); + if (WARN_ONCE(cxl_cper_work, + "CXL CPER kfifo consumer already registered\n")) return -EINVAL; =20 - guard(spinlock)(&cxl_cper_work_lock); cxl_cper_work =3D work; return 0; } @@ -860,11 +869,18 @@ EXPORT_SYMBOL_NS_GPL(cxl_cper_register_work, "CXL"); =20 int cxl_cper_unregister_work(struct work_struct *work) { - if (cxl_cper_work !=3D work) - return -EINVAL; + scoped_guard(raw_spinlock_irqsave, &cxl_cper_work_lock) { + if (WARN_ONCE(cxl_cper_work !=3D work, + "CXL CPER kfifo consumer mismatch on unregister\n")) + return -EINVAL; + cxl_cper_work =3D NULL; + } + + cancel_work_sync(work); + + /* Discard stale entries so they are not replayed on next module load */ + kfifo_reset(&cxl_cper_fifo); =20 - guard(spinlock)(&cxl_cper_work_lock); - cxl_cper_work =3D NULL; return 0; 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Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 03/13] cxl: Tighten CPER kfifo registration API and symbol visibility Date: Fri, 17 Jul 2026 17:26:56 -0500 Message-ID: <20260717222706.3540281-4-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231C:EE_|DS0PR12MB7727:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b94d1b1-a522-4436-2ea8-08dee452a149 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700016|23010399003|7416014|376014|10067099003|3023799007|11063799006|6133799003|22082099003|56012099006|18002099003; X-Microsoft-Antispam-Message-Info: 8u8NEYsC3R9wlJalAhtJd0l7QlLYpxVTy3YKwQpvVU4QakDneyJE4l/YYDpfn7BTyiQn9L0YpMuHC0V36Bfmau2nhVPQe0HoUuowufZqNVjxw0UG/jRrvWSORMrXTnVGkO30FVMUQ74Gp3szCiaFsBZSX3aA4SOOPG+4SMWHI8r0arOiKS+Ix/nhC97bUwDc8sfj1NHkNfKA5BeDKq8ByY2vzXn6cQgodGUpUisdLl739lKsZLWaNnzr+IE5loGHS5ZPuZU8jNq/pvCrHLMQ+rLMFzfne0QobpH2j47vr9vPzrS2zIovsSZ0gYY4mhsN95eaWPoNUAUWgrEukEn0iPicY7SkCW8ML4v6E/u+ed9AEidbRlUiaDFOJtzHAm9xT6FoV+tFukqkrrlXG75GvZ/vXkygdl6/JLSnh24+0/qIlNOUHiJLrhAc1pS9Nm3pskL7CmW4BfDp+/V4f0evzNaA5ttZgP4wVs02Us58lhlDDUKOwfXO/t0idWvmGQItzko7FAsNGcXpar1g13zMD8ZXCYg16H/jy4KHOEoixXWOZDNEv0nkzDXVyP8W7ADYcs1GFGjLLxC0X9LuWiaY3kELBBs2rrg3XMUm8reONPrOAKkov2mODzq4eYvRTk7xh8Dm0qcGzVWMbGfd5K/Gt0RhwIWuRf68TesmQl8eAlyO26SvfmqYWHuWeUkA7shUXq7CEGntTZDFe/m8wG+ayQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(23010399003)(7416014)(376014)(10067099003)(3023799007)(11063799006)(6133799003)(22082099003)(56012099006)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OBRHjYwqMsrrL7BmNVbv/dGW19ahGPeiHhkIY5qGHxHbzQ4T4AM7mr4EBzgemMf3G3iC6igV59c0RGVha1dyAYDiiEtDxg4jlacf4EDJfeXhFrf7z8++r9hEIAwTh013LtcimXZXxZ7UxDxKGAlIWbLOc0s1iSUdhCLxrFDTf69kuO/B/LdHbJnBPKQk+cw1oe7dc+caqzDvskMwBs6xStkwFSmF0BugyBI/s4FfvPECT3A5n3l2CWzJPIUdpqCJZdopO50nhR7dH9isN6eL5FyRKM/mahhhwK1CKNywA0u/KO+HXZ74NF47t8O0OqSXC+w0igCkTkdtu2KSVEaFo3kypoo19lUDIygOk/GWgMxnoj6/bLKzKaPK0eUoFPrkSUnJK+9Tt74tYVY+qdTQlWQgsSMvQL+6ktxPz9v9610ht/SyA1vd1dqz1iLw5N7m X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:27:47.6296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b94d1b1-a522-4436-2ea8-08dee452a149 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7727 Content-Type: text/plain; charset="utf-8" From: Dan Williams Tighten the CPER protocol error kfifo registration API and symbol visibility. Use EXPORT_SYMBOL_FOR_MODULES() instead of EXPORT_SYMBOL_NS_GPL() for the CPER kfifo registration symbols. This names the consuming module explicitly and gives compile-time enforcement. Drop the work_struct argument from the unregister path. Change the WARN_ONCE condition to a NULL check since there is no caller pointer to compare against anymore. Change register/unregister return types to void. Flag double registration with WARN_ONCE() inside the lock instead of returning an error. Change cxl_ras_init() to void because there is one consumer and one producer so the error return was unnecessary. Remove the now-dead error check in cxl_core_init(). Add a diagnostic log when the driver is not bound in cxl_cper_handle_prot_err(). Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Dan Williams Reviewed-by: Dave Jiang --- Changes in v17 -> v18: - New patch. --- drivers/acpi/apei/ghes.c | 32 +++++++++++++++----------------- drivers/cxl/core/core.h | 7 ++----- drivers/cxl/core/port.c | 6 +----- drivers/cxl/core/ras.c | 12 +++++++----- include/cxl/event.h | 17 ++++++----------- 5 files changed, 31 insertions(+), 43 deletions(-) diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c index ca7a138c1ff2e..187f54e31c33e 100644 --- a/drivers/acpi/apei/ghes.c +++ b/drivers/acpi/apei/ghes.c @@ -778,41 +778,41 @@ static void cxl_cper_post_prot_err(struct cxl_cper_se= c_prot_err *prot_err, #endif } =20 -int cxl_cper_register_prot_err_work(struct work_struct *work) +void cxl_cper_register_prot_err_work(struct work_struct *work) { guard(raw_spinlock_irqsave)(&cxl_cper_prot_err_work_lock); =20 if (WARN_ONCE(cxl_cper_prot_err_work, "CPER-CXL kfifo consumer already registered\n")) - return -EINVAL; + return; cxl_cper_prot_err_work =3D work; - return 0; } -EXPORT_SYMBOL_NS_GPL(cxl_cper_register_prot_err_work, "CXL"); +EXPORT_SYMBOL_FOR_MODULES(cxl_cper_register_prot_err_work, "cxl_core"); =20 -int cxl_cper_unregister_prot_err_work(struct work_struct *work) +void cxl_cper_unregister_prot_err_work(void) { + struct work_struct *old; + scoped_guard(raw_spinlock_irqsave, &cxl_cper_prot_err_work_lock) { - if (WARN_ONCE(cxl_cper_prot_err_work !=3D work, - "CPER-CXL kfifo consumer mismatch on unregister\n")) - return -EINVAL; + WARN_ONCE(!cxl_cper_prot_err_work, + "CPER-CXL kfifo consumer not registered on unregister\n"); + old =3D cxl_cper_prot_err_work; cxl_cper_prot_err_work =3D NULL; } =20 - cancel_work_sync(work); + if (old) + cancel_work_sync(old); =20 /* Discard stale entries so they are not replayed on next module load */ kfifo_reset(&cxl_cper_prot_err_fifo); - - return 0; } -EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_prot_err_work, "CXL"); +EXPORT_SYMBOL_FOR_MODULES(cxl_cper_unregister_prot_err_work, "cxl_core"); =20 int cxl_cper_prot_err_kfifo_get(struct cxl_cper_prot_err_work_data *wd) { return kfifo_get(&cxl_cper_prot_err_fifo, wd); } -EXPORT_SYMBOL_NS_GPL(cxl_cper_prot_err_kfifo_get, "CXL"); +EXPORT_SYMBOL_FOR_MODULES(cxl_cper_prot_err_kfifo_get, "cxl_core"); =20 /* Room for 8 entries for each of the 4 event log queues */ #define CXL_CPER_FIFO_DEPTH 32 @@ -867,12 +867,12 @@ int cxl_cper_register_work(struct work_struct *work) } EXPORT_SYMBOL_NS_GPL(cxl_cper_register_work, "CXL"); =20 -int cxl_cper_unregister_work(struct work_struct *work) +void cxl_cper_unregister_work(struct work_struct *work) { scoped_guard(raw_spinlock_irqsave, &cxl_cper_work_lock) { if (WARN_ONCE(cxl_cper_work !=3D work, "CXL CPER kfifo consumer mismatch on unregister\n")) - return -EINVAL; + return; cxl_cper_work =3D NULL; } =20 @@ -880,8 +880,6 @@ int cxl_cper_unregister_work(struct work_struct *work) =20 /* Discard stale entries so they are not replayed on next module load */ kfifo_reset(&cxl_cper_fifo); - - return 0; } EXPORT_SYMBOL_NS_GPL(cxl_cper_unregister_work, "CXL"); =20 diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 07555ae638594..23fe40ddf4c6b 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -183,7 +183,7 @@ static inline struct device *dport_to_host(struct cxl_d= port *dport) return &port->dev; } #ifdef CONFIG_CXL_RAS -int cxl_ras_init(void); +void cxl_ras_init(void); void cxl_ras_exit(void); bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); @@ -192,10 +192,7 @@ void cxl_disable_rch_root_ints(struct cxl_dport *dport= ); void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); #else -static inline int cxl_ras_init(void) -{ - return 0; -} +static inline void cxl_ras_init(void) { } static inline void cxl_ras_exit(void) { } static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) { diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 1215ee4f40351..f90f899c31d07 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -2531,14 +2531,10 @@ static __init int cxl_core_init(void) if (rc) goto err_region; =20 - rc =3D cxl_ras_init(); - if (rc) - goto err_ras; + cxl_ras_init(); =20 return 0; =20 -err_ras: - cxl_region_exit(); err_region: bus_unregister(&cxl_bus_type); err_bus: diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 99fb00949c2fa..135f1997e6f4f 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -104,8 +104,11 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err= _work_data *data) } =20 guard(device)(&pdev->dev); - if (!pdev->dev.driver) + if (!pdev->dev.driver) { + dev_warn_ratelimited(&pdev->dev, + "Device is unbound, abort CPER error handling\n"); return; + } =20 struct device *mem_dev __free(put_device) =3D bus_find_device( &cxl_bus_type, NULL, pdev, match_memdev_by_parent); @@ -129,15 +132,14 @@ static void cxl_cper_prot_err_work_fn(struct work_str= uct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 -int cxl_ras_init(void) +void cxl_ras_init(void) { - return cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); + cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); } =20 void cxl_ras_exit(void) { - cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work); - cancel_work_sync(&cxl_cper_prot_err_work); + cxl_cper_unregister_prot_err_work(); } =20 static void cxl_dport_map_ras(struct cxl_dport *dport) diff --git a/include/cxl/event.h b/include/cxl/event.h index ff97fea718d2c..3471d4f75c025 100644 --- a/include/cxl/event.h +++ b/include/cxl/event.h @@ -287,10 +287,10 @@ struct cxl_cper_prot_err_work_data { =20 #ifdef CONFIG_ACPI_APEI_GHES int cxl_cper_register_work(struct work_struct *work); -int cxl_cper_unregister_work(struct work_struct *work); +void cxl_cper_unregister_work(struct work_struct *work); int cxl_cper_kfifo_get(struct cxl_cper_work_data *wd); -int cxl_cper_register_prot_err_work(struct work_struct *work); -int cxl_cper_unregister_prot_err_work(struct work_struct *work); +void cxl_cper_register_prot_err_work(struct work_struct *work); +void cxl_cper_unregister_prot_err_work(void); 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Fri, 17 Jul 2026 17:27:57 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 04/13] cxl: Rename find_cxl_port() to find_cxl_port_by_dport() Date: Fri, 17 Jul 2026 17:26:57 -0500 Message-ID: <20260717222706.3540281-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231E:EE_|SA1PR12MB7442:EE_ X-MS-Office365-Filtering-Correlation-Id: 941bccf6-d9dc-496c-9519-08dee452a820 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|23010399003|1800799024|36860700016|6133799003|3023799007|56012099006|10067099003|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: RakSHDiV2T9lp8IoPY5eKY300pLtT6yfScXvom5WMst9m2z5+Ld8fDXEWG0vXgXIuIET99123b3MQO6EyBoe5wwK3ilgxo8fANibFjnj/8fma4xBM05wvsZF9p5d8vuVyehjDw/5IE/4hT1urS1VHkTf8D+KHQ6I1ZYmJAQZJVNkL/L82bfo5B9dqWwpsnXp0db9qLtlJuVRjfx2KDoRqYLQ5VbWPOmLpgjD2zw8Yu6M/TXtjTW+GsHAz6qTqdoa8ALPwR8HPeCxFY1zM3/+lSI5uuKpZvPHPdA42QzHu+2hup1TAbEs/CHlGp7s4NGW1ehBk4tUbRGoGLQRPYHvbjT8bggdqls8J1+l0XCnTUrYAZa9ck/+dpg6hyAIGE2/ldGyj4YSiM9CfQZ8YKoS/gPn6fUd35rT7WHjjeNFTXV9aaYWrqleFwzl48zacRUuhH1r38f4TTdb7zGMRnDX4Duk/0l21jVq2qurdDWljCyBpr/g93b702pBP65xS4zv7BUN/UhaaklQq+tTM2gbeqyYtcAJ58p9xPYsFaiUktsJFf15ywLiZMTAwvkejmZqpUMvHecL8F+1QKLhO/Huqz5yr1hTZqL+oxytXltKr4lQNtUKuQnkw9JCmD/C0/i+VvGKATVFlQ2vPjdUtT6k2RMXTqVMSUActu5oXwam6DMvi7H/vQFTHi93Cr5Y1R848cxjS7uOn44l55vWrxlpqA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(23010399003)(1800799024)(36860700016)(6133799003)(3023799007)(56012099006)(10067099003)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5MwJ1O27XI183tAFPdEzQfKHdxUHgvicV2yfMWOkMVskxyjfVIytIoeBeqjT5SUoIiM41t4xmNLhBc0CS7NgESmqfR9vxqwJhh6IbJKxCDBt59WKXZJ3CftLtXQuGYG49j8SrIj3RWFUDTj9JOj1A6lMA1Uyh0KiXMXp/ILsMPtOEw5ScaxO0ONr/LoCpxlFPCGutWnORa8VOVv7kMJR1w6HhYjwaZgBjLMyRPBM+bCkpz+F9Kepyj8/tFgwRpf5rY5mQ0EqX2pchEcipvxiAUpXoSkunJeX7HBemDvCR9eSMwtFzbAcpLsl3ek30IOHVUmvjMzNnbwuhV/B48vhyd/dzz0Nfl6XnXiomRvyXhBeI8sO2tqtUmSGfH9u/uoAT7ltuuwEJ/Sf47pHleyf3Goizo4axLJl5lXwCjmD9eF9QVnsuJVIcFqopOL43qcl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:27:59.1077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 941bccf6-d9dc-496c-9519-08dee452a820 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7442 Content-Type: text/plain; charset="utf-8" From: Dan Williams find_cxl_port() and find_cxl_port_by_uport() are internal port lookup functions that search the CXL bus by dport and uport respectively, but their names do not make the lookup method clear. Rename find_cxl_port() to find_cxl_port_by_dport() to make the lookup method explicit and consistent with find_cxl_port_by_uport(). Both functions remain static to port.c; the upcoming patch that adds the first cross-file caller will widen their scope. Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Dan Williams Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v17 -> v18: - New commit --- drivers/cxl/core/port.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index f90f899c31d07..cadb51f70f854 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1379,7 +1379,7 @@ static int match_port_by_dport(struct device *dev, co= nst void *data) return dport !=3D NULL; } =20 -static struct cxl_port *__find_cxl_port(struct cxl_find_port_ctx *ctx) +static struct cxl_port *__find_cxl_port_by_dport(struct cxl_find_port_ctx = *ctx) { struct device *dev; =20 @@ -1392,8 +1392,16 @@ static struct cxl_port *__find_cxl_port(struct cxl_f= ind_port_ctx *ctx) return NULL; } =20 -static struct cxl_port *find_cxl_port(struct device *dport_dev, - struct cxl_dport **dport) +/** + * find_cxl_port_by_dport - find a cxl_port by one of its targets + * @dport_dev: device representing the dport target + * @dport: optional output of the 'struct cxl_dport' companion of the @dpo= rt_dev + * + * Return a 'struct cxl_port' with an elevated reference if found. Use + * __free(put_cxl_port) to release. + */ +static struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, @@ -1401,7 +1409,7 @@ static struct cxl_port *find_cxl_port(struct device *= dport_dev, }; struct cxl_port *port; =20 - port =3D __find_cxl_port(&ctx); + port =3D __find_cxl_port_by_dport(&ctx); return port; } =20 @@ -1895,14 +1903,14 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_enumerate_ports, "CXL= "); struct cxl_port *cxl_pci_find_port(struct pci_dev *pdev, struct cxl_dport **dport) { - return find_cxl_port(pdev->dev.parent, dport); + return find_cxl_port_by_dport(pdev->dev.parent, dport); } EXPORT_SYMBOL_NS_GPL(cxl_pci_find_port, "CXL"); =20 struct cxl_port *cxl_mem_find_port(struct cxl_memdev *cxlmd, struct cxl_dport **dport) { - return find_cxl_port(grandparent(&cxlmd->dev), dport); + return find_cxl_port_by_dport(grandparent(&cxlmd->dev), dport); } EXPORT_SYMBOL_NS_GPL(cxl_mem_find_port, "CXL"); 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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231B.mail.protection.outlook.com (10.167.242.232) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Fri, 17 Jul 2026 22:28:10 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Fri, 17 Jul 2026 17:28:09 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 05/13] PCI/AER: Introduce AER-CXL protocol error kfifo Date: Fri, 17 Jul 2026 17:26:58 -0500 Message-ID: <20260717222706.3540281-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231B:EE_|MW4PR12MB7439:EE_ X-MS-Office365-Filtering-Correlation-Id: c05c2af9-9fe3-483c-650f-08dee452aec4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|7416014|23010399003|376014|22082099003|18002099003|10067099003|3023799007|56012099006|11063799006|6133799003; X-Microsoft-Antispam-Message-Info: jXT55tLVbCZRfWEVwP5UB0CSzqLULPXja18jJehaesAcLkql6r7+pm6ZBOca9GG0/3HNgZbSotz9JcjQMhz+k6NMb5DpqcNVzmA0jbC79/5MmycZTrGH8gtQSbWu7Y5KrJhqrB4ZtNyBpSORSQeM3icqR/ey9Xu6v15lEUW8EvdFWdpwiY7PnhZJjH5fRwI2wltT6q3VuxGN5Hme6VsT6KPXVM7rfO8V95pg3fY7VS6AX5Z/ZE2jp/+jmADYIJ2gfcH3CaRUKKDFePbKD3S77soCWgwPiuC0DMZRBv9pJRd12lOCiV/kcRgHyHK7B+e+Zpf38gnWsL1w8iv7J4rNtQUymiqpZX1zPdZFy6+w/j9FDxhkSgGL8jUv51u2SialMVkC+BtuhMSeaHqIAdvhuQuFDSf48QKEPGmpVeLg3Sd9TIHmmIzrzxdhlyjq6SnVsXH+EEjVshnkbc0QDEe346F6ffs/mvHqy/R5pPwYJn2GLR0goMCysIk2mv2QDBG7yCdXootnL7kI1vQxj5p8Hiu7N2i0p41gn33zgIKRcjYP8hm52N3d6F1SMRv2lNThoPBZMSNGSEk9zXc/RM+BDq8Kph39PfVj5bMjhNQYOIb0AFN/eViGm1HfjvyJMl0JoV8PRNX8Asbu4wW7fjKnZ/6PYJnoPJZzdr4Ec1sta+aiPrAeG2pIh6IDYDw6e+Y3TOZz1JyGqUutDqfPYQ1DXQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(7416014)(23010399003)(376014)(22082099003)(18002099003)(10067099003)(3023799007)(56012099006)(11063799006)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fydtEwRMTE1AXq3aHJD3Q77KEYf29n0rnHFiFOUPV4c4HePHEtF89lTc06uMZbkFRqS1mbx3xD78YoW/mQjaC5R8ogEp4TQQh+vC2oLMHXu/LDs8ofGYGfjNABJgllUFU/7tEDCOem00w9U4owBQDgDiW6RPc8Yd5J1IcZeKbxZ55NEXK5zpZThRdDjkjQUGpCQp36DaGH6/vvo2RIs15PM40GQmLITRYmMZIX146SbElEACOtml4g+erw6JyleiYqMXJ2THc/uQ9pslbCQ315f3Amm0aUiONKejRmgC2t6+rK9y70+8uyM9vgNrON8BE0wRf/T7kYv/kizNj7lhd0pP/mfs2OZ3pp+5rjs53YYN7VGpdlBmTbNioyI5vq1k8bx+TDW5sFUeAtdDfCK2iiAHvVQlFJ85OHX7k2djd6rIiAGq+vhAEW+LzVsfdIpY X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:28:10.2730 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c05c2af9-9fe3-483c-650f-08dee452aec4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7439 Content-Type: text/plain; charset="utf-8" CXL VH RAS handling requires a path for the AER driver to hand off CXL protocol errors to cxl_core for logging and recovery before PCIe AER recovery tears down the device. Add drivers/pci/pcie/aer_cxl_vh.c to implement this handoff via a kfifo-backed work item. Introduce is_aer_internal_error() to identify CXL protocol errors from AER internal error status bits across both correctable and uncorrectable severities. Introduce is_cxl_error() to gate the VH kfifo path. Introduce struct cxl_proto_err_work_data to carry the error source PCI device and severity through the kfifo. Encapsulate the kfifo, per-producer spinlock, registration rwsem, and work pointer in struct cxl_proto_err_kfifo. Initialize the embedded kfifo via INIT_KFIFO() from a subsys_initcall so its metadata is populated before any producer or consumer runs. Introduce cxl_forward_error() to enqueue a CXL protocol error. A reference is taken on the PCI device; the consumer releases it via for_each_cxl_proto_err(). On enqueue failure the reference is released immediately, the error is dropped, and the consumer is scheduled to drain existing entries. A subsequent patch wires cxl_forward_error() into handle_error_source() where correctable and uncorrectable status clearing is left to pci_aer_handle_error(). Introduce cxl_proto_err_flush() to synchronously wait for the consumer worker to drain the kfifo. A subsequent patch wires this into handle_error_source() for UCE events so the CXL plane completes error handling and panic policy before pci_aer_handle_error() drives PCIe recovery. Introduce cxl_register_proto_err_work() and cxl_unregister_proto_err_work() for cxl_core to register and deregister its work handler. On unregistration, pending kfifo entries are drained and their pdev references released before cancel_work_sync() runs. Export these and for_each_cxl_proto_err() via EXPORT_SYMBOL_FOR_MODULES restricted to cxl_core. Protect the work pointer with a rwsem to correctly serialize registration, deregistration, enqueue, and dequeue against concurrent AER IRQ threads. Serialize concurrent kfifo writers with a spinlock. Add MAINTAINERS entries for aer_cxl_vh.c and aer_cxl_rch.c under the CXL entry so CXL maintainers are CC'd on changes to the AER-CXL bridging code. Co-developed-by: Dan Williams Signed-off-by: Dan Williams Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang --- Changes in v17->v18: - Remove correctable status clear from cxl_forward_error(); the AER core clears all status bits via pci_aer_handle_error() info->status writeback - Schedule consumer on kfifo overflow so existing entries can be drained Changes in v16->v17: - Reword "kfifo semaphore" to "kfifo spinlock" to match fifo_lock. - Defer the handle_error_source() is_cxl_error() switch to the patch that registers the kfifo consumer to keep each commit bisect-safe. - Rename rwsema to rwsem - Change CPER exports to use EXPORT_SYMBOL_FOR_MODULES. - Add work cancel function. - Replace kfifo_put() with kfifo_in_spinlocked() for multiple producers - Add fifo_lock spinlock for concurrent producer serialisation - Initialize the embedded kfifo with INIT_KFIFO() in a subsys_initcall so kfifo->mask, ->esize and ->data are set before first use. - Clear PCI_ERR_COR_STATUS in cxl_forward_error() after enqueue so the device is acked for correctable events even when the consumer drops the event. Uncorrectable status is left for cxl_do_recovery() to clear after recovery completes, mirroring the AER core convention. - WARN on double-registration in cxl_register_proto_err_work() to make an unintended second consumer visible at runtime. - Add direct rwsem.h, cleanup.h and workqueue.h includes for symbols used in aer_cxl_vh.c - Add MAINTAINERS entries for drivers/pci/pcie/aer_cxl_*.c - Update message --- MAINTAINERS | 2 + drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/aer.c | 10 -- drivers/pci/pcie/aer_cxl_vh.c | 221 ++++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.h | 6 + include/linux/aer.h | 24 ++++ 6 files changed, 254 insertions(+), 10 deletions(-) create mode 100644 drivers/pci/pcie/aer_cxl_vh.c diff --git a/MAINTAINERS b/MAINTAINERS index 806bd2d80d153..39007aa90b20f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6526,6 +6526,8 @@ S: Maintained F: Documentation/driver-api/cxl F: Documentation/userspace-api/fwctl/fwctl-cxl.rst F: drivers/cxl/ +F: drivers/pci/pcie/aer_cxl_rch.c +F: drivers/pci/pcie/aer_cxl_vh.c F: include/cxl/ F: include/uapi/linux/cxl_mem.h F: tools/testing/cxl/ diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index b0b43a18c304b..62d3d3c69a5df 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -9,6 +9,7 @@ obj-$(CONFIG_PCIEPORTBUS) +=3D pcieportdrv.o bwctrl.o obj-y +=3D aspm.o obj-$(CONFIG_PCIEAER) +=3D aer.o err.o tlp.o obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_rch.o +obj-$(CONFIG_CXL_RAS) +=3D aer_cxl_vh.o obj-$(CONFIG_PCIEAER_INJECT) +=3D aer_inject.o obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index c4fd9c0b2a548..c5bce25df51cb 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1150,16 +1150,6 @@ void pci_aer_unmask_internal_errors(struct pci_dev *= dev) */ EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); =20 -#ifdef CONFIG_CXL_RAS -bool is_aer_internal_error(struct aer_err_info *info) -{ - if (info->severity =3D=3D AER_CORRECTABLE) - return info->status & PCI_ERR_COR_INTERNAL; - - return info->status & PCI_ERR_UNC_INTN; -} -#endif - /** * pci_aer_handle_error - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c new file mode 100644 index 0000000000000..93bed07936100 --- /dev/null +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright(c) 2026 AMD Corporation. All rights reserved. */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "../pci.h" +#include "portdrv.h" + +#define CXL_ERROR_SOURCES_MAX 128 + +struct cxl_proto_err_kfifo { + struct work_struct *work; + void (*flush)(void); + struct rw_semaphore rwsem; + spinlock_t fifo_lock; + atomic_t flush_inflight; + DECLARE_KFIFO(fifo, struct cxl_proto_err_work_data, + CXL_ERROR_SOURCES_MAX); +}; + +static struct cxl_proto_err_kfifo cxl_proto_err_kfifo =3D { + .rwsem =3D __RWSEM_INITIALIZER(cxl_proto_err_kfifo.rwsem), + .fifo_lock =3D __SPIN_LOCK_UNLOCKED(cxl_proto_err_kfifo.fifo_lock), +}; + +static int __init cxl_proto_err_kfifo_init(void) +{ + INIT_KFIFO(cxl_proto_err_kfifo.fifo); + return 0; +} +subsys_initcall(cxl_proto_err_kfifo_init); + +bool is_aer_internal_error(struct aer_err_info *info) +{ + if (info->severity =3D=3D AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} + +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + if (!info || !info->is_cxl) + return false; + + if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + return false; + + return is_aer_internal_error(info); +} + +/** + * cxl_forward_error - Forward a CXL protocol error to the CXL subsystem v= ia kfifo + * @pdev: PCI device that reported the AER error + * @info: AER error info containing severity and status + * + * Producer side of the AER-CXL kfifo. Enqueues a CXL protocol error work + * item and schedules the consumer workqueue. Takes a reference on @pdev + * that the consumer releases after handling. + * + * Return: true if the caller must flush the kfifo before AER recovery, + * false if no CXL error handling was initiated due to early return on + * error. + */ +bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info) +{ + struct cxl_proto_err_work_data wd =3D { + .severity =3D info->severity, + .pdev =3D pdev, + }; + + guard(rwsem_read)(&cxl_proto_err_kfifo.rwsem); + + if (!cxl_proto_err_kfifo.work) { + dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo reader not registered\n"); + return false; + } + + /* + * Reference discipline: the AER caller (handle_error_source()) + * holds a ref on @pdev for the duration of this call and releases + * it on return. Take a fresh ref here so the pdev stays live while + * queued in the kfifo; the consumer (for_each_cxl_proto_err()) + * drops that ref after handling. On enqueue failure below, drop + * the ref we just took to avoid a leak. + */ + pci_dev_get(pdev); + + /* Serialize concurrent kfifo writers: multiple AER threaded IRQs */ + if (!kfifo_in_spinlocked(&cxl_proto_err_kfifo.fifo, &wd, 1, + &cxl_proto_err_kfifo.fifo_lock)) { + /* Dropped; no panic - UCE unconfirmed without RAS read */ + dev_err_ratelimited(&pdev->dev, "AER-CXL kfifo add failed\n"); + pci_dev_put(pdev); + schedule_work(cxl_proto_err_kfifo.work); + return true; + } + + schedule_work(cxl_proto_err_kfifo.work); + return true; +} + +void cxl_register_proto_err_work(struct work_struct *work, + void (*flush)(void)) +{ + guard(rwsem_write)(&cxl_proto_err_kfifo.rwsem); + + /* + * Warn on double-registration to surface driver bugs (e.g. missing + * cxl_unregister_proto_err_work() on module exit) + */ + if (WARN(cxl_proto_err_kfifo.work, + "AER-CXL kfifo consumer already registered\n")) + return; + cxl_proto_err_kfifo.work =3D work; + cxl_proto_err_kfifo.flush =3D flush; +} +EXPORT_SYMBOL_FOR_MODULES(cxl_register_proto_err_work, "cxl_core"); + +static struct work_struct *cancel_cxl_proto_err(void) +{ + struct work_struct *work; + struct cxl_proto_err_work_data wd; + + guard(rwsem_write)(&cxl_proto_err_kfifo.rwsem); + work =3D cxl_proto_err_kfifo.work; + cxl_proto_err_kfifo.work =3D NULL; + cxl_proto_err_kfifo.flush =3D NULL; + + /* rwsem_write excludes all producers; fifo_lock not needed */ + while (kfifo_get(&cxl_proto_err_kfifo.fifo, &wd)) { + dev_err_ratelimited(&wd.pdev->dev, + "AER-CXL error report canceled\n"); + pci_dev_put(wd.pdev); + } + return work; +} + +void cxl_unregister_proto_err_work(void) +{ + struct work_struct *work; + + lockdep_assert_not_held(&cxl_proto_err_kfifo.rwsem); + + work =3D cancel_cxl_proto_err(); + + /* Wait for any in-flight cxl_proto_err_flush() calls to complete */ + wait_var_event(&cxl_proto_err_kfifo.flush_inflight, + atomic_read(&cxl_proto_err_kfifo.flush_inflight) =3D=3D 0); + + if (work) + cancel_work_sync(work); +} +EXPORT_SYMBOL_FOR_MODULES(cxl_unregister_proto_err_work, "cxl_core"); + +/** + * for_each_cxl_proto_err - Call a function for each kfifo work item + * + * Single-consumer invariant: this function is only called from + * cxl_proto_err_work_fn() via a single DECLARE_WORK. + * + * Holds rwsem_read internally; fn() must not call cxl_register_proto_err_= work() + * or cxl_unregister_proto_err_work(). + */ +void for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd, + cxl_proto_err_fn_t fn) +{ + guard(rwsem_read)(&cxl_proto_err_kfifo.rwsem); + while (kfifo_get(&cxl_proto_err_kfifo.fifo, wd)) { + fn(wd); + pci_dev_put(wd->pdev); + } +} +EXPORT_SYMBOL_FOR_MODULES(for_each_cxl_proto_err, "cxl_core"); + +/** + * cxl_proto_err_flush - drain pending AER-CXL kfifo work synchronously + * + * Wait for the consumer worker to finish processing all entries + * currently in the kfifo. Used by handle_error_source() for UCE so + * the CXL plane can read CXL RAS, apply panic policy, and clear CXL + * state before pci_aer_handle_error() drives PCIe recovery. + * + * Snapshots the flush callback under rwsem_read and releases the rwsem + * before calling it. This avoids holding rwsem_read across flush_work(), + * which would deadlock via the rwsem HANDOFF mechanism when a concurrent + * rwsem_write waiter (cxl_unregister_proto_err_work) blocks new readers + * including the worker's for_each_cxl_proto_err() rwsem_read acquisition. + * + * The flush_inflight counter prevents cxl_core module unload while a + * flush is in progress outside the rwsem. The counter is incremented + * under rwsem_read (mutually exclusive with the rwsem_write in + * cancel_cxl_proto_err() that NULLs the flush pointer) and decremented + * after the flush completes. cxl_unregister_proto_err_work() waits for + * the counter to reach zero before proceeding with cancel_work_sync(). + * + * For correctable events the consumer can run asynchronously; AER + * does not need to call this helper for AER_CORRECTABLE. + */ +void cxl_proto_err_flush(void) +{ + void (*flush)(void); + + scoped_guard(rwsem_read, &cxl_proto_err_kfifo.rwsem) { + flush =3D cxl_proto_err_kfifo.flush; + if (flush) + atomic_inc(&cxl_proto_err_kfifo.flush_inflight); + } + + if (flush) { + flush(); + if (atomic_dec_and_test(&cxl_proto_err_kfifo.flush_inflight)) + wake_up_var(&cxl_proto_err_kfifo.flush_inflight); + } +} diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index cc58bf2f2c844..fd203010877bf 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -130,9 +130,15 @@ struct aer_err_info; bool is_aer_internal_error(struct aer_err_info *info); void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); void cxl_rch_enable_rcec(struct pci_dev *rcec); +bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info *info); +bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_info *info); +void cxl_proto_err_flush(void); #else static inline bool is_aer_internal_error(struct aer_err_info *info) { retu= rn false; } static inline void cxl_rch_handle_error(struct pci_dev *dev, struct aer_er= r_info *info) { } static inline void cxl_rch_enable_rcec(struct pci_dev *rcec) { } +static inline bool is_cxl_error(struct pci_dev *pdev, struct aer_err_info = *info) { return false; } +static inline bool cxl_forward_error(struct pci_dev *pdev, struct aer_err_= info *info) { return false; } +static inline void cxl_proto_err_flush(void) { } #endif /* CONFIG_CXL_RAS */ #endif /* _PORTDRV_H_ */ diff --git a/include/linux/aer.h b/include/linux/aer.h index df0f5c382286f..8eba3192e2d15 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -25,6 +25,7 @@ #define PCIE_STD_MAX_TLP_HEADERLOG (PCIE_STD_NUM_TLP_HEADERLOG + 10) =20 struct pci_dev; +struct work_struct; =20 struct pcie_tlp_log { union { @@ -66,6 +67,29 @@ static inline int pcie_aer_is_native(struct pci_dev *dev= ) { return 0; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } #endif =20 +#ifdef CONFIG_CXL_RAS +/** + * struct cxl_proto_err_work_data - Error information used in CXL error ha= ndling + * @pdev: PCI device detecting the error + * @severity: AER severity + */ +struct cxl_proto_err_work_data { + struct pci_dev *pdev; + int severity; +}; + +/** + * Callback for processing a CXL protocol error from the AER-CXL kfifo. + */ +typedef void (*cxl_proto_err_fn_t)(struct cxl_proto_err_work_data *wd); + +void cxl_register_proto_err_work(struct work_struct *work, + void (*flush)(void)); +void for_each_cxl_proto_err(struct cxl_proto_err_work_data *wd, + cxl_proto_err_fn_t fn); +void cxl_unregister_proto_err_work(void); +#endif + void pci_print_aer(struct pci_dev *dev, int aer_severity, struct aer_capability_regs *aer); int cper_severity_to_aer(int cper_severity); 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De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 06/13] PCI: Establish common CXL Port protocol error flow Date: Fri, 17 Jul 2026 17:26:59 -0500 Message-ID: <20260717222706.3540281-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231C:EE_|SAVPR12MB999169:EE_ X-MS-Office365-Filtering-Correlation-Id: 022ff984-acac-4fba-9065-08dee452b5aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|7416014|82310400026|23010399003|56012099006|11063799006|6133799003|3023799007|18002099003|22082099003|10067099003; X-Microsoft-Antispam-Message-Info: K45BjTugxF6HnsHx0Bi39dI71lglbhrzZQlKCn08RXgw3I34kFqJyH10pO6hM8DtcZcNtj9mM7pcReMNhKiOHABZu2Vu3yzRcIZfqNyCbQjLPcHy1+sD4TKLGk0cuS3DFPmWygOIaIzYajQ4ZzXbn/4DCI4XUsKMliwAnMIh28aydBTwzefBSI5Df8sVfLQb1jSgNM9Wh4CarA844yQu9k/AwPvMqCOaQrYCGfZNHiLjK3ygQKJ18P/My4MIgRFJDKvf6ZjhLCnd4KYZ9t0W78+FAjIeFnr9/FDhVOEI4vcBqEX3dJgDYVOd9oKXlm/5OhiHf/lHQhgcjU1vXWDZIhu+k3k0eJkU7NDR1iwHHf088klT25czWRo4JS+U1brPeZDjQ1Qw+7w2dmfK/E9E2cZEobciH8jLK3RiZT3T3hzizA/im38c8sHtAWaaxVOWFHjyhd3qJ9fk50vBPohEhaYAL+LgKmz9GMA0CNMJXKzdMt5owwFBDRSil7x2LlCwbtKYvvVKXwm8UYQy5JJp0mgsPGJ6poJy5FjA1FFI21KgdZF0JzP8T+LGiQ01cWoc9iozZ0RhIrXw/BtUFILSwM+RAHfN09YCGd4YJqnel2O3xQ+gL5ixE1+px5+DAWUsBMprsuQo+/TebvLOgUsHTJ6X2GKy9TfjkSlbb2HoLy0ZNAoS6iqd3FTaKgZN7qqPWLrDMbxKkK2GEzOysFe67A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(7416014)(82310400026)(23010399003)(56012099006)(11063799006)(6133799003)(3023799007)(18002099003)(22082099003)(10067099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: r8OV+ZQ7dSomywCNKQiGRdFgpedbdPGhFctDdkTToee0rhrbFIB32zUTmVJSdJt0RUKUR5gT/e9MIDR0a7CgWm/o58JG88StaEPXX4ipGj8L2ao1H7ovu4SJ+j0lePzUBCLIeusX++YB3nUTuwEiRg5yTngMuaNw6UR935TCTZ6xkKpGWva8iYseewV/RAjQDe74UqlmyOs+NfMn91nXLFAEh8KrCKP5KgL1EDZqSR6C9WHe++xQpc31WJlGiAeNJwxFvbQHIapTMAdiDwHGF+4zGVA49N+dmg4lWPu5fQu0M3ZKtHi8zG9edEwJsPG4P2Nj2VdT0Lyvt8quvMFIGMVXS6oPCFT60BIDiZwRjkQSDQ74ARUwqKQdDj4uRF5ljhTeuu3ThUNUeq+9lFbGTah0bctLV+bKxwJxebtdl266/6o0ZCVxDQD2uzwBG3PS X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:28:21.8151 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 022ff984-acac-4fba-9065-08dee452b5aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231C.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAVPR12MB999169 Content-Type: text/plain; charset="utf-8" Add CXL protocol error dispatch in handle_error_source() using is_cxl_error() and cxl_forward_error() to route errors through the AER-CXL kfifo. Expand is_cxl_error() from Endpoint-only to include Root Port, Upstream Port, and Downstream Port device types. The producer and consumer go live in the same commit to avoid silently dropping CXL errors during bisect. For uncorrectable events, call cxl_proto_err_flush() to ensure CXL RAS registers are read, panic policy is applied, and CXL state is cleared before pci_aer_handle_error() drives PCIe recovery. Without the flush, AER recovery can tear down drivers and unmap the CXL RAS iomaps while the kfifo consumer is still reading them. Correctable events do not need the flush and run asynchronously. RCH kfifo support is added in the following patch ("PCI/CXL: Add RCH support to CXL handlers"). Add cxl_handle_proto_error() to dispatch correctable and uncorrectable errors through the CXL RAS helpers. Add cxl_do_recovery() to coordinate uncorrectable recovery. Panic when a UCE is confirmed by a successful CXL RAS status register read. If the RAS registers cannot be read the UCE cannot be confirmed and panic is not triggered. Gate error handling on the port driver being bound to avoid processing errors on disabled devices. The kfifo consumer holds guard(device)(&port->dev) and checks port->dev.driver before accessing RAS registers, serializing against driver unbind and devm iomap teardown. For UCE, cxl_proto_err_flush() runs the worker synchronously before AER recovery, ensuring the device is present during RAS register access. Add to_ras_base() to centralize RAS base lookup: dport->regs.ras for Root/Downstream Ports, port->regs.ras for Upstream Ports and Endpoints. Use to_ras_base() to access the CXL devices' RAS registers as it will provide an avenue to inject status simulation during testing. Add CXL RAS logging in cxl_handle_cor_ras() and cxl_handle_ras(). The existing cxl_cor_error_detected() and cxl_error_detected() AER callbacks remain for all Endpoints and are reworked to use find_cxl_port_by_uport() and to_ras_base(), with UCE now triggering panic unconditionally. These callbacks are further updated in the following patch ("PCI/CXL: Add RCH support to CXL handlers"). Fix a pre-existing race for cxlds between cxl_handle_rdport_errors() and cxl_memdev_shutdown() by holding a cxlmd device scoped_guard() around the rdport call. Release the lock before taking the Port lock to avoid the lock inversion. Co-developed-by: Dan Williams Signed-off-by: Dan Williams Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang --- Changes in v17->v18: - Fix pre-existing race: hold memdev device lock around cxl_handle_rdport_errors(), release before port lock - Fix handle_error_source() to call pci_aer_handle_error() unconditionally so AER handling always runs after cxl_forward_error() - Add cxl_proto_err_flush() call for CXL UCE to drain kfifo before AER recovery tears down the device - Fix NULL dereference of dport->dport_dev in cxl_handle_cor_ras() and cxl_handle_ras() for UPSTREAM/ENDPOINT port types: use dport->dport_dev when dport is non-NULL, else fall back to port->uport_dev - Remove duplicate pcie_clear_device_status() call from cxl_handle_proto_error() CE path; pci_aer_handle_error() already clears it - Clarify panic policy: panic only on confirmed UCE via RAS status read - Document kfifo consumer serialization against driver unbind via guard(device)(&port->dev) and port->dev.driver check Changes in v16->v17: - get_cxl_port() -> find_cxl_port_by_dev() - Simplified find_cxl_port_by_dev() - Replace and remove cxl_serial_number() w/ pci_get_dsn() - cxl_get_ras_base() -> to_ras_base() - Drop dependency on PCI_ERS_RESULT_PANIC; cxl_do_recovery() panics directly. (PANIC enum patch dropped from series.) - Clarify panic semantics: panic on any uncorrectable CXL RAS error, not only AER-FATAL severities. - Add is_cxl_error() switch in handle_error_source() here, paired with the kfifo consumer registration, to keep each commit bisect-safe. - Drop pcie_aer_is_native() guard in cxl_do_recovery() (always native). - Swap order with the "Limit" patch for bisectability w/ cxl_ras_exit() - Reword for "any uncorrectable" CXL RAS error panics. - Restore log messages for port-not-found and port-unbound cases. - Whitespace cleanup (Jonathan) - Update to get_cxl_port() documentation (Terry) - Fix __cxl_proto_err_work_fn() to return 0 for transient errors. - Drop !port check in cxl_do_recovery(), caller already validated - Fix kerneldoc @pdev -> @dev in find_cxl_port_by_dev() - Fix missing space in pr_err_ratelimited() - Made pcie_clear_device_status() and pci_aer_clear_fatal_status() EXPORT_SYMBOL_FOR_MODULES("cxl_core") (Dan) - Move find_cxl_port_by_dport() and find_cxl_port_by_uport() de-staticisation and core.h declarations from the rename patch to here, where the first cross-file callers in find_cxl_port_by_dev() land. Changes in v15->v16: - get_ras_base(), initialize dport to NULL (Jonathan) - Remove guard(device)(&cxlmd->dev) (Jonathan) - Fix dev_warns() (Jonathan) - Remove comment in cxl_port_error_detected() (Dan) - Update switch-case brackets to follow clang-format (Dan) - Add PCI_EXP_TYPE_RC_END for cxl_get_ras_base() (Terry) - Add NULL port check in cxl_serial_number() (Terry) Changes in v14->v15: - Update commit message and title. Added Bjorn's ack. - Move CE and UCE handling logic here Changes in v13->v14: - Add Dave Jiang's review-by - Update commit message & headline (Bjorn) - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to one line (Jonathan) - Remove cxl_walk_port() (Dan) - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is sufficient (Dan) - Remove device_lock_if() - Combined CE and UCE here (Terry) Changes in v12->v13: - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue patch (Terry) - Remove EP case in cxl_get_ras_base(), not used. (Terry) - Remove check for dport->dport_dev (Dave) - Remove whitespace (Terry) Changes in v11->v12: - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and pci_to_cxl_dev() - Change cxl_error_detected() -> cxl_cor_error_detected() - Remove NULL variable assignments - Replace bus_find_device() with find_cxl_port_by_uport() for upstream port searches. Changes in v10->v11: - None --- drivers/cxl/core/core.h | 7 ++ drivers/cxl/core/port.c | 6 +- drivers/cxl/core/ras.c | 223 +++++++++++++++++++++++++++------- drivers/pci/pci.h | 1 - drivers/pci/pcie/aer.c | 13 ++ drivers/pci/pcie/aer_cxl_vh.c | 16 ++- 6 files changed, 220 insertions(+), 46 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 23fe40ddf4c6b..7c70bea06c2db 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -186,6 +186,8 @@ static inline struct device *dport_to_host(struct cxl_d= port *dport) void cxl_ras_init(void); void cxl_ras_exit(void); bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); +void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, + struct cxl_dport *dport); void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); @@ -198,6 +200,8 @@ static inline bool cxl_handle_ras(struct device *dev, v= oid __iomem *ras_base) { return false; } +static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *= port, + struct cxl_dport *dport) { } static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } @@ -206,6 +210,9 @@ static inline void devm_cxl_dport_ras_setup(struct cxl_= dport *dport) { } #endif /* CONFIG_CXL_RAS */ =20 int cxl_gpf_port_setup(struct cxl_dport *dport); +struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev, + struct cxl_dport **dport); +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev); =20 struct cxl_hdm; int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhd= m, diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index cadb51f70f854..a76f3ee05cba8 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -1400,8 +1400,8 @@ static struct cxl_port *__find_cxl_port_by_dport(stru= ct cxl_find_port_ctx *ctx) * Return a 'struct cxl_port' with an elevated reference if found. Use * __free(put_cxl_port) to release. */ -static struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev, - struct cxl_dport **dport) +struct cxl_port *find_cxl_port_by_dport(struct device *dport_dev, + struct cxl_dport **dport) { struct cxl_find_port_ctx ctx =3D { .dport_dev =3D dport_dev, @@ -1596,7 +1596,7 @@ static int match_port_by_uport(struct device *dev, co= nst void *data) * Function takes a device reference on the port device. Caller should do a * put_device() when done. */ -static struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) +struct cxl_port *find_cxl_port_by_uport(struct device *uport_dev) { struct device *dev; =20 diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 135f1997e6f4f..b190e69c2d415 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -77,6 +77,36 @@ static int match_memdev_by_parent(struct device *dev, co= nst void *uport) return 0; } =20 + +/** + * find_cxl_port_by_dev - Use @dev as hint to do a _by_dport or _by_uport = lookup + * @dev: generic device that may either be a companion of port or target d= port + * @dport: output parameter; set to the matched dport for dport-class + * lookups (Root Port, Downstream Port), NULL otherwise. + * + * Return a 'struct cxl_port' with an elevated reference if found. Use + * __free(put_cxl_port) to release. + */ +static struct cxl_port *find_cxl_port_by_dev(struct device *dev, struct cx= l_dport **dport) +{ + if (dport) + *dport =3D NULL; + if (!dev_is_pci(dev)) + return NULL; + + switch (pci_pcie_type(to_pci_dev(dev))) { + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_DOWNSTREAM: + return find_cxl_port_by_dport(dev, dport); + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_RC_END: + return find_cxl_port_by_uport(dev); + } + + return NULL; +} + void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data) { unsigned int devfn =3D PCI_DEVFN(data->prot_err.agent_addr.device, @@ -132,16 +162,6 @@ static void cxl_cper_prot_err_work_fn(struct work_stru= ct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 -void cxl_ras_init(void) -{ - cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); -} - -void cxl_ras_exit(void) -{ - cxl_cper_unregister_prot_err_work(); -} - static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; @@ -198,10 +218,39 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 +static void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *= dport) +{ + if (!port) + return NULL; + + if (dport) + return dport->regs.ras; + + return port->regs.ras; +} + +void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct c= xl_dport *dport) +{ + struct device *dev =3D dport ? dport->dport_dev : port->uport_dev; + void __iomem *ras_base =3D to_ras_base(port, dport); + + if (!ras_base) { + dev_err(&pdev->dev, + "CXL UCE signaled but RAS registers not mapped\n"); + return; + } + + if (cxl_handle_ras(dev, ras_base)) + panic("CXL cachemem error"); + + dev_dbg(&pdev->dev, + "CXL UCE signaled but no CXL RAS status bits set\n"); +} + void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { - void __iomem *addr; u32 status; + void __iomem *addr; =20 if (!ras_base) return; @@ -210,7 +259,10 @@ void cxl_handle_cor_ras(struct device *dev, void __iom= em *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + if (is_cxl_memdev(dev)) + trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + else + trace_cxl_port_aer_correctable_error(dev, status); } } =20 @@ -262,7 +314,11 @@ bool cxl_handle_ras(struct device *dev, void __iomem *= ras_base) } =20 header_log_copy(ras_base, hl); - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + if (is_cxl_memdev(dev)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + else + trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 return true; @@ -270,22 +326,32 @@ bool cxl_handle_ras(struct device *dev, void __iomem = *ras_base) =20 void cxl_cor_error_detected(struct pci_dev *pdev) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlds->cxlmd->dev; + guard(device)(&pdev->dev); + if (!pdev->dev.driver) + return; + + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&pd= ev->dev); + if (!port) + return; + + if (is_cxl_restricted(pdev)) { + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; =20 - scoped_guard(device, dev) { - if (!dev->driver) { + scoped_guard(device, &cxlmd->dev) { + cxl_handle_rdport_errors(cxlds); + } + } + + scoped_guard(device, &port->dev) { + if (!port->dev.driver) { dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); + "%s: port disabled, abort error handling\n", + dev_name(&port->dev)); return; } =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); - - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras); + cxl_handle_cor_ras(port->uport_dev, to_ras_base(port, NULL)); } } EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); @@ -293,42 +359,53 @@ EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - struct device *dev =3D &cxlmd->dev; - bool ue; + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&pd= ev->dev); + bool ue =3D false; =20 - scoped_guard(device, dev) { - if (!dev->driver) { + if (!port) + return PCI_ERS_RESULT_DISCONNECT; + + if (is_cxl_restricted(pdev)) { + struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); + struct cxl_memdev *cxlmd =3D cxlds->cxlmd; + + scoped_guard(device, &cxlmd->dev) { + cxl_handle_rdport_errors(cxlds); + } + } + + scoped_guard(device, &port->dev) { + if (!port->dev.driver) { dev_warn(&pdev->dev, - "%s: memdev disabled, abort error handling\n", - dev_name(dev)); + "%s: port disabled, abort error handling\n", + dev_name(&port->dev)); return PCI_ERS_RESULT_DISCONNECT; } =20 - if (cxlds->rcd) - cxl_handle_rdport_errors(cxlds); /* * A frozen channel indicates an impending reset which is fatal to * CXL.mem operation, and will likely crash the system. On the off * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras); + ue =3D cxl_handle_ras(port->uport_dev, to_ras_base(port, NULL)); } =20 + /* + * CXL.mem UCE means cache coherency is lost. Continuing risks + * silent data corruption across interleaved HDM regions. + */ + if (ue) + panic("CXL cachemem error"); + switch (state) { case pci_channel_io_normal: - if (ue) { - device_release_driver(dev); - return PCI_ERS_RESULT_NEED_RESET; - } return PCI_ERS_RESULT_CAN_RECOVER; case pci_channel_io_frozen: dev_warn(&pdev->dev, "%s: frozen state error detected, disable CXL.mem\n", - dev_name(dev)); - device_release_driver(dev); + dev_name(port->uport_dev)); + device_release_driver(port->uport_dev); return PCI_ERS_RESULT_NEED_RESET; case pci_channel_io_perm_failure: dev_warn(&pdev->dev, @@ -338,3 +415,67 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pd= ev, return PCI_ERS_RESULT_NEED_RESET; } EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); + +static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *= port, + struct cxl_dport *dport, int severity) +{ + struct device *dev =3D dport ? dport->dport_dev : port->uport_dev; + + if (severity =3D=3D AER_CORRECTABLE) + cxl_handle_cor_ras(dev, to_ras_base(port, dport)); + else + cxl_do_recovery(pdev, port, dport); +} + +static void __cxl_proto_err_work_fn(struct cxl_proto_err_work_data *wd) +{ + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_dev(&wd->= pdev->dev, NULL); + if (!port) { + dev_err_ratelimited(&wd->pdev->dev, + "Failed to find parent port device in CXL topology\n"); + return; + } + guard(device)(&port->dev); + if (!port->dev.driver) { + dev_err_ratelimited(&port->dev, + "Port device is unbound, abort error handling\n"); + return; + } + + struct cxl_dport *dport =3D cxl_find_dport_by_dev(port, &wd->pdev->dev); + if (!dport && (pci_pcie_type(wd->pdev) =3D=3D PCI_EXP_TYPE_ROOT_PORT || + pci_pcie_type(wd->pdev) =3D=3D PCI_EXP_TYPE_DOWNSTREAM)) { + dev_err_ratelimited(&wd->pdev->dev, + "Failed to find dport device in CXL topology\n"); + return; + } + + cxl_handle_proto_error(wd->pdev, port, dport, wd->severity); +} + +static void cxl_proto_err_work_fn(struct work_struct *work) +{ + struct cxl_proto_err_work_data wd; + + for_each_cxl_proto_err(&wd, __cxl_proto_err_work_fn); +} + +static DECLARE_WORK(cxl_proto_err_work, cxl_proto_err_work_fn); + +static void cxl_proto_err_do_flush(void) +{ + flush_work(&cxl_proto_err_work); +} + +void cxl_ras_init(void) +{ + cxl_cper_register_prot_err_work(&cxl_cper_prot_err_work); + cxl_register_proto_err_work(&cxl_proto_err_work, + cxl_proto_err_do_flush); +} + +void cxl_ras_exit(void) +{ + cxl_unregister_proto_err_work(); + cxl_cper_unregister_prot_err_work(); +} diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4469e1a77f3c1..a83e2aef75912 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -1296,7 +1296,6 @@ void pci_restore_aer_state(struct pci_dev *dev); static inline void pci_no_aer(void) { } static inline void pci_aer_init(struct pci_dev *d) { } static inline void pci_aer_exit(struct pci_dev *d) { } -static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINV= AL; } static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -= EINVAL; } static inline void pci_save_aer_state(struct pci_dev *dev) { } diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index c5bce25df51cb..2d9d40528e709 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1185,7 +1185,20 @@ static void pci_aer_handle_error(struct pci_dev *dev= , struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { + bool cxl_pending =3D false; + cxl_rch_handle_error(dev, info); + + if (is_cxl_error(dev, info)) + cxl_pending |=3D cxl_forward_error(dev, info); + + /* + * Wait for UCE CXL work to complete before AER recovery + * tears down the device. CE can run asynchronously. + */ + if (cxl_pending && info->severity !=3D AER_CORRECTABLE) + cxl_proto_err_flush(); + pci_aer_handle_error(dev, info); pci_dev_put(dev); } diff --git a/drivers/pci/pcie/aer_cxl_vh.c b/drivers/pci/pcie/aer_cxl_vh.c index 93bed07936100..ecf47bba0c9d4 100644 --- a/drivers/pci/pcie/aer_cxl_vh.c +++ b/drivers/pci/pcie/aer_cxl_vh.c @@ -49,8 +49,22 @@ bool is_cxl_error(struct pci_dev *pdev, struct aer_err_i= nfo *info) if (!info || !info->is_cxl) return false; =20 - if (pci_pcie_type(pdev) !=3D PCI_EXP_TYPE_ENDPOINT) + /* + * RC_END (Restricted CXL Device) is not included here because RC_END + * reports errors on behalf of upstream RCH Downstream Port and thus + * requires a unique discovery detailed in CXL4.0 spec (12.2.1.1). + * The RCH device error discovery and RC_END forwarding flow begins + * in cxl_rch_handle_error(). + */ + switch (pci_pcie_type(pdev)) { + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_ROOT_PORT: + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_DOWNSTREAM: + break; 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Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 07/13] PCI/CXL: Add RCH support to CXL handlers Date: Fri, 17 Jul 2026 17:27:00 -0500 Message-ID: <20260717222706.3540281-8-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|LV1PR12MB999279:EE_ X-MS-Office365-Filtering-Correlation-Id: 7053a89f-92a9-4d9a-1796-08dee452bcbc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|23010399003|376014|7416014|18002099003|22082099003|56012099006|11063799006|3023799007|10067099003|6133799003; X-Microsoft-Antispam-Message-Info: 9wEyR/CB6zinC5Y5AheKzHRMGcC2aH6k8ZVv6pQkTpV4pP56/32goZ2khivdEUw8fFB2h0iZ0uUPfcoavpgmpoR0eRzPUyL33M5ZmoC56afjvywEpma/uNjH7drWq6SyOOnUh+n8FrzpE05ECCcymGDb2v1LuRGYZyoCE0BDFCtIUbbuIeAEprGOQicf8OOWDsKzVdl6SXUeo42xgPRrEXWdmuA9g5PoPYRG37alx6Roj3ZAAnhCKQ9Fvk/fCiaSQLVbg1iP91xEt/qWnNArqQRDsE/Dtl/fXEWLoS734Mp96/jfT2WxrfdA+I4iBwFZ5dXyXhjyJyNMrFeEZ6O8Oug1RKyX8f0Zsx7gxUaODykui7cZNQvOeyOsh80NDA0pmjFIHTgrpssWpQd2sNnCmS877s2Dk9EA4INZmBq1RM7XsLj0V2Pcqddpwz+wBeYCACw4m5E7M2RGSXdE1V86MiWsrLR+ZmL6cBHRPWOJrSuBslo5mI5BSwxj/1atLyayLobhP649Zs28akGWirMO+M1u42uRLhyLJzAYjiYqyIhsy4wxGRbGDxfjxXw/v5mzXoP15onL1QTqAhiNAQLpGHekOxZzr/yVpqefA/pFgb8mQ14+ph3GQISCZn52a5CCCOqWn89K78GH9ohNkZjeGipOMFQ2HiXVpP6EHGtcJQCXrfF2gVGnXL7oicyLX4YRT9gxPuH7q5+LU8/c7Ux5Fg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(23010399003)(376014)(7416014)(18002099003)(22082099003)(56012099006)(11063799006)(3023799007)(10067099003)(6133799003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Jgo/fI0kZ1f0D+GQ4MS1XW/IgkxZGxEkRypcX0JASIkMIWXbITOPMmb6T4eu6jHsjNc5mUl4aHXTcQ3TevYqt3VsLTIGmXU/q5vAuN+9q+UBpl0elnKg6ZeRpcaRP7poecXuIqY205Q3pk8CaDjtKOe+RhYmhbZJqlsV/7pAJeoXAikq90hpBuBrIfnIt/dQ9a5/K3yS4+CmqiT2i/62ZL5KVAQvIKNRah4xPmVP/nqEDrUCWI5+2zBB4HuPBBFrqkNpyRTikcffwvwzK2i4Eg8oXRGxOi8QMelXBHamEbQEMciGeCyGlgf9cFr3keUmxDsSdfxzrALbFs+TJVzXJvXFWvsSNxUN0GmpqYEOelVurLZcf2wOOF8tEcMSNEa5FWrhyIq+0QB+TmWuAM0lc3ga5IjTKYdSlqYRjHp49m55kyc4cbquVWEy5fhgapyK X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:28:33.6810 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7053a89f-92a9-4d9a-1796-08dee452bcbc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV1PR12MB999279 Content-Type: text/plain; charset="utf-8" Restricted CXL Host (RCH) error handling is a separate path from the new CXL Port error handling flow. Fold RCH error handling into the Port flow so both share a common entry point. Update cxl_rch_handle_error_iter() to forward RCH protocol errors through the AER-CXL kfifo. Change cxl_rch_handle_error() return type from void to bool so handle_error_source() can determine whether work was enqueued and call cxl_proto_err_flush() before AER recovery proceeds. For RC_END devices, __cxl_proto_err_work_fn() calls cxl_handle_rdport_errors() to process RCH Downstream Port errors, then falls through to the VH path for RC_END Endpoint handling. An RCD uncorrectable CXL RAS error now panics via cxl_do_recovery(). Before this patch the RCH Downstream Port UCE path called cxl_handle_ras() but ignored its return value - no panic. After this patch the same condition calls cxl_do_recovery() which panics on confirmed UCE. The Endpoint UCE path already panicked at the parent commit. This matches the panic policy added in the common CXL Port protocol error flow. Remove cxl_cor_error_detected() and its .cor_error_detected registration in cxl_error_handlers. Correctable Endpoint errors are now routed through the AER-CXL kfifo like all other CXL protocol errors. Drop the cxlds->rcd / cxl_handle_rdport_errors(cxlds) branches from cxl_error_detected(). RCH downstream port error handling is now performed by __cxl_proto_err_work_fn() via the kfifo path, which calls cxl_handle_rdport_errors(pdev) before the common dispatch. Change cxl_handle_rdport_errors() to take a struct pci_dev * instead of a struct cxl_dev_state *, matching the new caller context. Re-fetch dport under guard() to close the TOCTOU window between cxl_pci_find_port()'s lockless xa_load() and the first dereference of the returned pointer. Change find_cxl_port_by_dev() RC_END lookup from find_cxl_port_by_dport(dev->parent) to find_cxl_port_by_uport(dev), matching the Endpoint lookup path. RC_END Endpoint port resolution uses the uport (the RC_END device itself), while the separate RCH Downstream Port lookup is handled by cxl_handle_rdport_errors(). The RCH Downstream Port and the RCD Endpoint (RC_END) are separate devices with independent RAS register blocks. cxl_handle_rdport_errors() handles the RCH Downstream Port RAS. RCD Endpoint (RC_END) is handled in cxl_handle_proto_error(). Use to_ras_base() in cxl_handle_rdport_errors() instead of referencing dport->regs.ras directly. Make to_ras_base() non-static in ras.c and declare it in core.h so ras_rch.c can access it. Route all RAS base address= lookups through a single helper to prepare for CXL RAS error injection testing that follows this series. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang --- Changes in v17->v18: - Pass &pdev->dev instead of dport->port->uport_dev in cxl_handle_rdport_errors() to avoid dropping RCH trace events. - Document trace event attribution change. - Document removal of cxl_cor_error_detected() and cxlds->rcd branches. - Capitalize Endpoint per PCI spec convention. - Use to_ras_base() in cxl_handle_rdport_errors() to centralize RAS base address lookup in preparation for error injection testing. Changes in v16->v17: - Drop now-dead cxlds->rcd branches from cxl_{cor_,}error_detected(). - Drop duplicate subject line from commit body. - Document panic-on-uncorrectable behavior change for RCD path. - Document trace event device-name change (memN -> PCI BDF) for RCH path. - Rewrite cxl_handle_proto_error() RC_END comment to clarify RCD/RCH shared interrupt relationship - Rewrite commit message Changes in v16: - New commit --- drivers/cxl/core/core.h | 10 +++++-- drivers/cxl/core/ras.c | 50 ++++++++-------------------------- drivers/cxl/core/ras_rch.c | 16 ++++++----- drivers/cxl/cxlpci.h | 3 -- drivers/cxl/pci.c | 1 - drivers/pci/pcie/aer.c | 4 +-- drivers/pci/pcie/aer_cxl_rch.c | 39 ++++++++++++-------------- drivers/pci/pcie/portdrv.h | 4 +-- 8 files changed, 48 insertions(+), 79 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 7c70bea06c2db..272634ff2615b 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -191,7 +191,8 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_p= ort *port, void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); -void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds); +void cxl_handle_rdport_errors(struct pci_dev *pdev); +void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport); void devm_cxl_dport_ras_setup(struct cxl_dport *dport); #else static inline void cxl_ras_init(void) { } @@ -205,7 +206,12 @@ static inline void cxl_do_recovery(struct pci_dev *pde= v, struct cxl_port *port, static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } -static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) {= } +static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { } +static inline void __iomem *to_ras_base(struct cxl_port *port, + struct cxl_dport *dport) +{ + return NULL; +} static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { } #endif /* CONFIG_CXL_RAS */ =20 diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index b190e69c2d415..9a142abcf4f8b 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -218,7 +218,8 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 -static void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *= dport) + +void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport) { if (!port) return NULL; @@ -324,37 +325,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *= ras_base) return true; } =20 -void cxl_cor_error_detected(struct pci_dev *pdev) -{ - guard(device)(&pdev->dev); - if (!pdev->dev.driver) - return; - - struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&pd= ev->dev); - if (!port) - return; - - if (is_cxl_restricted(pdev)) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; =20 - scoped_guard(device, &cxlmd->dev) { - cxl_handle_rdport_errors(cxlds); - } - } - - scoped_guard(device, &port->dev) { - if (!port->dev.driver) { - dev_warn(&pdev->dev, - "%s: port disabled, abort error handling\n", - dev_name(&port->dev)); - return; - } - - cxl_handle_cor_ras(port->uport_dev, to_ras_base(port, NULL)); - } -} -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, "CXL"); =20 pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state) @@ -365,14 +336,6 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pd= ev, if (!port) return PCI_ERS_RESULT_DISCONNECT; =20 - if (is_cxl_restricted(pdev)) { - struct cxl_dev_state *cxlds =3D pci_get_drvdata(pdev); - struct cxl_memdev *cxlmd =3D cxlds->cxlmd; - - scoped_guard(device, &cxlmd->dev) { - cxl_handle_rdport_errors(cxlds); - } - } =20 scoped_guard(device, &port->dev) { if (!port->dev.driver) { @@ -429,6 +392,15 @@ static void cxl_handle_proto_error(struct pci_dev *pde= v, struct cxl_port *port, =20 static void __cxl_proto_err_work_fn(struct cxl_proto_err_work_data *wd) { + /* + * For RC_END (RCD) devices, handle RCH Downstream Port errors + * first. cxl_handle_rdport_errors() does its own port lookup + * and locking, keeping the Downstream Port lock separate from the + * Endpoint Port lock taken below. + */ + if (is_cxl_restricted(wd->pdev)) + cxl_handle_rdport_errors(wd->pdev); + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_dev(&wd->= pdev->dev, NULL); if (!port) { dev_err_ratelimited(&wd->pdev->dev, diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 44b335d560708..f2d2fb83758b9 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2025 AMD Corporation. All rights reserved. */ =20 -#include #include #include "cxl.h" #include "core.h" @@ -96,18 +95,21 @@ static bool cxl_rch_get_aer_severity(struct aer_capabil= ity_regs *aer_regs, return false; } =20 -void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) +void cxl_handle_rdport_errors(struct pci_dev *pdev) { - struct pci_dev *pdev =3D to_pci_dev(cxlds->dev); struct aer_capability_regs aer_regs; struct cxl_dport *dport; int severity; =20 - struct cxl_port *port __free(put_cxl_port) =3D - cxl_pci_find_port(pdev, &dport); + struct cxl_port *port __free(put_cxl_port) =3D cxl_pci_find_port(pdev, NU= LL); if (!port) return; =20 + guard(device)(&port->dev); + dport =3D cxl_find_dport_by_dev(port, pdev->dev.parent); + if (!dport) + return; + if (!cxl_rch_get_aer_info(dport->regs.dport_aer, &aer_regs)) return; =20 @@ -116,7 +118,7 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxl= ds) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_handle_cor_ras(&pdev->dev, to_ras_base(port, dport)); else - cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); + cxl_do_recovery(pdev, dport->port, dport); } diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index b826eb53cf7ba..06c46adcf0f6c 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -89,14 +89,11 @@ struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS -void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport); void devm_cxl_port_ras_setup(struct cxl_port *port); #else -static inline void cxl_cor_error_detected(struct pci_dev *pdev) { } - static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 7c6faee7f85ed..5c21db36073fe 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1004,7 +1004,6 @@ static const struct pci_error_handlers cxl_error_hand= lers =3D { .error_detected =3D cxl_error_detected, .slot_reset =3D cxl_slot_reset, .resume =3D cxl_error_resume, - .cor_error_detected =3D cxl_cor_error_detected, .reset_done =3D cxl_reset_done, }; =20 diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 2d9d40528e709..0bd23a65e7ebc 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1185,9 +1185,7 @@ static void pci_aer_handle_error(struct pci_dev *dev,= struct aer_err_info *info) =20 static void handle_error_source(struct pci_dev *dev, struct aer_err_info *= info) { - bool cxl_pending =3D false; - - cxl_rch_handle_error(dev, info); + bool cxl_pending =3D cxl_rch_handle_error(dev, info); =20 if (is_cxl_error(dev, info)) cxl_pending |=3D cxl_forward_error(dev, info); diff --git a/drivers/pci/pcie/aer_cxl_rch.c b/drivers/pci/pcie/aer_cxl_rch.c index e471eefec9c40..683712fc965ff 100644 --- a/drivers/pci/pcie/aer_cxl_rch.c +++ b/drivers/pci/pcie/aer_cxl_rch.c @@ -34,42 +34,37 @@ static bool cxl_error_is_native(struct pci_dev *dev) return (pcie_ports_native || host->native_aer); } =20 +struct cxl_rch_error_ctx { + struct aer_err_info *info; + bool enqueued; +}; + static int cxl_rch_handle_error_iter(struct pci_dev *dev, void *data) { - struct aer_err_info *info =3D (struct aer_err_info *)data; - const struct pci_error_handlers *err_handler; + struct cxl_rch_error_ctx *ctx =3D data; =20 if (!is_cxl_mem_dev(dev) || !cxl_error_is_native(dev)) return 0; =20 - guard(device)(&dev->dev); - - err_handler =3D dev->driver ? dev->driver->err_handler : NULL; - if (!err_handler) - return 0; - - if (info->severity =3D=3D AER_CORRECTABLE) { - if (err_handler->cor_error_detected) - err_handler->cor_error_detected(dev); - } else if (err_handler->error_detected) { - if (info->severity =3D=3D AER_NONFATAL) - err_handler->error_detected(dev, pci_channel_io_normal); - else if (info->severity =3D=3D AER_FATAL) - err_handler->error_detected(dev, pci_channel_io_frozen); - } + if (cxl_forward_error(dev, ctx->info)) + ctx->enqueued =3D true; return 0; } =20 -void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) +bool cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info) { + struct cxl_rch_error_ctx ctx =3D { .info =3D info }; + /* - * Internal errors of an RCEC indicate an AER error in an - * RCH's downstream port. Check and handle them in the CXL.mem - * device driver. + * An RCEC AER internal error indicates an error in an + * associated RCH Downstream Port or RC_END device or both. + * Forward to the cxl_core module for handling. */ if (pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_RC_EC && is_aer_internal_error(info)) - pcie_walk_rcec(dev, cxl_rch_handle_error_iter, info); + pcie_walk_rcec(dev, cxl_rch_handle_error_iter, &ctx); + + return ctx.enqueued; } =20 static int handles_cxl_error_iter(struct pci_dev *dev, void *data) diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index fd203010877bf..807bca90dee0e 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -128,14 +128,14 @@ struct aer_err_info; =20 #ifdef CONFIG_CXL_RAS bool is_aer_internal_error(struct aer_err_info *info); -void cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); +bool cxl_rch_handle_error(struct pci_dev *dev, struct aer_err_info *info); void cxl_rch_enable_rcec(struct pci_dev *rcec); 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Fri, 17 Jul 2026 17:28:43 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 08/13] cxl/pci: Thread port and dport through RAS handling helpers Date: Fri, 17 Jul 2026 17:27:01 -0500 Message-ID: <20260717222706.3540281-9-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002319:EE_|CH1PPF84B7B0C96:EE_ X-MS-Office365-Filtering-Correlation-Id: 03f9441c-65aa-448d-c6bc-08dee452c3ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|36860700016|82310400026|1800799024|10067099003|6133799003|56012099006|22082099003|18002099003|11063799006; X-Microsoft-Antispam-Message-Info: CbqYr+kY/IgsXX1RSccqFz3lKtzHOYZv7GP2hK/QmKP9xRVzgur6oXsl0OQGJJjqnCjlKzX4MZ6dc/7OzlX5kmOlliFkVgai0xSGAcsyRKh46PK4F5pVjAiD/Ev5ZrdYD18zWR/OstWBvI/6hwXZ0g5rIO/oRqPJzN6iv8ZuONqdtHFJH6pSGp7c3Udj8UE1NC9Z7r7u6O578slTM+cizsQ4wKwuf/CSry9E8zP1Hj8HBRfkzOWh6/EXu+Talfz4TMygEYpcTB2KkFy/89ZqtIe4X1v8yrXwK6mw+m94kEUc+wo1cSkgd+Y/B9JrgctVBqrZn/sGrEdhKIXlmsnTbly/RhSk0WK68NXUeBSVxF6moQL1nFqZLlMvcHn0Sb56FP3J23F5exUOX+6pWSGDYZp+foFbLQ69tF6LsBMysLjqCVbTdn5KZ88qD2w5Co/NNfXNNGW9L8ctbLJPjOGrqQPeD88hsrq96AeEHpOhKhte7Win6eR+/I2WYQu7+zpBbQSsAZPzFc9S/UH6OXAfUTf4zVusFqaArBU3Vg8WzHfw+q0euQDuwQEN2yyE6NKWyPmcfryfzlW02Z8m+dUbKmLskRM3tNxsq704Zd9tvNwIFrm1UguDpsO5pnRH/jcRn5CzwSBzjEiZzhTE4zbOhfovKkPrrBTT1V2F1x+M8h0Hz6i0+dwXzIHf9NWvzxWwsPBL5EplMsndra/KOx08yw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(7416014)(376014)(36860700016)(82310400026)(1800799024)(10067099003)(6133799003)(56012099006)(22082099003)(18002099003)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 9mVrq4ePbfxXja9NrMW/sws2QQjBmvf4sy5YD+2r80mMyYFFLENFBQzzrEaILCahpxcJi0+NGwO0/JcKUxoj64KrmjvuJcFKpT9HwxtS4ztqcY8s0YwjotSyqg8C7nc2S6qGccgnTbyipoLP1qnPkHi2pVfeDJbdV+500g/zmfVuknBiygwzK1u4UayhG3SqCJEum/RSOkCR2pHompIxxYMbRbV6SehJeN1N0s7l1x3+NZ9J6qvH7lLYjSRQydglFfyHs4mZN889bQw4fJXxOap+evo/RxmudtMaSxbncgsDYpD1WnKYVkLyyx6YsvZEkeI+hy/TIfKWDcGLLwV3VqF8CvJNjNIxvDZALxhQhZjxzY0D0E67ZUt1mnLnZGz8iw/KSj9N7VyH/T3ZMXFGWgud5SiJgiWzd5x0XJ7SZuhHnYDcbys0/z1YY7WPKpTM X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:28:45.3215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03f9441c-65aa-448d-c6bc-08dee452c3ac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002319.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF84B7B0C96 Content-Type: text/plain; charset="utf-8" From: Dan Williams The callers of cxl_handle_ras() and cxl_handle_cor_ras() already hold a struct cxl_port * and struct cxl_dport * for the device being handled. Passing a generic struct device * requires is_cxl_memdev() to distinguish Endpoints from ports at trace emission time. Threading port and dport directly enables is_cxl_endpoint(port) and explicit dport/port branching for cleaner trace dispatch. Refactor cxl_handle_ras() and cxl_handle_cor_ras() to accept struct cxl_port * and struct cxl_dport * directly. The CXL RAS trace event emission logic is split into three branches: Endpoint events are identified via is_cxl_endpoint(port) and emit with the memdev, dport events emit with dport->dport_dev, and Upstream Port events fall back to port->uport_dev. Update cxl_handle_rdport_errors() in ras_rch.c and cxl_handle_proto_error() in ras.c to pass port and dport to the refactored functions. RCH Downstream Port correctable trace events now report the dport device (dport->dport_dev) as a consequence of threading port and dport through the RAS helpers. The following trace event rework ("cxl: Add port and dport identifiers to CXL AER trace events") adds explicit memdev, port, dport, and host fields that provide full context for all device types. Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Dan Williams Reviewed-by: Dave Jiang --- Changes in v17 -> v18: - New patch. --- drivers/cxl/core/core.h | 12 ++++++++---- drivers/cxl/core/ras.c | 29 +++++++++++++++-------------- drivers/cxl/core/ras_rch.c | 2 +- 3 files changed, 24 insertions(+), 19 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 272634ff2615b..5ca1275fd8f35 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -185,10 +185,12 @@ static inline struct device *dport_to_host(struct cxl= _dport *dport) #ifdef CONFIG_CXL_RAS void cxl_ras_init(void); void cxl_ras_exit(void); -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base); +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base); void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport); -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base); +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct pci_dev *pdev); @@ -197,13 +199,15 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport= ); #else static inline void cxl_ras_init(void) { } static inline void cxl_ras_exit(void) { } -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_ba= se) +static inline bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport = *dport, + void __iomem *ras_base) { return false; } static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *= port, struct cxl_dport *dport) { } -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ra= s_base) { } +static inline void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dp= ort *dport, + void __iomem *ras_base) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 9a142abcf4f8b..6f4a3c1b0bb85 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -232,7 +232,6 @@ void __iomem *to_ras_base(struct cxl_port *port, struct= cxl_dport *dport) =20 void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct c= xl_dport *dport) { - struct device *dev =3D dport ? dport->dport_dev : port->uport_dev; void __iomem *ras_base =3D to_ras_base(port, dport); =20 if (!ras_base) { @@ -241,14 +240,14 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl= _port *port, struct cxl_dpo return; } =20 - if (cxl_handle_ras(dev, ras_base)) + if (cxl_handle_ras(port, dport, ras_base)) panic("CXL cachemem error"); =20 dev_dbg(&pdev->dev, "CXL UCE signaled but no CXL RAS status bits set\n"); } =20 -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, vo= id __iomem *ras_base) { u32 status; void __iomem *addr; @@ -260,10 +259,12 @@ void cxl_handle_cor_ras(struct device *dev, void __io= mem *ras_base) status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - if (is_cxl_memdev(dev)) - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status); + if (is_cxl_endpoint(port)) + trace_cxl_aer_correctable_error(to_cxl_memdev(port->uport_dev), status); + else if (dport) + trace_cxl_port_aer_correctable_error(dport->dport_dev, status); else - trace_cxl_port_aer_correctable_error(dev, status); + trace_cxl_port_aer_correctable_error(port->uport_dev, status); } } =20 @@ -288,7 +289,7 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base) +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void _= _iomem *ras_base) { u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; void __iomem *addr; @@ -315,10 +316,12 @@ bool cxl_handle_ras(struct device *dev, void __iomem = *ras_base) } =20 header_log_copy(ras_base, hl); - if (is_cxl_memdev(dev)) - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl); + if (is_cxl_endpoint(port)) + trace_cxl_aer_uncorrectable_error(to_cxl_memdev(port->uport_dev), status= , fe, hl); + else if (dport) + trace_cxl_port_aer_uncorrectable_error(dport->dport_dev, status, fe, hl); else - trace_cxl_port_aer_uncorrectable_error(dev, status, fe, hl); + trace_cxl_port_aer_uncorrectable_error(port->uport_dev, status, fe, hl); =20 writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 @@ -351,7 +354,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =3D cxl_handle_ras(port->uport_dev, to_ras_base(port, NULL)); + ue =3D cxl_handle_ras(port, NULL, to_ras_base(port, NULL)); } =20 /* @@ -382,10 +385,8 @@ EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *= port, struct cxl_dport *dport, int severity) { - struct device *dev =3D dport ? dport->dport_dev : port->uport_dev; - if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(dev, to_ras_base(port, dport)); + cxl_handle_cor_ras(port, dport, to_ras_base(port, dport)); else cxl_do_recovery(pdev, port, dport); } diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index f2d2fb83758b9..f4b98f2c11a1c 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -118,7 +118,7 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(&pdev->dev, to_ras_base(port, dport)); + cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport)); else cxl_do_recovery(pdev, dport->port, dport); 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Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . 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Document the unconditional CXL RAS read policy: on a dead link, readl() returns 0xFFFFFFFF which is interpreted as UCE bits set and triggers a panic. If RAS registers are not mapped the read is skipped and the frozen/perm_failure switch cases defer to AER recovery for devices without active CXL.mem traffic. Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v17->v18: - Fix cxl_pci_error_detected() to use find_cxl_port_by_uport() and port->up= ort_dev - Read CXL RAS unconditionally; panic on UCE regardless of channel state - Document unconditional read policy and 0xFFFFFFFF behavior in comment - Drop guard removal paragraph from commit message (not in this diff) - Drop Reviewed-by tags pending re-review after message change Changes in v16->v17: - Rename pci_error_handlers struct instance to cxl_pci_error_handlers to avoid shadowing the struct type tag. - Restore scoped_guard(device) and dev->driver check around AER read. - NULL-check find_cxl_port_by_dev() before deref of port->uport_dev. - Updated commit message. (Terry) - Add scope cleanup for port variable in cxl_pci_error_detected() (Terry) - Drop cxl_uncor_aer_present(), rely on AER state Changes in v15->v16: - Update commit message (DaveJ) - s/cxl_handle_aer()/cxl_uncor_aer_present()/g (Jonathan) - cxl_uncor_aer_present(): Leave original result calculation based on if a UCE is present and the provided state (Terry) - Add call to pci_print_aer(). AER fails to log because is upstream link (Terry) Changes in v14->v15: - Update commit message and title. Added Bjorn's ack. - Move CE and UCE handling logic here Changes in v13->v14: - Add Dave Jiang's review-by - Update commit message & headline (Bjorn) - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to one line (Jonathan) - Remove cxl_walk_port() (Dan) - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is sufficient (Dan) - Remove device_lock_if() - Combined CE and UCE here (Terry) Changes in v12->v13: - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue patch (Terry) - Remove EP case in cxl_get_ras_base(), not used. (Terry) - Remove check for dport->dport_dev (Dave) - Remove whitespace (Terry) Changes in v11->v12: - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and pci_to_cxl_dev() - Change cxl_error_detected() -> cxl_cor_error_detected() - Remove NULL variable assignments - Replace bus_find_device() with find_cxl_port_by_uport() for upstream port searches. Changes in v10->v11: - None --- drivers/cxl/core/ras.c | 24 +++++++++++++++--------- drivers/cxl/cxlpci.h | 8 ++++---- drivers/cxl/pci.c | 12 ++++++------ 3 files changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 6f4a3c1b0bb85..d5dc2c22565da 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -328,10 +328,8 @@ bool cxl_handle_ras(struct cxl_port *port, struct cxl_= dport *dport, void __iomem return true; } =20 - - -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) { struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_uport(&pd= ev->dev); bool ue =3D false; @@ -349,10 +347,18 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *p= dev, } =20 /* - * A frozen channel indicates an impending reset which is fatal to - * CXL.mem operation, and will likely crash the system. On the off - * chance the situation is recoverable dump the status of the RAS - * capability registers and bounce the active state of the memdev. + * The CXL RAS read is unconditional regardless of channel + * state. Any uncorrectable error bit set in the CXL RAS + * status register triggers a panic because CXL.mem cache + * coherency is already lost; continuing risks silent data + * corruption across interleaved HDM regions. + * + * On a dead link readl() returns 0xFFFFFFFF which sets all + * UCE bits and also triggers the panic - this is intentional. + * If RAS registers are not mapped the read is skipped, the + * panic is not reached, and the frozen/perm_failure switch + * cases below handle AER recovery for devices without active + * CXL.mem traffic. */ ue =3D cxl_handle_ras(port, NULL, to_ras_base(port, NULL)); } @@ -380,7 +386,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pde= v, } return PCI_ERS_RESULT_NEED_RESET; } -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, "CXL"); +EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, "CXL"); =20 static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *= port, struct cxl_dport *dport, int severity) diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 06c46adcf0f6c..8aeb80a4e5732 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -89,13 +89,13 @@ struct cxl_dev_state; void read_cdat_data(struct cxl_port *port); =20 #ifdef CONFIG_CXL_RAS -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state); +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state); void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport); void devm_cxl_port_ras_setup(struct cxl_port *port); #else -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, - pci_channel_state_t state) +static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev, + pci_channel_state_t state) { return PCI_ERS_RESULT_NONE; } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 5c21db36073fe..6cf1db7b85020 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -1000,18 +1000,18 @@ static void cxl_reset_done(struct pci_dev *pdev) } } =20 -static const struct pci_error_handlers cxl_error_handlers =3D { - .error_detected =3D cxl_error_detected, - .slot_reset =3D cxl_slot_reset, - .resume =3D cxl_error_resume, - .reset_done =3D cxl_reset_done, +static const struct pci_error_handlers cxl_pci_error_handlers =3D { + .error_detected =3D cxl_pci_error_detected, + .slot_reset =3D cxl_slot_reset, + .resume =3D cxl_error_resume, + .reset_done =3D cxl_reset_done, }; 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Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . 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The trace event helpers then derive the right strings for endpoints, switch ports, root ports, and RCH downstream ports consistently across the CPER and native AER paths. The unified cxl_aer_* events keep "memdev" as the legacy field (endpoint events populate it with the memdev name; non-endpoint events emit memdev=3D"") and add new "port" and "dport" string fields populated for all CXL device classes. Updated userspace can key off "port" and "dport" without a parallel set of events. Remove the separate cxl_port_aer_uncorrectable_error and cxl_port_aer_correctable_error trace events. All CXL AER events now use the unified cxl_aer_* events with port and dport fields. Rework cxl_cper_handle_prot_err() to use find_cxl_port_by_dev() and the unified trace helpers, replacing the per-port-type branching and bus_find_device() memdev lookup. The TP_printk format string places "port=3D%s dport=3D%s" between "memdev=3D%s" and "host=3D%s", changing the text-mode field order from the pre-patch output. This does not affect consumers such as rasdaemon that use libtraceevent to parse fields by name rather than by fixed text position. For non-endpoint events (switch port, root port, RCH dport), "memdev" is empty and "port"/"dport" carry the topology information. The serial number is retrieved via pci_get_dsn() which performs live PCI configuration space reads. A following patch ("PCI: Cache PCI DSN into pci_dev->dsn during probe") replaces these with a cached serial number to avoid config space access in error handlers and panic paths. Below are examples of the different CXL devices' error trace logs after this patch: --------------------- | CXL RP - 0C:00.0 | --------------------- | --------------------- | CXL USP - 0D:00.0 | --------------------- | -------------------- | CXL DSP - 0E:00.0 | -------------------- | --------------------- | CXL EP - 0F:00.0 | --------------------- Root Port: cxl_aer_correctable_error: memdev=3D port=3Dport1 dport=3D0000:0c:00.0 \ host=3Dpci0000:0c serial=3D0: status: 'Memory Data ECC Error' cxl_aer_uncorrectable_error: memdev=3D port=3Dport1 dport=3D0000:0c:00.0 \ host=3Dpci0000:0c serial=3D0: status: 'Cache Address Parity Error' \ first_error: 'Cache Address Parity Error' Upstream Switch Port: cxl_aer_correctable_error: memdev=3D port=3Dport2 dport=3D host=3D0000:0d:0= 0.0 \ serial=3D0: status: 'Memory Data ECC Error' UCE NA - Upstream Switch Port UCE's are handled in the portdrv driver's PCI AER callbacks that are not CXL aware. Downstream Switch Port: cxl_aer_correctable_error: memdev=3D port=3Dport2 dport=3D0000:0e:00.0 \ host=3D0000:0d:00.0 serial=3D0: status: 'Memory Data ECC Error' cxl_aer_uncorrectable_error: memdev=3D port=3Dport2 dport=3D0000:0e:00.0 \ host=3D0000:0d:00.0 serial=3D0: status: 'Cache Address Parity Error' \ first_error: 'Cache Address Parity Error' Endpoint: cxl_aer_uncorrectable_error: memdev=3Dmem1 port=3Dendpoint4 dport=3D \ host=3D0000:0f:00.0 serial=3D0: status: 'Cache Address Parity Error' \ first_error: 'Cache Address Parity Error' cxl_aer_correctable_error: memdev=3Dmem1 port=3Dendpoint4 dport=3D host=3D0= 000:0f:00.0 \ serial=3D0: status: 'Memory Data ECC Error' Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Dan Williams Reviewed-by: Dave Jiang --- Changes in v17->v18: - Consolidate double find_cxl_port_by_dev() in cxl_cper_handle_prot_err() - Add comment noting dport is NULL for Endpoint and Upstream Port devices - Add cxl_trace_* helpers - Add CPER refactor Changes in v16->v17: - Replace cxlds->serial with pci_get_dsn() - Change 'memdev' to 'device' (Dan) - Updated Commit message Changes in v15->v16: - Add Dan's review-by - Incorporate Dan's comment into commit message: "Add the serial number at the end to preserve compatibility with libtraceevent parsing of the parameters." Changes in v14->v15: - Update commit message. - Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry) Changes in v13->v14: - Update commit headline (Bjorn) Changes in v12->v13: - Added Dave Jiang's review-by Changes in v11 -> v12: - Correct parameters to call trace_cxl_aer_correctable_error() - Add reviewed-by for Jonathan and Shiju Changes in v10->v11: - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI and unchanged TP_printk() logging. --- drivers/cxl/core/core.h | 8 +-- drivers/cxl/core/ras.c | 131 +++++++++++-------------------------- drivers/cxl/core/ras_rch.c | 3 +- drivers/cxl/core/trace.c | 35 ++++++++++ drivers/cxl/core/trace.h | 91 ++++++++------------------ drivers/cxl/cxlmem.h | 7 ++ 6 files changed, 113 insertions(+), 162 deletions(-) diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h index 5ca1275fd8f35..a55a4e409feda 100644 --- a/drivers/cxl/core/core.h +++ b/drivers/cxl/core/core.h @@ -186,11 +186,11 @@ static inline struct device *dport_to_host(struct cxl= _dport *dport) void cxl_ras_init(void); void cxl_ras_exit(void); bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, - void __iomem *ras_base); + void __iomem *ras_base, u64 serial); void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport); void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, - void __iomem *ras_base); + void __iomem *ras_base, u64 serial); void cxl_dport_map_rch_aer(struct cxl_dport *dport); void cxl_disable_rch_root_ints(struct cxl_dport *dport); void cxl_handle_rdport_errors(struct pci_dev *pdev); @@ -200,14 +200,14 @@ void devm_cxl_dport_ras_setup(struct cxl_dport *dport= ); static inline void cxl_ras_init(void) { } static inline void cxl_ras_exit(void) { } static inline bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport = *dport, - void __iomem *ras_base) + void __iomem *ras_base, u64 serial) { return false; } static inline void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *= port, struct cxl_dport *dport) { } static inline void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dp= ort *dport, - void __iomem *ras_base) { } + void __iomem *ras_base, u64 serial) { } static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { } static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { } static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { } diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index d5dc2c22565da..acf40b2396c3b 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -12,69 +12,37 @@ static_assert(CXL_HEADERLOG_TRACE_SIZE_U32 =3D=3D 128, "rasdaemon ABI requires exactly 128 u32s"); =20 -static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev, - struct cxl_ras_capability_regs ras_cap) -{ - u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; - - trace_cxl_port_aer_correctable_error(&pdev->dev, status); -} - -static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev, - struct cxl_ras_capability_regs ras_cap) +static void cxl_cper_trace_uncorr_prot_err(struct cxl_port *port, struct c= xl_dport *dport, + u64 serial, struct cxl_ras_capability_regs *ras_cap) { u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; - u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; + u32 status =3D ras_cap->uncor_status & ~ras_cap->uncor_mask; u32 fe; =20 if (hweight32(status) > 1) fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, - ras_cap.cap_control)); - else - fe =3D status; - - memcpy(hl, ras_cap.header_log, CXL_HEADERLOG_SIZE); - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe, hl); -} - -static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd, - struct cxl_ras_capability_regs ras_cap) -{ - u32 status =3D ras_cap.cor_status & ~ras_cap.cor_mask; - - trace_cxl_aer_correctable_error(cxlmd, status); -} - -static void -cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd, - struct cxl_ras_capability_regs ras_cap) -{ - u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; - u32 status =3D ras_cap.uncor_status & ~ras_cap.uncor_mask; - u32 fe; - - if (hweight32(status) > 1) - fe =3D BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, - ras_cap.cap_control)); + ras_cap->cap_control)); else fe =3D status; =20 /* - * ras_cap.header_log[] holds CXL_HEADERLOG_SIZE_U32 (16) hardware + * ras_cap->header_log[] holds CXL_HEADERLOG_SIZE_U32 (16) hardware * dwords. Copy them into the front of a zero-filled * CXL_HEADERLOG_TRACE_SIZE_U32 (128) u32 staging buffer so the trace * event memcpy sees a full 512-byte source and the userspace ABI * (rasdaemon) is preserved. */ - memcpy(hl, ras_cap.header_log, CXL_HEADERLOG_SIZE); - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, hl); + memcpy(hl, ras_cap->header_log, CXL_HEADERLOG_SIZE); + trace_cxl_aer_uncorrectable_error(port, dport, status, fe, + hl, serial); } =20 -static int match_memdev_by_parent(struct device *dev, const void *uport) +static void cxl_cper_trace_corr_prot_err(struct cxl_port *port, struct cxl= _dport *dport, + u64 serial, struct cxl_ras_capability_regs *ras_cap) { - if (is_cxl_memdev(dev) && dev->parent =3D=3D uport) - return 1; - return 0; + u32 status =3D ras_cap->cor_status & ~ras_cap->cor_mask; + + trace_cxl_aer_correctable_error(port, dport, status, serial); } =20 =20 @@ -109,47 +77,34 @@ static struct cxl_port *find_cxl_port_by_dev(struct de= vice *dev, struct cxl_dpor =20 void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data) { + struct cxl_dport *dport; unsigned int devfn =3D PCI_DEVFN(data->prot_err.agent_addr.device, data->prot_err.agent_addr.function); - struct pci_dev *pdev __free(pci_dev_put) =3D - pci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment, - data->prot_err.agent_addr.bus, - devfn); - struct cxl_memdev *cxlmd; - int port_type; - - if (!pdev) - return; - - port_type =3D pci_pcie_type(pdev); - if (port_type =3D=3D PCI_EXP_TYPE_ROOT_PORT || - port_type =3D=3D PCI_EXP_TYPE_DOWNSTREAM || - port_type =3D=3D PCI_EXP_TYPE_UPSTREAM) { - if (data->severity =3D=3D AER_CORRECTABLE) - cxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap); - else - cxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap); - + struct pci_dev *pdev __free(pci_dev_put) =3D pci_get_domain_bus_and_slot( + data->prot_err.agent_addr.segment, data->prot_err.agent_addr.bus, devfn); + if (!pdev) { + pr_err_ratelimited("Failed to find CPER device in CXL topology\n"); return; } =20 - guard(device)(&pdev->dev); - if (!pdev->dev.driver) { - dev_warn_ratelimited(&pdev->dev, - "Device is unbound, abort CPER error handling\n"); + struct cxl_port *port __free(put_cxl_port) =3D find_cxl_port_by_dev(&pdev= ->dev, NULL); + if (!port) { + dev_err_ratelimited(&pdev->dev, + "Failed to find parent port device in CXL topology\n"); return; } =20 - struct device *mem_dev __free(put_device) =3D bus_find_device( - &cxl_bus_type, NULL, pdev, match_memdev_by_parent); - if (!mem_dev) - return; + guard(device)(&port->dev); + + /* dport is NULL for Endpoint and Upstream Port devices */ + dport =3D cxl_find_dport_by_dev(port, &pdev->dev); =20 - cxlmd =3D to_cxl_memdev(mem_dev); if (data->severity =3D=3D AER_CORRECTABLE) - cxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap); + cxl_cper_trace_corr_prot_err(port, dport, pci_get_dsn(pdev), + &data->ras_cap); else - cxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap); + cxl_cper_trace_uncorr_prot_err(port, dport, pci_get_dsn(pdev), + &data->ras_cap); } EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err); =20 @@ -240,14 +195,14 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl= _port *port, struct cxl_dpo return; } =20 - if (cxl_handle_ras(port, dport, ras_base)) + if (cxl_handle_ras(port, dport, ras_base, pci_get_dsn(pdev))) panic("CXL cachemem error"); =20 dev_dbg(&pdev->dev, "CXL UCE signaled but no CXL RAS status bits set\n"); } =20 -void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, vo= id __iomem *ras_base) +void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport, vo= id __iomem *ras_base, u64 serial) { u32 status; void __iomem *addr; @@ -259,12 +214,7 @@ void cxl_handle_cor_ras(struct cxl_port *port, struct = cxl_dport *dport, void __i status =3D readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); - if (is_cxl_endpoint(port)) - trace_cxl_aer_correctable_error(to_cxl_memdev(port->uport_dev), status); - else if (dport) - trace_cxl_port_aer_correctable_error(dport->dport_dev, status); - else - trace_cxl_port_aer_correctable_error(port->uport_dev, status); + trace_cxl_aer_correctable_error(port, dport, status, serial); } } =20 @@ -289,7 +239,8 @@ static void header_log_copy(void __iomem *ras_base, u32= *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, void _= _iomem *ras_base) +bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, + void __iomem *ras_base, u64 serial) { u32 hl[CXL_HEADERLOG_TRACE_SIZE_U32] =3D {}; void __iomem *addr; @@ -316,12 +267,7 @@ bool cxl_handle_ras(struct cxl_port *port, struct cxl_= dport *dport, void __iomem } =20 header_log_copy(ras_base, hl); - if (is_cxl_endpoint(port)) - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(port->uport_dev), status= , fe, hl); - else if (dport) - trace_cxl_port_aer_uncorrectable_error(dport->dport_dev, status, fe, hl); - else - trace_cxl_port_aer_uncorrectable_error(port->uport_dev, status, fe, hl); + trace_cxl_aer_uncorrectable_error(port, dport, status, fe, hl, serial); =20 writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); =20 @@ -360,7 +306,8 @@ pci_ers_result_t cxl_pci_error_detected(struct pci_dev = *pdev, * cases below handle AER recovery for devices without active * CXL.mem traffic. */ - ue =3D cxl_handle_ras(port, NULL, to_ras_base(port, NULL)); + ue =3D cxl_handle_ras(port, NULL, to_ras_base(port, NULL), + pci_get_dsn(pdev)); } =20 /* @@ -392,7 +339,7 @@ static void cxl_handle_proto_error(struct pci_dev *pdev= , struct cxl_port *port, struct cxl_dport *dport, int severity) { if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(port, dport, to_ras_base(port, dport)); + cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), pci_get_dsn(pd= ev)); else cxl_do_recovery(pdev, port, dport); } diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index f4b98f2c11a1c..0385d2f4a2f66 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -118,7 +118,8 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport)); + cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport), + pci_get_dsn(pdev)); else cxl_do_recovery(pdev, dport->port, dport); } diff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c index 7f2a9dd0d0e3f..df42d119c53dd 100644 --- a/drivers/cxl/core/trace.c +++ b/drivers/cxl/core/trace.c @@ -2,7 +2,42 @@ /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ =20 #include +#include #include "core.h" =20 +const char *cxl_trace_memdev_name(struct cxl_port *port) +{ + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + + return dev_name(&cxlmd->dev); + } + + return ""; +} + +const char *cxl_trace_host_name(struct cxl_port *port) +{ + if (is_cxl_endpoint(port)) { + struct cxl_memdev *cxlmd =3D to_cxl_memdev(port->uport_dev); + + return dev_name(cxlmd->dev.parent); + } + + return dev_name(port->uport_dev); +} + +const char *cxl_trace_port_name(struct cxl_port *port) +{ + return dev_name(&port->dev); +} + +const char *cxl_trace_dport_name(struct cxl_dport *dport) +{ + if (dport) + return dev_name(dport->dport_dev); + return ""; +} + #define CREATE_TRACE_POINTS #include "trace.h" diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h index d37876096dd7c..910aceb2ca3ab 100644 --- a/drivers/cxl/core/trace.h +++ b/drivers/cxl/core/trace.h @@ -48,44 +48,15 @@ { CXL_RAS_UC_IDE_RX_ERR, "IDE Rx Error" } \ ) =20 -TRACE_EVENT(cxl_port_aer_uncorrectable_error, - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl), - TP_ARGS(dev, status, fe, hl), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - __field(u32, first_error) - __array(u32, header_log, CXL_HEADERLOG_TRACE_SIZE_U32) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - __entry->first_error =3D fe; - /* - * Embed headerlog data for user app retrieval and parsing, - * but no need to print in the trace buffer. Only - * CXL_HEADERLOG_SIZE_U32 (16) dwords are hardware data; - * the remaining entries preserve the 512-byte ABI layout - * rasdaemon depends on and are zero-filled by the caller. - */ - memcpy(__entry->header_log, hl, - CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32)); - ), - TP_printk("device=3D%s host=3D%s status: '%s' first_error: '%s'", - __get_str(device), __get_str(host), - show_uc_errs(__entry->status), - show_uc_errs(__entry->first_error) - ) -); - TRACE_EVENT(cxl_aer_uncorrectable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl), - TP_ARGS(cxlmd, status, fe, hl), + TP_PROTO(struct cxl_port *port, struct cxl_dport *dport, + u32 status, u32 fe, u32 *hl, u64 serial), + TP_ARGS(port, dport, status, fe, hl, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, cxl_trace_memdev_name(port)) + __string(port, cxl_trace_port_name(port)) + __string(dport, cxl_trace_dport_name(dport)) + __string(host, cxl_trace_host_name(port)) __field(u64, serial) __field(u32, status) __field(u32, first_error) @@ -93,8 +64,10 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, ), TP_fast_assign( __assign_str(memdev); + __assign_str(port); + __assign_str(dport); __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __entry->serial =3D serial; __entry->status =3D status; __entry->first_error =3D fe; /* @@ -107,8 +80,9 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, memcpy(__entry->header_log, hl, CXL_HEADERLOG_TRACE_SIZE_U32 * sizeof(u32)); ), - TP_printk("memdev=3D%s host=3D%s serial=3D%lld: status: '%s' first_error:= '%s'", - __get_str(memdev), __get_str(host), __entry->serial, + TP_printk("memdev=3D%s port=3D%s dport=3D%s host=3D%s serial=3D%lld: stat= us: '%s' first_error: '%s'", + __get_str(memdev), __get_str(port), __get_str(dport), + __get_str(host), __entry->serial, show_uc_errs(__entry->status), show_uc_errs(__entry->first_error) ) @@ -132,42 +106,29 @@ TRACE_EVENT(cxl_aer_uncorrectable_error, { CXL_RAS_CE_PHYS_LAYER_ERR, "Received Error From Physical Layer" } \ ) =20 -TRACE_EVENT(cxl_port_aer_correctable_error, - TP_PROTO(struct device *dev, u32 status), - TP_ARGS(dev, status), - TP_STRUCT__entry( - __string(device, dev_name(dev)) - __string(host, dev_name(dev->parent)) - __field(u32, status) - ), - TP_fast_assign( - __assign_str(device); - __assign_str(host); - __entry->status =3D status; - ), - TP_printk("device=3D%s host=3D%s status=3D'%s'", - __get_str(device), __get_str(host), - show_ce_errs(__entry->status) - ) -); - TRACE_EVENT(cxl_aer_correctable_error, - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status), - TP_ARGS(cxlmd, status), + TP_PROTO(struct cxl_port *port, struct cxl_dport *dport, + u32 status, u64 serial), + TP_ARGS(port, dport, status, serial), TP_STRUCT__entry( - __string(memdev, dev_name(&cxlmd->dev)) - __string(host, dev_name(cxlmd->dev.parent)) + __string(memdev, cxl_trace_memdev_name(port)) + __string(port, cxl_trace_port_name(port)) + __string(dport, cxl_trace_dport_name(dport)) + __string(host, cxl_trace_host_name(port)) __field(u64, serial) __field(u32, status) ), TP_fast_assign( __assign_str(memdev); + __assign_str(port); + __assign_str(dport); __assign_str(host); - __entry->serial =3D cxlmd->cxlds->serial; + __entry->serial =3D serial; __entry->status =3D status; ), - TP_printk("memdev=3D%s host=3D%s serial=3D%lld: status: '%s'", - __get_str(memdev), __get_str(host), __entry->serial, + TP_printk("memdev=3D%s port=3D%s dport=3D%s host=3D%s serial=3D%lld: stat= us: '%s'", + __get_str(memdev), __get_str(port), __get_str(dport), + __get_str(host), __entry->serial, show_ce_errs(__entry->status) ) ); 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Fri, 17 Jul 2026 17:29:18 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 11/13] PCI: Cache PCI DSN into pci_dev->dsn during probe Date: Fri, 17 Jul 2026 17:27:04 -0500 Message-ID: <20260717222706.3540281-12-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|BL3PR12MB6521:EE_ X-MS-Office365-Filtering-Correlation-Id: bb52cb4c-8a01-4a4a-cf78-08dee452d839 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|23010399003|376014|1800799024|6133799003|56012099006|11063799006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: cvD165g+fkhnl5f+WuX7JbhIbItD4yFE2+gvGB0MyW7BXddHmNJBzxCi0iqihzWFK5m2nhJnrj5aogVfhVA4zT0G/IFFn/mbV5RcWeRAmG7dO3hM8OaOZ3Iv5M28JlJQnvr6kW2PRW3+b91BVw4soGDQw7YIZMl9GYA8fmOHB+gsKhD1yU4HUqpvqX7mfJknboMsCA4b9LQD5BlhT3t/ylrg8emrpjlZC0bdgKClVl/Ju1+awgSZa50CE9teI/sXk6RCcHIABjwf3FoS7u9hjWcolVuqw1haoqULRo2em9otjCQ0KeCHPvZ6aSy6Y6Kqkt7Ynwdwq6fbYtpcoRFwTMd6t+fnfwJ8ut3hckdzR7ugjMX4DJpzF9ObzC899HihdLKiqQMZJFuJ8ws2R/pwBGQFUrRBlPW1yfwRWuQi+RyFRMNFCDu/tGhdRCFQDkfloTkuy6Pdg6ptEgvUuWDhfa7SAOereAydp/PMCNT1iiX5kDars44Edm/JodUPQoi8MbNZxQBZIrTTywUcCJunaMw5RFiDLuMhdWm1iMJ36B6CyRjWedc/HR2rU+iKv4B7U43QwmoRHLtVs4D7NrlGEA/g4QDYAb8rt4qk7VwVlwVbEGtc+T2lSiiJWLX/NTDROo6xibLCa17tUn01wWeJ3EOzSWGs3j+AK0QN73EQ46xoFtlJjpM6K9oMmCo5dFmPCZuTEm8cAQqSOLTmEdug8g== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(7416014)(23010399003)(376014)(1800799024)(6133799003)(56012099006)(11063799006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gMrsoUE2T3tLHTULWXF85fweqnd0xsAkr4bsR+YRcTTby6yzq6x5PQ0cpvReR0Fzu+hQM0gQ6gTFQNglaHvowLoOXVqN5dNwQpsmo6VRTBwgEacvMZR0VtPufgCw3WabvRuRwCeHq28ypw0U3ZOLnOU+yrH+aztQwV1+KZUOLkaCs25wzVp/SP6DzOb9O6L0wZ4rzmoaMUEwOdm0GajaHql6sAK62sX2/8BCmPLXUiz+VZ84w9ELFBnTXblD33XUNJMYKMhT5KpYsXH4bLng001uijAAg7P/KHTpJ6ucot0PRfMky96mL9XomeKb7+EQyJ9rD7QgmE0Cd7BR0Oj8WLStU1aZ1lNy3FZbmRvNj06UeVylATp1pQ6HoRmzzIg/2fHQ5fnOm4z5lm3QhgxFtZrUEMgvpPHXsnKvKawpOrH8xI308yzQBRtKZJEAtKcx X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:29:19.8037 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bb52cb4c-8a01-4a4a-cf78-08dee452d839 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6521 Content-Type: text/plain; charset="utf-8" Subsequent CXL error-reporting code paths need to log the PCI Device Serial Number (DSN) as part of trace events emitted from interrupt or panic context. Computing the DSN there via pci_get_dsn() requires PCI configuration space reads, which are slow, can fail when the link is down or frozen, and may not be safe in some contexts. Add a u64 dsn field to struct pci_dev and populate it from pci_get_dsn() during pci_init_capabilities() at probe time via pci_dsn_init(). Only write dev->dsn when the read succeeds. The zero initial value from pci_dev allocation already represents 'no DSN available.' pci_get_dsn() is not modified because it remains a pure config-space read with no side effects on pci_dev. The cache is written exclusively by pci_dsn_init() at probe time. Signed-off-by: Terry Bowman --- Changes in v17->v18: - New commit. --- drivers/cxl/core/ras.c | 11 ++++++----- drivers/cxl/core/ras_rch.c | 4 ++-- drivers/cxl/pci.c | 2 +- drivers/pci/probe.c | 14 ++++++++++++++ include/linux/pci.h | 1 + 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index acf40b2396c3b..69b320c74469c 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -100,10 +100,10 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_er= r_work_data *data) dport =3D cxl_find_dport_by_dev(port, &pdev->dev); =20 if (data->severity =3D=3D AER_CORRECTABLE) - cxl_cper_trace_corr_prot_err(port, dport, pci_get_dsn(pdev), + cxl_cper_trace_corr_prot_err(port, dport, pdev->dsn, &data->ras_cap); else - cxl_cper_trace_uncorr_prot_err(port, dport, pci_get_dsn(pdev), + cxl_cper_trace_uncorr_prot_err(port, dport, pdev->dsn, &data->ras_cap); } EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err); @@ -195,7 +195,7 @@ void cxl_do_recovery(struct pci_dev *pdev, struct cxl_p= ort *port, struct cxl_dpo return; } =20 - if (cxl_handle_ras(port, dport, ras_base, pci_get_dsn(pdev))) + if (cxl_handle_ras(port, dport, ras_base, pdev->dsn)) panic("CXL cachemem error"); =20 dev_dbg(&pdev->dev, @@ -307,7 +307,7 @@ pci_ers_result_t cxl_pci_error_detected(struct pci_dev = *pdev, * CXL.mem traffic. */ ue =3D cxl_handle_ras(port, NULL, to_ras_base(port, NULL), - pci_get_dsn(pdev)); + pdev->dsn); } =20 /* @@ -339,7 +339,8 @@ static void cxl_handle_proto_error(struct pci_dev *pdev= , struct cxl_port *port, struct cxl_dport *dport, int severity) { if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), pci_get_dsn(pd= ev)); + cxl_handle_cor_ras(port, dport, to_ras_base(port, dport), + pdev->dsn); else cxl_do_recovery(pdev, port, dport); } diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c index 0385d2f4a2f66..14bb3bdb2d092 100644 --- a/drivers/cxl/core/ras_rch.c +++ b/drivers/cxl/core/ras_rch.c @@ -118,8 +118,8 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev) =20 pci_print_aer(pdev, severity, &aer_regs); if (severity =3D=3D AER_CORRECTABLE) - cxl_handle_cor_ras(dport->port, dport, to_ras_base(port, dport), - pci_get_dsn(pdev)); + cxl_handle_cor_ras(dport->port, dport, + to_ras_base(port, dport), pdev->dsn); else cxl_do_recovery(pdev, dport->port, dport); } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 6cf1db7b85020..45a994cc782a9 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -807,7 +807,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) if (!dvsec) pci_warn(pdev, "Device DVSEC not present, skip CXL.mem init\n"); =20 - mds =3D cxl_memdev_state_create(&pdev->dev, pci_get_dsn(pdev), dvsec); + mds =3D cxl_memdev_state_create(&pdev->dev, pdev->dsn, dvsec); if (IS_ERR(mds)) return PTR_ERR(mds); cxlds =3D &mds->cxlds; diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index dd0abbc63e18d..92ece5ec211f8 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2638,6 +2638,19 @@ void pcie_report_downtraining(struct pci_dev *dev) __pcie_print_link_status(dev, false); } =20 +/* + * Cache the Device Serial Number for use in contexts where config-space + * reads are unsafe (interrupt, panic). Process-context callers that + * need a fresh value (e.g. hotplug device replacement) use pci_get_dsn(). + */ +static void pci_dsn_init(struct pci_dev *dev) +{ + u64 dsn =3D pci_get_dsn(dev); + + if (dsn) + dev->dsn =3D dsn; +} + static void pci_imm_ready_init(struct pci_dev *dev) { u16 status; @@ -2674,6 +2687,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_rebar_init(dev); /* Resizable BAR */ pci_dev3_init(dev); /* Device 3 capabilities */ pci_ide_init(dev); /* Link Integrity and Data Encryption */ + pci_dsn_init(dev); /* Serial number */ =20 pcie_report_downtraining(dev); pci_init_reset_methods(dev); diff --git a/include/linux/pci.h b/include/linux/pci.h index 64b308b6e61c1..48a1622639190 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -386,6 +386,7 @@ struct pci_dev { unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */ =20 struct pci_driver *driver; /* Driver bound to this device */ + u64 dsn; /* PCI Device Serial Number */ u64 dma_mask; /* Mask of the bits of bus address this device implements. Normally this is 0xffffffff. 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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SJ1PEPF0000231A.mail.protection.outlook.com (10.167.242.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Fri, 17 Jul 2026 22:29:31 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Fri, 17 Jul 2026 17:29:29 -0500 From: Terry Bowman To: Bjorn Helgaas , Dan Williams , "Dave Jiang" , Ira Weiny , Jonathan Cameron , Len Brown , "Rafael J . Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . De Francesco" , Gregory Price , Hanjun Guo , Jonathan Corbet , Kees Cook , Kuppuswamy Sathyanarayanan , Li Ming , Mahesh J Salgaonkar , Mauro Carvalho Chehab , Oliver O'Halloran , Shiju Jose , Shuah Khan , Shuai Xue , Smita Koralahalli , Terry Bowman , Tony Luck , Vishal Verma Subject: [PATCH v18 12/13] PCI/CXL: Mask/Unmask CXL protocol errors Date: Fri, 17 Jul 2026 17:27:05 -0500 Message-ID: <20260717222706.3540281-13-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717222706.3540281-1-terry.bowman@amd.com> References: <20260717222706.3540281-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|PH7PR12MB6884:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d7070ef-bbdd-4c26-1fde-08dee452df0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|376014|36860700016|82310400026|1800799024|10067099003|6133799003|56012099006|11063799006|3023799007|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: fIke7sjxCDFeF+d/Zst3o2e1CcI0U1F5A4bAbzONGUwurGlkoLGGiz61QYAbzDuTWjWrWsth8rTi+cWhC9cUCnTqAVdgl6u2tmqsoqThjwkU6l7tf/xEx5N7+uSMO3hSV0W/cM455+pIF9lNQrChRzPMIb/EktQDn67G9g+yT0CThB6OJMDkYid4aWT7MVGFKHGhfXzjPReWHaXDHmqyZzxS41ukVSzFfCHRfhsUQRi+N2/PlbMKwO8EynuP6EIi0eoji6+2s/HM71pLi8G+MiFXTa0xIxXg2TmRxqAoSW07kCVqIP1jYtSk3HQUHJxLe1Wz+4Ziu2QBtvABrDTzW4py7PiidjYcQD7bNelD7I+XCswhRThoAeMjJImx3eM13FPsNdB+IP6Yd26spac/ihp/uLnFb3VHazPnFbgKtzct6yEWfn+Qm7KFudMSbkJD2QFWmyJ88usLfqGDPz3nQ1cmRHDS4zuBDbKM5CNse4oTRtjIlWir58ZEqU0AeYfUTgvSos+EHKTCukrGkJ0TFTxo8BoXbvP11JbyzuoEidI/yYm1zrVlKrd2TeQ0/w7MrzTFHvWyyBZl8x2tfiouWtS7B1h8O8W36wgi6cBriTXci4qZKi8ZDDY1ZqQbB1BGcdJDyKL6BpqyLf80wYbNoPp5cNQI75qr5GMTnE3+navcH9TmQUvbx3Bn9U5GqLKHVAO3vVMA8y4M9LfHuaJMoA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(7416014)(376014)(36860700016)(82310400026)(1800799024)(10067099003)(6133799003)(56012099006)(11063799006)(3023799007)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: AlC3oxhTxyrnKVxYuxd0GOEKjxYLFBmxTgVmnRRnLKYcuxtvbeFnaA3QlWESpLS2I7v0BfdDgl5KschZvAO3DHO523xgstGLfaBnekKosnJBPMHnNJ/ZFoKxZ4aHIOUQbHtgGTMyd5mCQQq4OD93ZFIroTfAkTZOv4uMA1o7zf7YBrtLDs5msHGmHA6MqWoB5wjftGRY7Ey0MuapJfDEzJMe7am4Rx40sDjOVcptwUwe8NCHL8qb9Uk+xo5p3ALnKcWvRI+wqhUGdTKeRZbYTdkGSumCQoDOyI7zJnaanaZyAT9Y02iRbR5kJ34EI7Lw1A62iwlA3mTJSF6t5RnqpQ4xqTAO9TtqgXhxemoeiy1Pkgou1+jgcfVDPrhoyALK0Id6gzXhMqbD/d1NcWK9r2G9rMzUIr/XvR2yOPv30IHDWQDLffgVLY6JuVfuU+lv X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 22:29:31.2481 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d7070ef-bbdd-4c26-1fde-08dee452df0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6884 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. They must be enabled in order to process CXL protocol errors. Provide matching teardown helpers so the masks are restored when a CXL Port or dport goes away. Add pci_aer_mask_internal_errors() as the symmetric counterpart to pci_aer_unmask_internal_errors() and export both for the cxl_core module. Introduce cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts() in cxl_core to wrap the PCI helpers with the dev_is_pci() and pcie_aer_is_native() gating CXL needs. Both helpers tolerate a NULL or non-PCI @dev so callers do not have to special-case it. Wire cxl_unmask_proto_interrupts() into the success path of cxl_dport_map_ras() and devm_cxl_port_ras_setup() so the unmask only runs when the RAS register block was actually mapped. Pair each unmask with a devm_add_action_or_reset() registration of cxl_mask_proto_irqs() scoped to the host device so the mask is restored when devres is released. This applies to dports, Endpoints, Upstream Switch Ports, Downstream Switch Ports, and Root Ports. Remove the dev_is_pci(dport->dport_dev) guard in devm_cxl_dport_rch_ras_setup(). On RCH systems dport->dport_dev is the pci_host_bridge device, which is not on pci_bus_type, so this guard caused the function to return early on real hardware without mapping dport RAS or AER registers. The caller already gates on dport->rch, which is sufficient to exclude cxl_test mock devices. Co-developed-by: Dan Williams Signed-off-by: Dan Williams Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v17->v18: - Make cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts() static - Remove dev_is_pci() guard from devm_cxl_dport_rch_ras_setup(); the guard blocked real RCH hardware because pci_host_bridge is not on pci_bus_type Changes in v16->v17: - Drop redundant cxl_mask_proto_interrupts() calls from unregister_port() and cxl_dport_remove(); the devres action registered alongside the unmask is the sole mask path. - Update title - Remove unnecessary check for aer_capabilities - Gate cxl_unmask_proto_interrupts() on pcie_aer_is_native() - Add pci_aer_mask_internal_errors() and cxl_mask_proto_interrupts() - Only unmask on successful cxl_map_component_regs() - NULL-check @dev in cxl_{un,}mask_proto_interrupts() - Drop static and declare in core/core.h Change in v15 -> v16: - None Change in v14 -> v15: - None Changes in v13->v14: - Update commit title's prefix (Bjorn) Changes in v12->v13: - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Te= rry) - Add Dave Jiang's and Ben's review-by Changes in v11->v12: - None --- drivers/cxl/core/ras.c | 73 +++++++++++++++++++++++++++++++---- drivers/pci/pcie/aer.c | 28 ++++++++++++-- include/linux/aer.h | 2 + tools/testing/cxl/Kbuild | 1 + tools/testing/cxl/test/mock.c | 12 ++++++ 5 files changed, 105 insertions(+), 11 deletions(-) diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c index 69b320c74469c..d77208af41e03 100644 --- a/drivers/cxl/core/ras.c +++ b/drivers/cxl/core/ras.c @@ -117,16 +117,64 @@ static void cxl_cper_prot_err_work_fn(struct work_str= uct *work) } static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn); =20 +static void cxl_unmask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev; + + if (!dev || !dev_is_pci(dev)) + return; + + pdev =3D to_pci_dev(dev); + if (!pcie_aer_is_native(pdev)) + return; + + pci_aer_unmask_internal_errors(pdev); +} + +static void cxl_mask_proto_interrupts(struct device *dev) +{ + struct pci_dev *pdev; + + if (!dev || !dev_is_pci(dev)) + return; + + pdev =3D to_pci_dev(dev); + if (!pcie_aer_is_native(pdev)) + return; + + pci_aer_mask_internal_errors(pdev); +} + +static void cxl_mask_proto_irqs(void *dev) +{ + cxl_mask_proto_interrupts(dev); +} + static void cxl_dport_map_ras(struct cxl_dport *dport) { struct cxl_register_map *map =3D &dport->reg_map; struct device *dev =3D dport->dport_dev; =20 - if (!map->component_map.ras.valid) + if (!map->component_map.ras.valid) { dev_dbg(dev, "RAS registers not found\n"); - else if (cxl_map_component_regs(map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + return; + } + + if (cxl_map_component_regs(map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(dev, "Failed to map RAS capability.\n"); + return; + } + + if (!dev_is_pci(dev)) + return; + + cxl_unmask_proto_interrupts(dev); + if (devm_add_action_or_reset(dport_to_host(dport), + cxl_mask_proto_irqs, dev)) { + dev_warn(dev, "failed to defer CXL proto-irq mask; CXL protocol error re= porting disabled\n"); + dport->regs.component.ras =3D NULL; + } } =20 /** @@ -143,9 +191,6 @@ void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dpo= rt) { struct pci_host_bridge *host_bridge; =20 - if (!dev_is_pci(dport->dport_dev)) - return; - devm_cxl_dport_ras_setup(dport); =20 host_bridge =3D to_pci_host_bridge(dport->dport_dev); @@ -160,6 +205,7 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_rch_ras_setup, "CXL= "); void devm_cxl_port_ras_setup(struct cxl_port *port) { struct cxl_register_map *map =3D &port->reg_map; + struct device *dev; =20 if (!map->component_map.ras.valid) { dev_dbg(&port->dev, "RAS registers not found\n"); @@ -168,8 +214,21 @@ void devm_cxl_port_ras_setup(struct cxl_port *port) =20 map->host =3D &port->dev; if (cxl_map_component_regs(map, &port->regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(&port->dev, "Failed to map RAS capability\n"); + return; + } + + dev =3D is_cxl_endpoint(port) ? port->uport_dev->parent : port->uport_dev; + if (!dev_is_pci(dev)) + return; + + cxl_unmask_proto_interrupts(dev); + if (devm_add_action_or_reset(&port->dev, cxl_mask_proto_irqs, dev)) { + dev_warn(&port->dev, + "failed to defer CXL proto-irq mask; CXL protocol error reporting disa= bled\n"); + port->regs.ras =3D NULL; + } } EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, "CXL"); =20 diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 0bd23a65e7ebc..be6dc2cbd4491 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1143,12 +1143,32 @@ void pci_aer_unmask_internal_errors(struct pci_dev = *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); =20 -/* - * Internal errors are too device-specific to enable generally, however fo= r CXL - * their behavior is standardized for conveying CXL protocol errors. +/** + * pci_aer_mask_internal_errors - mask internal errors + * @dev: pointer to the pci_dev data structure + * + * Mask internal errors in the Uncorrectable and Correctable Error + * Mask registers. + * + * Note: AER must be enabled and supported by the device which must be + * checked in advance, e.g. with pcie_aer_is_native(). */ -EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); +void pci_aer_mask_internal_errors(struct pci_dev *dev) +{ + int aer =3D dev->aer_cap; + u32 mask; + + pci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask); + mask |=3D PCI_ERR_UNC_INTN; + pci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask); + + pci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask); + mask |=3D PCI_ERR_COR_INTERNAL; + pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); +} +EXPORT_SYMBOL_FOR_MODULES(pci_aer_mask_internal_errors, "cxl_core"); =20 /** * pci_aer_handle_error - handle logging error into an event log diff --git a/include/linux/aer.h b/include/linux/aer.h index 8eba3192e2d15..b3657b80564b9 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -58,6 +58,7 @@ struct aer_capability_regs { int pci_aer_clear_nonfatal_status(struct pci_dev *dev); int pcie_aer_is_native(struct pci_dev *dev); void pci_aer_unmask_internal_errors(struct pci_dev *dev); +void pci_aer_mask_internal_errors(struct pci_dev *dev); #else static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev) { @@ -65,6 +66,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pc= i_dev *dev) } static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; } static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { } +static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { } #endif =20 #ifdef CONFIG_CXL_RAS diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild index 2be1df80fcc93..957945201f04d 100644 --- a/tools/testing/cxl/Kbuild +++ b/tools/testing/cxl/Kbuild @@ -6,6 +6,7 @@ ldflags-y +=3D --wrap=3Dacpi_pci_find_root ldflags-y +=3D --wrap=3Dnvdimm_bus_register ldflags-y +=3D --wrap=3Dcxl_await_media_ready ldflags-y +=3D --wrap=3Ddevm_cxl_add_rch_dport +ldflags-y +=3D --wrap=3Ddevm_cxl_dport_rch_ras_setup ldflags-y +=3D --wrap=3Dcxl_endpoint_parse_cdat ldflags-y +=3D --wrap=3Ddevm_cxl_endpoint_decoders_setup ldflags-y +=3D --wrap=3Dhmat_get_extended_linear_cache_size diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c index 6454b868b122c..5ad3243da8d29 100644 --- a/tools/testing/cxl/test/mock.c +++ b/tools/testing/cxl/test/mock.c @@ -220,6 +220,18 @@ struct cxl_dport *__wrap_devm_cxl_add_rch_dport(struct= cxl_port *port, } EXPORT_SYMBOL_NS_GPL(__wrap_devm_cxl_add_rch_dport, "CXL"); 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Wysocki" , Robert Richter CC: , , , , , , "Alejandro Lucero" , Alison Schofield , Ankit Agrawal , Ard Biesheuvel , "Ben Cheatham" , Borislav Petkov , "Breno Leitao" , Davidlohr Bueso , "Fabio M . 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This documents the architecture introduced by the preceding patches in this series. Assisted-by: Claude:claude-opus-4.7 Signed-off-by: Terry Bowman Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron --- Changes in v17->v18: - Simplify document for readability (Jonathan) - Drop historical context that goes stale (Jonathan) - Shorten ASCII flow diagram (Jonathan) - Drop manual backtick markup, use automarkup (Jonathan) - Clarify USP/DSP as single switch component (Dave) - Fix line wrapping to 80 chars (Jonathan) --- Documentation/driver-api/cxl/index.rst | 1 + .../cxl/linux/protocol-error-handling.rst | 222 ++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 Documentation/driver-api/cxl/linux/protocol-error-handl= ing.rst diff --git a/Documentation/driver-api/cxl/index.rst b/Documentation/driver-= api/cxl/index.rst index 3dfae1d310ca5..6861b2e5726a3 100644 --- a/Documentation/driver-api/cxl/index.rst +++ b/Documentation/driver-api/cxl/index.rst @@ -42,6 +42,7 @@ that have impacts on each other. The docs here break up = configurations steps. linux/dax-driver linux/memory-hotplug linux/access-coordinates + linux/protocol-error-handling =20 .. toctree:: :maxdepth: 2 diff --git a/Documentation/driver-api/cxl/linux/protocol-error-handling.rst= b/Documentation/driver-api/cxl/linux/protocol-error-handling.rst new file mode 100644 index 0000000000000..67f0492e56702 --- /dev/null +++ b/Documentation/driver-api/cxl/linux/protocol-error-handling.rst @@ -0,0 +1,222 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +CXL Protocol Error Handling +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + +CXL devices report protocol-layer failures (CXL.cachemem RAS) as PCIe +AER Internal Errors: PCI_ERR_COR_INTERNAL for correctable events and +PCI_ERR_UNC_INTN for uncorrectable events. The actual fault +information lives in CXL RAS capability registers, not in the PCIe AER +status registers. + +The kernel routes every CXL Internal Error through a producer/consumer +pipeline shared by all CXL device types: Root Ports, Upstream/Downstream +Switch Ports, Endpoints, and Restricted CXL Devices (RCDs). + + +Architecture +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Two error planes run side by side: + +* The **PCIe AER plane** handles native PCIe errors (receiver + overflows, malformed TLPs, completion timeouts, etc.). +* The **CXL protocol error plane** handles CXL Internal Errors. + The AER core forwards them to cxl_core via a dedicated kfifo; + cxl_core reads the CXL RAS registers, emits trace events, and + applies recovery/panic policy. + +The boundary between the two planes is enforced by is_cxl_error() in +aer_cxl_vh.c. It checks info->is_cxl, the PCIe device type +(Endpoint, Root Port, Upstream, or Downstream), and whether the AER +status word indicates an internal error. RC_END devices are excluded +from is_cxl_error() because they reach the kfifo via the separate +cxl_rch_handle_error() path instead. + +The pipeline: + +1. **Producer** (aer_cxl_vh.c, aer_cxl_rch.c) - AER threaded + handler context. Classifies and enqueues a + struct cxl_proto_err_work_data into the kfifo. +2. **Queue** - the AER-CXL kfifo plus a backing work_struct. +3. **Consumer** (cxl_core/ras.c) - workqueue context. Resolves + the CXL port topology and dispatches to CE/UE handlers. + + +Topologies +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Virtual Hierarchy (VH) +---------------------- + +Standard PCIe topology: Root Port, optional switch (Upstream Port with +one or more Downstream Ports), and Endpoints. Each component raises +Internal Errors directly via the Root Port's AER interrupt. + +Producer: cxl_forward_error() in aer_cxl_vh.c. + +Restricted CXL Host (RCH) +-------------------------- + +A Root Complex Event Collector (RCEC) aggregates errors from RCDs +attached as Root Complex Integrated Endpoints. The AER driver +iterates RCDs beneath the RCEC via pcie_walk_rcec() and forwards +each qualifying device through cxl_forward_error() into the same +kfifo. + +Producer: cxl_forward_error() in aer_cxl_vh.c, called from +cxl_rch_handle_error_iter() via pcie_walk_rcec(). + + +Error flow +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. code-block:: text + + CXL device raises AER Internal Error + (PCI_ERR_COR_INTERNAL or PCI_ERR_UNC_INTN) + | + v + +--------------------------------------+ + | AER core (aer.c) | + | aer_irq() -> aer_isr() | + | -> find_source_device() | + | -> handle_error_source(dev, info) | + +--------------------------------------+ + | + v + +--------------------------------------+ + | handle_error_source() dispatch | + | | + | 1. cxl_rch_handle_error() | + | [always; filters internally] | + | | + | 2. if is_cxl_error(): | + | cxl_forward_error() | + | [enqueue to kfifo] | + | | + | 3. if cxl_pending && non-CE: | + | cxl_proto_err_flush() | + | [sync drain before recovery] | + | | + | 4. pci_aer_handle_error() [always] | + +--------------------------------------+ + | + (kfifo -> workqueue) + | + v + +--------------------------------------+ + | __cxl_proto_err_work_fn() consumer | + | | + | if is_cxl_restricted(pdev): | + | cxl_handle_rdport_errors() | + | [RCH dport RAS first] | + | | + | port =3D find_cxl_port_by_dev( | + | &pdev->dev, NULL) | + | dport =3D cxl_find_dport_by_dev( | + | port, &pdev->dev) | + | [dport NULL for EP/USP; set RP/DSP] | + | | + | cxl_handle_proto_error() | + +--------------------------------------+ + | | + v v + +-----------------+ +--------------------+ + | CE | | UCE | + | cxl_handle_ | | cxl_do_recovery() | + | cor_ras() | | read RAS status | + | trace + clear | | trace + panic | + +-----------------+ +--------------------+ + +cxl_do_recovery() reads the CXL RAS uncorrectable status register. +If UE bits are set, it emits the trace event and panics. If no bits +are set (e.g. RAS mapped but error already cleared), it logs a +diagnostic and defers to AER recovery. + + +Severity policy +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +**CE** - cxl_handle_cor_ras() reads the CXL RAS correctable status +register, clears set bits, and emits a cxl_aer_correctable_error +trace event. No recovery action. + +**UCE (non-fatal, and fatal on Root Port/Downstream Port)** - cxl_do_recov= ery() reads the CXL RAS +uncorrectable status register. If UE bits are set, the kernel panics. +CXL.cachemem traffic cannot be safely recovered once an uncorrectable +error is signaled; continuing risks silent data corruption across +interleaved HDM regions. This panic policy applies to the native AER +path. On firmware-first (CPER/GHES) platforms the CPER handler emits +trace events only and does not call cxl_do_recovery(). + +**Fatal UCE on EP/USP** - The AER core driver does not read AER status +registers for Endpoint and Upstream Ports with fatal events because the +link is down. Without AER status, is_cxl_error() cannot classify +the event as a CXL protocol error and it falls through to standard +AER recovery. + +RCH special case +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +When the consumer sees is_cxl_restricted(pdev), it calls +cxl_handle_rdport_errors() first to process the RCH Downstream +Port's RAS registers (accessed via RCRB, not standard config space). +It then continues to process the RCD Endpoint's own RAS registers +via the common path. Both register blocks are checked because +errors can appear in either independently. + +cxl_handle_rdport_errors() acquires the port lock internally. +Callers must not hold it. + + +Trace events +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Two trace events cover all device types and both the native AER and +CPER/GHES firmware-first paths: + +* cxl_aer_correctable_error +* cxl_aer_uncorrectable_error + +Fields: + +* ``memdev`` - memdev name for Endpoints; empty for non-Endpoints. +* ``port`` - CXL port device name. +* ``dport`` - Downstream Port device name; empty when not applicable. +* ``host`` - parent host bridge or uport device name. +* ``serial`` - PCI Device Serial Number from pdev->dsn (cached at + enumeration; no config-space read in the error path). + + +Interrupt masking +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +CXL Internal Error bits (PCI_ERR_UNC_INTN and PCI_ERR_COR_INTERNAL) +are unmasked in the AER capability only after the CXL RAS register +block is successfully mapped. A devm teardown action restores the +mask when the port or dport is removed, ensuring clean state after +driver removal. + + +Source files +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +.. list-table:: + :header-rows: 1 + + * - File + - Role + * - drivers/pci/pcie/aer.c + - AER core; IRQ, dispatch + * - drivers/pci/pcie/aer_cxl_vh.c + - VH producer; kfifo + * - drivers/pci/pcie/aer_cxl_rch.c + - RCH dispatch; RCEC walk + * - drivers/cxl/core/ras.c + - Consumer; CE/UE handlers; CPER + * - drivers/cxl/core/ras_rch.c + - RCH dport RAS handling + * - drivers/acpi/apei/ghes.c + - CPER/GHES kfifo producer --=20 2.34.1