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charset="utf-8" On phy_init() failure the error path fell through to disable_rsts, which deasserted the controller reset and then entered disable_phys calling phy_power_off() on PHYs that were never powered on. That corrupts the PHY power_count and triggers an extra runtime PM put. Use a separate exit_phys path that unwinds with phy_exit() only and falls through to disable_clks while the controller remains in reset. Reserve phy_power_off() for the phy_power_on() failure path only, and skip masked-out ports in both unwind loops. On phy_power_on() failure re-assert the controller reset before disabling clocks and regulators, matching the teardown order used by ahci_platform_enable_resources() and ahci_platform_disable_resources(). Fixes: 26c8404e162b ("ata: ahci_ceva: fix error handling for Xilinx GT PHY = support") Signed-off-by: Radhey Shyam Pandey --- drivers/ata/ahci_ceva.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c index 2d6a08c23d6a..2961e53288f4 100644 --- a/drivers/ata/ahci_ceva.c +++ b/drivers/ata/ahci_ceva.c @@ -211,7 +211,7 @@ static int ceva_ahci_platform_enable_resources(struct a= hci_host_priv *hpriv) =20 rc =3D phy_init(hpriv->phys[i]); if (rc) - goto disable_rsts; + goto exit_phys; } =20 /* De-assert the controller reset */ @@ -230,14 +230,24 @@ static int ceva_ahci_platform_enable_resources(struct= ahci_host_priv *hpriv) =20 return 0; =20 -disable_rsts: - ahci_platform_deassert_rsts(hpriv); - disable_phys: while (--i >=3D 0) { + if (ahci_ignore_port(hpriv, i)) + continue; + phy_power_off(hpriv->phys[i]); phy_exit(hpriv->phys[i]); } + ahci_platform_assert_rsts(hpriv); + goto disable_clks; + +exit_phys: + while (--i >=3D 0) { + if (ahci_ignore_port(hpriv, i)) + continue; + + phy_exit(hpriv->phys[i]); + } =20 disable_clks: ahci_platform_disable_clks(hpriv); base-commit: 1a1757b76427f6201bfe0bf1bea9f7574f332a93 --=20 2.43.0