From nobody Sat Jul 25 04:53:43 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4FFDE369225 for ; Fri, 17 Jul 2026 15:46:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784303219; cv=none; b=WY0IHIslVQP4ZEi/9aX7Odak1hT4lAhcA/yZqm8KmLHujn5zbnHwu6koLcyDL/VrvnKi2+V85fZRG2mn2OkZ0ZFscubi+UJlE2qN35wvbQ1yNzhDmpMHYlzT/bDc7nTduvCIz451ix0bMPp/vgFFDG35T+iAAO27J1k1uwqa3zA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784303219; c=relaxed/simple; bh=HAFauFP41CYCUuSK0DC7SycE+4WHF4gz507BMTfJC5o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=oSCgXIOyNqtNSchxWS3TOIFWvVuBaLiOB8Zn5qcxBbaFV+Q+XEdn2SX28I0RFaJY/KapwDcVZTVXEr+McUXhVgPKC0r4sOkCAQwQzFpkxWWVfmgyEB8G1d+va0U+hFLxPcXLcoMb+pxEPSaNrGdz6jjV6OyZZ00b7rSYWuomFH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=debian.org; spf=pass smtp.mailfrom=gmail.com; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=debian.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-845c92bc464so4420054b3a.2 for ; Fri, 17 Jul 2026 08:46:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784303217; x=1784908017; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=hj/nAMls8Idqw9YqxnSe6WRiiMInWfXR/jNJRmfXPBk=; b=EkDzyJb+zNu8TSbVpHW3NPg+TSEgd8b+jG78RE+Y3fYr0j8jvZTbnXuFVjg61EQj15 Wlz4V598enYt/l+7bnBrGBgW5A5rzQzV1KSvOUslLbtLZMAnJYRplE4O/75Rj+t4Nbsi ZTufLklrAEOeSzXAzfUUw0El7yPETizEFqv3qgu4wxCdKt9E4wl19X/1SPpDJfUNNz9L oLOee7UdTp4az8GU2I0WRTehs1znIpACOsrcmyLx0c79IU0NBi+Y2ZkmdhYyJ5F34BQH zmi+4di4GSpwB+/78nQEhF3I1d4qcIapTWyRn8i99gbUzJqUrQCpj/yXk9wi+nxcH3ve igIg== X-Forwarded-Encrypted: i=1; AHgh+Rq2lwEEnOlyHJld8RJfmR69ie/OXKNm+Js8Ak3eNtWazc9MGdQs0H2Yn7tu+jfa9x+jfRuTmhxvGzDFq6Q=@vger.kernel.org X-Gm-Message-State: AOJu0YwMeo2xBLwprk0AT4vMsqJM5wzik+uvKdZ0GhQnAcEdNFCa+P+E jxqBd7rJsIbR1E5QmrbDmTY8fzlsIvCgLx7/3bUNs0CoLhbKtldxBfA= X-Gm-Gg: AfdE7cnwCC0TJcUCehJmpEq50VVrmNZYKl2V+h1NUVVECX+d4UDB+MKxL/SCAnG0phm rxrSbMSzW1IM/eVHgFllvJarbVrgSqAHTq0bRpFwYaaliiTHLzqMaCnY4Ic/k6HAaMNPJqBWW8N 7gClX3XGoPbAQyR2ZRWLsohlgj2/R/jA5Qz6lrJVbKGeWeAfYmDFs+1s1uUfrgyd5M/caCPmw8L 9lJDuxYc4jVuA9dTtoanx55TKPrFmFYSBj159mYRHbrrhQaAJf/tyUKCSOqEJ+ouYpFj8Ice8ym H7LlUKgAsr1SOTchIJQrwXzrVnKgXxG5k4zCdpdOYALaxLxgXAX37U51IoVWOMftCwZjTs5hxIb WGhx99aWfskJ4JcqzwZnaAMYRxcDRnbd1hrKQwZulhNYBjtAFbVpZfu+4iZArgZed/0Ry5rPqr4 Vkt4WlIanW/i4NdoLcJcwt/nXr7+JRv3ttiLhe0JmAGcjylidfDpRnBfS5lGgTGJxJoYwkwT05Z UdRPRiK5T/8fVs= X-Received: by 2002:a05:6a00:10cd:b0:845:dfef:75b8 with SMTP id d2e1a72fcca58-84c29263072mr3350708b3a.15.1784303217344; Fri, 17 Jul 2026 08:46:57 -0700 (PDT) Received: from penguin.tail0a1999.ts.net (61-228-46-68.dynamic-ip.hinet.net. [61.228.46.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2ad87f83sm1332576b3a.3.2026.07.17.08.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 08:46:56 -0700 (PDT) From: Shih-Yuan Lee To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Shih-Yuan Lee Subject: [PATCH v3 1/2] spi: pxa2xx: disable DMA and fix runtime PM for Apple MacBook8,1 Date: Fri, 17 Jul 2026 23:46:45 +0800 Message-Id: <20260717154646.5854-2-fourdollars@debian.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260717154646.5854-1-fourdollars@debian.org> References: <20260712162420.7453-1-fourdollars@debian.org> <20260717154646.5854-1-fourdollars@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at 00:15.4 has two related problems: 1. The DMA handshake and interrupt routing frequently fail or time out, causing the keyboard and trackpad (driven by the applespi driver via SPI) to become unresponsive. Force PIO mode to avoid this. 2. When DMA is disabled, runtime PM autosuspend clock-gates the LPSS block between transfers. Accessing its MMIO registers while clock-gated triggers a PCIe Completion Timeout which causes a watchdog reset. Move the force-PIO DMI quirk to spi-pxa2xx-pci.c (the LPSS host controller driver) to avoid layering violations in the client driver. To prevent the PCIe Completion Timeout crash when operating in PIO mode: - Only enable runtime autosuspend in pxa2xx_spi_pci_probe() if enable_dma is true. - If DMA is disabled (either statically via the DMI quirk / module parameter or dynamically due to channel exhaustion), call pm_runtime_get_noresume() in pxa2xx_spi_probe() to hold a runtime PM reference, and release it via pm_runtime_put_noidle() in the remove/error paths. This keeps the PM cou= nt above 0 and permanently locks the device out of autosuspend, preventing userspace tools (like PowerTOP) or udev rules from overriding it. - In the shared interrupt handler ssp_int(), check device status using pm_runtime_get_if_active() instead of pm_runtime_suspended(). If the device is suspending (RPM_SUSPENDING) or suspended, ssp_int() immediately returns IRQ_NONE to avoid reading unclocked MMIO registers. - In pxa2xx_spi_runtime_suspend(), call synchronize_irq() to wait for any active handlers on the shared interrupt line to finish before disabling the clock. - Adjust the driver teardown order in pxa2xx_spi_remove() and probe error p= aths: always call free_irq() to unregister the handler before calling clk_disable_unprepare() to turn off the clock, preventing concurrent interrupts from reading registers while the clock is disabled. Avoid duplicate can-DMA pci_info() logging by checking the pre-computed enable_dma status in probe and passing a verbose flag to can_dma(). Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D108331 Signed-off-by: Shih-Yuan Lee --- drivers/spi/spi-pxa2xx-pci.c | 47 ++++++++++++++++++++++++++++---- drivers/spi/spi-pxa2xx.c | 53 +++++++++++++++++++++++++----------- 2 files changed, 78 insertions(+), 22 deletions(-) diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index cae77ac18520..c107b3b53d33 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c @@ -18,9 +18,14 @@ =20 #include #include +#include =20 #include "spi-pxa2xx.h" =20 +static bool spi_pxa2xx_force_pio; +module_param_named(force_pio, spi_pxa2xx_force_pio, bool, 0444); +MODULE_PARM_DESC(force_pio, "Force PIO mode (disables DMA) for SPI transfe= rs. ([0] =3D disabled, 1 =3D enabled)"); + #define PCI_DEVICE_ID_INTEL_QUARK_X1000 0x0935 #define PCI_DEVICE_ID_INTEL_BYT 0x0f0e #define PCI_DEVICE_ID_INTEL_MRFLD 0x1194 @@ -93,6 +98,34 @@ static void lpss_dma_put_device(void *dma_dev) pci_dev_put(dma_dev); } =20 +static const struct dmi_system_id pxa2xx_spi_pci_dmi_table[] =3D { + { + .ident =3D "Apple MacBook8,1", + .matches =3D { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBook8,1"), + }, + }, + { } +}; + +static bool pxa2xx_spi_pci_can_dma(struct pci_dev *dev, bool verbose) +{ + if (spi_pxa2xx_force_pio) { + if (verbose) + pci_info(dev, "Forcing PIO mode (disabling DMA)\n"); + return false; + } + + if (dmi_check_system(pxa2xx_spi_pci_dmi_table)) { + if (verbose) + pci_info(dev, "MacBook8,1 detected: disabling DMA to force PIO mode\n"); + return false; + } + + return true; +} + static int lpss_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controlle= r *c) { struct ssp_device *ssp =3D &c->ssp; @@ -166,7 +199,7 @@ static int lpss_spi_setup(struct pci_dev *dev, struct p= xa2xx_spi_controller *c) =20 c->dma_filter =3D lpss_dma_filter; c->dma_burst_size =3D 1; - c->enable_dma =3D 1; + c->enable_dma =3D pxa2xx_spi_pci_can_dma(dev, true); return 0; } =20 @@ -238,7 +271,7 @@ static int mrfld_spi_setup(struct pci_dev *dev, struct = pxa2xx_spi_controller *c) =20 c->dma_filter =3D lpss_dma_filter; c->dma_burst_size =3D 8; - c->enable_dma =3D 1; + c->enable_dma =3D pxa2xx_spi_pci_can_dma(dev, true); return 0; } =20 @@ -300,10 +333,12 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev, if (ret) return ret; =20 - pm_runtime_set_autosuspend_delay(&dev->dev, 50); - pm_runtime_use_autosuspend(&dev->dev); - pm_runtime_put_autosuspend(&dev->dev); - pm_runtime_allow(&dev->dev); + if (pdata->enable_dma) { + pm_runtime_set_autosuspend_delay(&dev->dev, 50); + pm_runtime_use_autosuspend(&dev->dev); + pm_runtime_put_autosuspend(&dev->dev); + pm_runtime_allow(&dev->dev); + } =20 return 0; } diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 6291d7c2e06f..22020c43fbe4 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -719,14 +719,11 @@ static irqreturn_t ssp_int(int irq, void *dev_id) u32 sccr1_reg; u32 mask =3D drv_data->mask_sr; u32 status; + int active; + irqreturn_t ret =3D IRQ_NONE; =20 - /* - * The IRQ might be shared with other peripherals so we must first - * check that are we RPM suspended or not. If we are we assume that - * the IRQ was not for us (we shouldn't be RPM suspended when the - * interrupt is enabled). - */ - if (pm_runtime_suspended(drv_data->ssp->dev)) + active =3D pm_runtime_get_if_active(drv_data->ssp->dev); + if (active =3D=3D 0) return IRQ_NONE; =20 /* @@ -737,7 +734,7 @@ static irqreturn_t ssp_int(int irq, void *dev_id) */ status =3D pxa2xx_spi_read(drv_data, SSSR); if (status =3D=3D ~0) - return IRQ_NONE; + goto out_put; =20 sccr1_reg =3D pxa2xx_spi_read(drv_data, SSCR1); =20 @@ -750,7 +747,7 @@ static irqreturn_t ssp_int(int irq, void *dev_id) mask &=3D ~SSSR_TINT; =20 if (!(status & mask)) - return IRQ_NONE; + goto out_put; =20 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); @@ -758,10 +755,19 @@ static irqreturn_t ssp_int(int irq, void *dev_id) if (!drv_data->controller->cur_msg) { handle_bad_msg(drv_data); /* Never fail */ - return IRQ_HANDLED; + ret =3D IRQ_HANDLED; + goto out_put; } =20 - return drv_data->transfer_handler(drv_data); + ret =3D drv_data->transfer_handler(drv_data); + +out_put: + if (active > 0) { + pm_runtime_mark_last_busy(drv_data->ssp->dev); + pm_runtime_put_autosuspend(drv_data->ssp->dev); + } + + return ret; } =20 /* @@ -1351,6 +1357,9 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_d= evice *ssp, } } =20 + if (!platform_info->enable_dma) + pm_runtime_get_noresume(dev); + /* Enable SOC clock */ status =3D clk_prepare_enable(ssp->clk); if (status) @@ -1449,11 +1458,18 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp= _device *ssp, return status; =20 out_error_clock_enabled: + free_irq(ssp->irq, drv_data); clk_disable_unprepare(ssp->clk); + pxa2xx_spi_dma_release(drv_data); + goto out_error_pm_forbid; =20 out_error_dma_irq_alloc: - pxa2xx_spi_dma_release(drv_data); free_irq(ssp->irq, drv_data); + pxa2xx_spi_dma_release(drv_data); + +out_error_pm_forbid: + if (!platform_info->enable_dma) + pm_runtime_put_noidle(dev); =20 return status; } @@ -1466,16 +1482,20 @@ void pxa2xx_spi_remove(struct device *dev) =20 spi_unregister_controller(drv_data->controller); =20 + /* Release IRQ first so handler won't access registers after clock is dis= abled */ + free_irq(ssp->irq, drv_data); + /* Disable the SSP at the peripheral and SOC level */ pxa_ssp_disable(ssp); clk_disable_unprepare(ssp->clk); =20 /* Release DMA */ - if (drv_data->controller_info->enable_dma) + if (drv_data->controller_info->enable_dma) { pxa2xx_spi_dma_release(drv_data); - - /* Release IRQ */ - free_irq(ssp->irq, drv_data); + pm_runtime_forbid(dev); + } else { + pm_runtime_put_noidle(dev); + } } EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx"); =20 @@ -1518,6 +1538,7 @@ static int pxa2xx_spi_runtime_suspend(struct device *= dev) { struct driver_data *drv_data =3D dev_get_drvdata(dev); =20 + synchronize_irq(drv_data->ssp->irq); clk_disable_unprepare(drv_data->ssp->clk); return 0; } --=20 2.39.5 From nobody Sat Jul 25 04:53:43 2026 Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA96636A34E for ; Fri, 17 Jul 2026 15:46:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784303222; cv=none; b=MLw3ayLspWMvikN9ytNlz5uq7X+ShKUHFMabH9h4x2fQZrIoknyPAgtbDRddK7F+akMy8BfYrqund9zYqvdc2ET+E4WPkmt+mj0XvsNal0N3fwn+pDNWefhek8xRIGLHQK+W0uQlYWtKZlRhQJ7V+dRlAZD6TGW9Ev4iIgNurEE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784303222; c=relaxed/simple; bh=/30ILNi97e371ZCUfDdkkvyywAaA/bsZTpX6mXbpwm8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=L3J6uaj0Y1Y5lR3TfJoKH2kkn0MXqXj5E0DCm077Hv61SJaMq8IxdDTFmTqmwIFpbHOjAIslJaElX5zccKzI6wFmzLPJYbfevSzHhAInTLJEIQbaduU+DjE/ovVCnBueOJpmAGUbjnLnkYTGUeiO2ZWrTqwaJBGFA9lEhLOepiM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=debian.org; spf=pass smtp.mailfrom=gmail.com; arc=none smtp.client-ip=209.85.210.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=fail (p=none dis=none) header.from=debian.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-pf1-f174.google.com with SMTP id d2e1a72fcca58-8453427d3f4so7355676b3a.3 for ; Fri, 17 Jul 2026 08:46:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784303219; x=1784908019; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=8C+dIg+iRIUuwRCedX9SwbyPIfJoMEmzzskW79kAUPY=; b=Vfv9CZ8YGn2AqJZ52yhy/0GZJWfPTAnyq7uW3k4jDeJshNghjzIbW2WnMXGn9gcChO SBXDqIDealLh9BU9V+XAD0th5RBg8PJ4u76NzjpsBxMXwYs4Kh/R5BBz7WCtOVL/mMqi eMg9MrAXt5ByqWWmpthh8SBX73tb78GcZNT/zCC8NWGJKNYTpIPw5h0DQ06R5sYsP91D 3cS8RRJ/CkrAo4+ug2wjsqqan6wkE8OMppagaVebn8CJ0ldezBWOrHbPi4kEFhR/3pMr Rvin2WSAde3njPfqJvx2V/pbk2nsWtf5phxMkLKw4zSt7b7Vlu/KdrkviUTpA7IY5DuV X1Nw== X-Forwarded-Encrypted: i=1; AHgh+RpxX3KWj6xmyaIaLtcXwfO+V6PHjeMgfAXEYHzMXzEdN4bVZmtjvNE4wDGfO5LVHQUBhgo54/RgpS1bKEU=@vger.kernel.org X-Gm-Message-State: AOJu0YwNgn2pfDIwuYFYIM/IqPKrTkGTOhuxfR2EItgom977kXa+b450 H/Tj2EEPFNmZOXBmXrjrtAhq2qJoVGFHeL7wrk0UURH1/DPaOkq/rzQPE7xbjUU= X-Gm-Gg: AfdE7cnja6p6jznmBk3z6KaljCy7yh05ju092RKzJDMVoQPvi69NulYoIszN+q4TdPd mZlFlJ8wNvv3nrdgonNrSz3e0gQAXfuKkoYpArfBVXGmlAsA189Gelzl/PrXQedQxYhahDiaBfK XiVzISj1UBKPWIhODZ6XCvgPx4OlpyZ4cBwyvsgjMlo3ntJZS02H55eh6DrY00noVF/V9I/qtII zntsEAzmXye2Dk+ykd9C5qMvvNRtYbx88E7s5UlgCFVYYGn66pcc/vsRJ/nbzUj8PUCG42jAEcZ t0a1B55VlsvdHQyYV2y+Leh3n0PHevr9IasWQ1mX1m1+1z1TfzAPPMG/ieUlQ6aMUjyd8gtmAVX JF/kJlvVMJP8Q3A69dck7Ic/pL3SlxqWfV8mqEaFK6kKxeWSL4vfyJWiwMNrTGQ7dmkU1C/mEAj LTbxK7xCfW8EPyy2tM9L81JEr7RuCNkNtdwcwZQSpsmVsDAjpLlAHgJ+NFRkDcXQoVuhOLWutl6 9rxOgJij6BC2D0= X-Received: by 2002:a05:6a00:4208:b0:845:c906:5ff5 with SMTP id d2e1a72fcca58-84c292d5262mr3363923b3a.30.1784303218932; Fri, 17 Jul 2026 08:46:58 -0700 (PDT) Received: from penguin.tail0a1999.ts.net (61-228-46-68.dynamic-ip.hinet.net. [61.228.46.68]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2ad87f83sm1332576b3a.3.2026.07.17.08.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 08:46:58 -0700 (PDT) From: Shih-Yuan Lee To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Shih-Yuan Lee Subject: [PATCH v3 2/2] spi: pxa2xx: restore LPSS private register state on S3 resume Date: Fri, 17 Jul 2026 23:46:46 +0800 Message-Id: <20260717154646.5854-3-fourdollars@debian.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260717154646.5854-1-fourdollars@debian.org> References: <20260712162420.7453-1-fourdollars@debian.org> <20260717154646.5854-1-fourdollars@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel LPSS SPI controllers lose all private register state across S3 suspend because the LPSS power domain is fully removed. On resume the driver only re-enables the SSP clock, leaving the LPSS private registers in their power-on-reset state, which causes two problems: 1. LPSS_PRIV_RESETS (offset 0x04 within the LPSS private space) stays zero, keeping the functional block in reset. Any MMIO access while the block is held in reset causes a PCIe Completion Timeout and a watchdog-triggered system reset. LPSS_PRIV_RESETS_FUNC and LPSS_PRIV_RESETS_IDMA must be de-asserted before any other register access on resume. 2. The LPSS software chip-select control register must not be blindly restored from its suspend-time snapshot: if CS was asserted at the moment of suspend, restoring that state corrupts the first post-resume SPI transaction. Instead, call lpss_ssp_setup() which unconditionally writes SW_MODE | CS_HIGH (idle/deasserted), matching the state established at probe time. To resolve these issues safely: - Wrap S3 suspend/resume with pm_runtime_resume_and_get() and pm_runtime_put_autosuspend() respectively. This ensures that if the device was runtime-suspended, it is temporarily resumed to active state prior to suspend. This guarantees that the clock and power domain are active during MMIO register access, and that the private registers are consistently saved and restored across S3 sleep cycles. - On S3 suspend success path, return 0 directly without dropping the PM reference. This preserves the acquired PM reference across suspend. On S3 resume, release it via pm_runtime_put_autosuspend(), and ensure all error paths in resume (clock enable failure or spi_controller_resume failure) jump to out_put to correctly release the reference, preventing reference count underflow and leaks. - Save only the first 6 LPSS private registers (offsets 0x00 to 0x14) via drv_data->lpss_base during suspend. Offsets beyond 0x14 (except CS control at 0x18, which is re-initialised by lpss_ssp_setup()) are reserved/unimplemented on LPT platforms (such as MacBook8,1), and writing to them triggers a PCIe Completion Timeout causing a system freeze. - Store the saved context in drv_data->lpss_priv_ctx[6] (inside struct driver_data) which is private to the core driver. This avoids changing the layout of struct pxa2xx_spi_controller, preventing ABI symbol version mismatches with uncompiled platform drivers (e.g., spi-pxa2xx-platform.ko). On resume, de-assert resets first, restore all other saved registers, then call lpss_ssp_setup() to re-initialise CS. Signed-off-by: Shih-Yuan Lee --- drivers/spi/spi-pxa2xx.c | 87 +++++++++++++++++++++++++++++++++++----- drivers/spi/spi-pxa2xx.h | 1 + 2 files changed, 79 insertions(+), 9 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 22020c43fbe4..94d41cbb3d71 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -72,7 +72,12 @@ struct chip_data { #define LPSS_CAPS_CS_EN_SHIFT 9 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) =20 -#define LPSS_PRIV_CLOCK_GATE 0x38 +/* Offsets from drv_data->lpss_base */ +#define LPSS_PRIV_RESETS 0x04 +#define LPSS_PRIV_RESETS_IDMA BIT(2) +#define LPSS_PRIV_RESETS_FUNC 0x3 + +#define LPSS_PRIV_CLOCK_GATE 0x38 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK 0x3 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON 0x3 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF 0x0 @@ -1505,16 +1510,39 @@ static int pxa2xx_spi_suspend(struct device *dev) struct ssp_device *ssp =3D drv_data->ssp; int status; =20 + status =3D pm_runtime_resume_and_get(dev); + if (status < 0) + return status; + status =3D spi_controller_suspend(drv_data->controller); if (status) - return status; + goto out_put; =20 pxa_ssp_disable(ssp); =20 - if (!pm_runtime_suspended(dev)) - clk_disable_unprepare(ssp->clk); + if (is_lpss_ssp(drv_data)) { + unsigned int i; =20 + /* + * Save the first 6 LPSS private registers (offsets 0x00 to 0x14) + * while the clock is still enabled. They are lost when the LPSS + * power domain is removed across S3 and must be restored on resume. + * Use drv_data->lpss_base so the correct per-platform offset + * is applied regardless of LPSS IP revision. + * Registers beyond 0x14 (except CS control at 0x18) are reserved + * or unimplemented on LPT, and accessing them triggers a PCIe + * Completion Timeout causing a system halt. + */ + for (i =3D 0; i < 6; i++) + drv_data->lpss_priv_ctx[i] =3D readl(drv_data->lpss_base + i * 4); + } + + clk_disable_unprepare(ssp->clk); return 0; + +out_put: + pm_runtime_put_noidle(dev); + return status; } =20 static int pxa2xx_spi_resume(struct device *dev) @@ -1524,14 +1552,55 @@ static int pxa2xx_spi_resume(struct device *dev) int status; =20 /* Enable the SSP clock */ - if (!pm_runtime_suspended(dev)) { - status =3D clk_prepare_enable(ssp->clk); - if (status) - return status; + status =3D clk_prepare_enable(ssp->clk); + if (status) + goto out_put; + + if (is_lpss_ssp(drv_data)) { + unsigned int i; + + /* + * The LPSS power domain is removed across S3, taking + * all private registers with it. De-assert the + * functional block and IDMA resets first; any MMIO + * access while the block is held in reset causes a + * PCIe Completion Timeout and a watchdog-triggered + * system reset. + */ + writel(LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA, + drv_data->lpss_base + LPSS_PRIV_RESETS); + + /* Restore the other 5 saved private registers */ + for (i =3D 0; i < 6; i++) { + if (i =3D=3D LPSS_PRIV_RESETS / 4) + continue; + writel(drv_data->lpss_priv_ctx[i], + drv_data->lpss_base + i * 4); + } + + /* + * Re-initialise the SW chip-select control register so + * CS starts deasserted (SW_MODE | CS_HIGH), regardless + * of the state it was in at suspend time. A stale + * asserted CS on the first post-resume transaction + * corrupts the write-status response from the device. + */ + lpss_ssp_setup(drv_data); } =20 /* Start the queue running */ - return spi_controller_resume(drv_data->controller); + status =3D spi_controller_resume(drv_data->controller); + if (status) { + clk_disable_unprepare(ssp->clk); + goto out_put; + } + +out_put: + /* Let runtime PM autosuspend again if needed */ + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + return status; } =20 static int pxa2xx_spi_runtime_suspend(struct device *dev) diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index 447be0369384..fce776e2404c 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -71,6 +71,7 @@ struct driver_data { irqreturn_t (*transfer_handler)(struct driver_data *drv_data); =20 void __iomem *lpss_base; + u32 lpss_priv_ctx[6]; =20 /* Optional slave FIFO ready signal */ struct gpio_desc *gpiod_ready; --=20 2.39.5