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bh=gA+LgbDDmWtKcLIZGrCT2OufglfLr6cc3fRTD6cDRVQ=; b=eiGP9vZkQ/Zf+r72xzXfnBvZR0 Ue5EWPbdbJ52mOIoxIeiHFlM2UCYm+1j4xmbidFNqeu/xLZnI02i3kRf7R6/HD+GJSytjURvozPfy Tzbq7R1RUT3SDthXXTYK2uVF5R3CcDUJ0togWkoF+ZdcV1+sAuG5MzfNWFHum1RncjPurB2lXR1KJ GvJRmZd1AmWpWp//vTJEDFTC5Mc+5fcSEqNNM4QlxSv9xiRa7oNMd5+1mLlaaPQx3iNlP/3e7DGry jGYVFPVeNw2dM5062u0cxU5EhkPemtLhEvZBz2KuvSBCc3lLmGbzsVMR0VP668bZzZ8nJ+N4i2CGF Q35XdC3Q==; Received: from [193.77.36.193] (port=54788 helo=rok-trip.kanardia.eu) by th8.neoserv.si with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.4) (envelope-from ) id 1wkhH0-00000001fP1-1pwy; Fri, 17 Jul 2026 14:02:34 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH 1/4] drm/rockchip: lvds: propagate bus_flags to the CRTC state Date: Fri, 17 Jul 2026 14:00:02 +0200 Message-ID: <20260717120005.2087386-2-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717120005.2087386-1-rok@kanardia.eu> References: <20260717120005.2087386-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wkhH0-00000001fP1-1pwy X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" rockchip_lvds_encoder_atomic_check() sets output_mode and output_type but never copies the connector's bus_flags into the Rockchip CRTC state, unlike dw_dp-rockchip.c and dw-mipi-dsi2-rockchip.c which both do. panel-lvds parses pixelclk-active from the DT display timing and publishes it on the connector as DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE. VOP2 reads that flag back out of the CRTC state to decide POLFLAG_DCLK_INV. With the flag dropped here, vcstate->bus_flags is always zero, so a panel that asks to be clocked on the falling edge is driven on the rising one, and there is no way to express the panel's requirement from DT at all. No functional change for the SoCs currently supported by this driver: rk3288 and px30 pair with the VOP1 driver (rockchip_drm_vop.c), which never reads bus_flags - only VOP2 consumes it. The flag becomes live with the RK3568 support added later in this series. Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 Reviewed-by: Chaoyi Chen --- drivers/gpu/drm/rockchip/rockchip_lvds.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/roc= kchip/rockchip_lvds.c index 75f898a..95fa0a9 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -129,7 +129,15 @@ rockchip_lvds_encoder_atomic_check(struct drm_encoder = *encoder, struct drm_connector_state *conn_state) { struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); - + struct drm_connector *connector =3D conn_state->connector; + + /* + * The VOP derives the pixel clock polarity from this. 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Fri, 17 Jul 2026 14:02:51 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH 2/4] dt-bindings: display: rockchip,lvds: add RK3568 Date: Fri, 17 Jul 2026 14:00:03 +0200 Message-ID: <20260717120005.2087386-3-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717120005.2087386-1-rok@kanardia.eu> References: <20260717120005.2087386-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wkhHH-00000001fP1-2qlb X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" The RK3568 LVDS transmitter has no register block of its own: it is programmed entirely through the GRF and re-uses the MIPI DSI0 D-PHY (rockchip,rk3568-dsi-dphy) in LVDS mode. It therefore needs phys/phy-names like px30, but unlike px30 it does take a pclk (PCLK_DSITX_0, shared with the DSI controller the D-PHY belongs to). It has no analog supplies of its own and no pinctrl: the lanes are dedicated D-PHY pins, not muxable GPIOs. Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- .../display/rockchip/rockchip,lvds.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,lv= ds.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.= yaml index 03b002a..6280f7e 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml @@ -15,6 +15,7 @@ properties: enum: - rockchip,px30-lvds - rockchip,rk3288-lvds + - rockchip,rk3568-lvds =20 reg: maxItems: 1 @@ -121,6 +122,27 @@ allOf: - avdd1v8-supply - avdd3v3-supply =20 + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-lvds + + then: + properties: + reg: false + avdd1v0-supply: false + avdd1v8-supply: false + avdd3v3-supply: false + pinctrl-names: false + pinctrl-0: false + + required: + - clocks + - clock-names + - phys + - phy-names + additionalProperties: false =20 examples: --=20 2.43.0 From nobody Sat Jul 25 05:18:30 2026 Received: from th8-a.mail-neoserv.si (th8-a.mail-neoserv.si [152.89.234.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76C621EB5FD; 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Received: from [193.77.36.193] (port=54788 helo=rok-trip.kanardia.eu) by th8.neoserv.si with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.4) (envelope-from ) id 1wkhHJ-00000001fP1-23GD; Fri, 17 Jul 2026 14:02:53 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH 3/4] drm/rockchip: lvds: add RK3568 support Date: Fri, 17 Jul 2026 14:00:04 +0200 Message-ID: <20260717120005.2087386-4-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717120005.2087386-1-rok@kanardia.eu> References: <20260717120005.2087386-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wkhHJ-00000001fP1-23GD X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" The RK3568 LVDS transmitter has no register block of its own. It is driven entirely through the GRF and re-uses the MIPI DSI0 D-PHY in PHY_MODE_LVDS, which phy-rockchip-inno-dsidphy already supports. Based on Alibek Omarov's earlier posting [1], with the changes below. Power the D-PHY from the encoder enable path rather than from probe. phy_power_on() runs the phy driver's whole LVDS bring-up: PLL and bandgap power-on, a settle, PLL mode select, then a reset pulse of the serializer and the lane enables. None of that is safe at probe time - the GRF has not yet switched the block to LVDS mode (LVDS0_MODE_EN is set from rk3568_lvds_poweron(), i.e. the enable path) and the VOP is not driving dclk. The serializer is clocked from dclk and latches its state coming out of that reset, so it comes up dead and stays dead. The failure is silent: every register in the phy, the GRF and the VOP reads back exactly as on a working system while the lanes sit at common mode and never toggle. Program RK3568_LVDS0_DCLK_INV_SEL from the CRTC state's bus_flags so the panel's declared pixelclk-active is honoured on the LVDS block as well as on the VOP pin polarity. Both have to agree with the edge the panel samples on. Re-assert RK3568_LVDS0_P2S_EN in rk3568_lvds_poweron(). rk3568_lvds_poweroff() clears MODE_EN and P2S_EN together, so setting P2S_EN once at probe would leave the parallel-to-serial converter off after the first disable/enable cycle. Use regmap_write() rather than regmap_update_bits() for the GRF. These registers are write-masked - the upper 16 bits select which of the lower 16 a write may change - so there is nothing to preserve and no reason to read first. Passing a FIELD_PREP_WM16() value as both the mask and the value of an update_bits() applies the masking twice and only works by accident. Between the two, nothing needs programming at probe at all: the GRF is written entirely from the enable path, so px30_lvds_probe() is left alone rather than being refactored into a shared phy helper. [1] https://lore.kernel.org/all/20230119184807.171132-1-a1ba.omarov@gmail.c= om/ Co-developed-by: Alibek Omarov Signed-off-by: Alibek Omarov Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- drivers/gpu/drm/rockchip/rockchip_lvds.c | 161 +++++++++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_lvds.h | 10 ++ 2 files changed, 171 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/roc= kchip/rockchip_lvds.c index 95fa0a9..f45d04a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -435,6 +435,133 @@ static void px30_lvds_encoder_disable(struct drm_enco= der *encoder) drm_panel_unprepare(lvds->panel); } =20 +static int rk3568_lvds_poweron(struct rockchip_lvds *lvds) +{ + int ret; + + ret =3D clk_enable(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return ret; + } + + ret =3D pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); + return ret; + } + + /* + * Enable LVDS mode and the parallel-to-serial converter. These are + * write-masked registers, so a plain write only touches the bits named + * here; there is nothing to preserve and no need to read first. + */ + return regmap_write(lvds->grf, RK3568_GRF_VO_CON2, + RK3568_LVDS0_MODE_EN(1) | + RK3568_LVDS0_P2S_EN(1)); +} + +static void rk3568_lvds_poweroff(struct rockchip_lvds *lvds) +{ + regmap_write(lvds->grf, RK3568_GRF_VO_CON2, + RK3568_LVDS0_MODE_EN(0) | RK3568_LVDS0_P2S_EN(0)); + + pm_runtime_put(lvds->dev); + clk_disable(lvds->pclk); +} + +static int rk3568_lvds_grf_config(struct drm_encoder *encoder, + struct drm_display_mode *mode) +{ + struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + struct rockchip_crtc_state *s =3D + to_rockchip_crtc_state(encoder->crtc->state); + bool negedge =3D !!(s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE); + + if (lvds->output !=3D DISPLAY_OUTPUT_LVDS) { + DRM_DEV_ERROR(lvds->dev, "Unsupported display output %d\n", + lvds->output); + return -EINVAL; + } + + /* + * The LVDS block has its own dclk inversion select, separate from the + * VOP's pin polarity. Both have to agree with what the panel samples on. + */ + regmap_write(lvds->grf, RK3568_GRF_VO_CON2, + RK3568_LVDS0_DCLK_INV_SEL(negedge)); + + /* Set format */ + return regmap_write(lvds->grf, RK3568_GRF_VO_CON0, + RK3568_LVDS0_SELECT(lvds->format) | + RK3568_LVDS0_MSBSEL(1)); +} + +static void rk3568_lvds_encoder_enable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + struct drm_display_mode *mode =3D &encoder->crtc->state->adjusted_mode; + int ret; + + drm_panel_prepare(lvds->panel); + + ret =3D rk3568_lvds_poweron(lvds); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to power on LVDS: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + ret =3D rk3568_lvds_grf_config(encoder, mode); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to configure LVDS: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + /* + * Only now bring the D-PHY up. phy_power_on() runs the whole + * inno_dsidphy_lvds_mode_enable() sequence - PLL and bandgap power-on, + * a settle, PLL mode select, then a reset pulse of the serializer and + * the lane enables. All of that has to happen with the block already + * switched to LVDS mode in the GRF (above) and with the VOP's dclk + * running, because the serializer is clocked from dclk and latches its + * state out of that reset. + * + * Doing it at probe instead - as this driver used to - resets and + * enables the serializer against a block that is not in LVDS mode yet + * and has no input clock. Every register then reads back correct while + * the lanes sit at common mode forever. Rockchip's BSP orders it this + * way (GRF writes, then phy_set_mode + phy_power_on). + */ + ret =3D phy_set_mode(lvds->dphy, PHY_MODE_LVDS); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to set phy mode: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + ret =3D phy_power_on(lvds->dphy); + if (ret) { + DRM_DEV_ERROR(lvds->dev, "failed to power on phy: %d\n", ret); + drm_panel_unprepare(lvds->panel); + return; + } + + drm_panel_enable(lvds->panel); +} + +static void rk3568_lvds_encoder_disable(struct drm_encoder *encoder) +{ + struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + + drm_panel_disable(lvds->panel); + phy_power_off(lvds->dphy); + rk3568_lvds_poweroff(lvds); + drm_panel_unprepare(lvds->panel); +} + static const struct drm_encoder_helper_funcs rk3288_lvds_encoder_helper_funcs =3D { .enable =3D rk3288_lvds_encoder_enable, @@ -449,6 +576,13 @@ struct drm_encoder_helper_funcs px30_lvds_encoder_help= er_funcs =3D { .atomic_check =3D rockchip_lvds_encoder_atomic_check, }; =20 +static const +struct drm_encoder_helper_funcs rk3568_lvds_encoder_helper_funcs =3D { + .enable =3D rk3568_lvds_encoder_enable, + .disable =3D rk3568_lvds_encoder_disable, + .atomic_check =3D rockchip_lvds_encoder_atomic_check, +}; + static int rk3288_lvds_probe(struct platform_device *pdev, struct rockchip_lvds *lvds) { @@ -512,6 +646,22 @@ static int px30_lvds_probe(struct platform_device *pde= v, return phy_power_on(lvds->dphy); } =20 +static int rk3568_lvds_probe(struct platform_device *pdev, + struct rockchip_lvds *lvds) +{ + /* + * Grab and init the phy, but do NOT power it on here - that is done in + * rk3568_lvds_encoder_enable() once the GRF is in LVDS mode and dclk is + * running. See the comment there. The GRF is not touched at probe + * either: every bit of it is programmed from the enable path. + */ + lvds->dphy =3D devm_phy_get(&pdev->dev, "dphy"); + if (IS_ERR(lvds->dphy)) + return PTR_ERR(lvds->dphy); + + return phy_init(lvds->dphy); +} + static const struct rockchip_lvds_soc_data rk3288_lvds_data =3D { .probe =3D rk3288_lvds_probe, .helper_funcs =3D &rk3288_lvds_encoder_helper_funcs, @@ -522,6 +672,11 @@ static const struct rockchip_lvds_soc_data px30_lvds_d= ata =3D { .helper_funcs =3D &px30_lvds_encoder_helper_funcs, }; =20 +static const struct rockchip_lvds_soc_data rk3568_lvds_data =3D { + .probe =3D rk3568_lvds_probe, + .helper_funcs =3D &rk3568_lvds_encoder_helper_funcs, +}; + static const struct of_device_id rockchip_lvds_dt_ids[] =3D { { .compatible =3D "rockchip,rk3288-lvds", @@ -531,6 +686,10 @@ static const struct of_device_id rockchip_lvds_dt_ids[= ] =3D { .compatible =3D "rockchip,px30-lvds", .data =3D &px30_lvds_data }, + { + .compatible =3D "rockchip,rk3568-lvds", + .data =3D &rk3568_lvds_data + }, {} }; MODULE_DEVICE_TABLE(of, rockchip_lvds_dt_ids); @@ -601,6 +760,8 @@ static int rockchip_lvds_bind(struct device *dev, struc= t device *master, encoder =3D &lvds->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm_dev, dev->of_node); + rockchip_drm_encoder_set_crtc_endpoint_id(&lvds->encoder, + dev->of_node, 0, 0); =20 ret =3D drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_LVDS); if (ret < 0) { diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/roc= kchip/rockchip_lvds.h index 2d92447..93d3415 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.h +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h @@ -121,4 +121,14 @@ #define PX30_LVDS_P2S_EN(val) FIELD_PREP_WM16(BIT(6), (val)) #define PX30_LVDS_VOP_SEL(val) FIELD_PREP_WM16(BIT(1), (val)) =20 +#define RK3568_GRF_VO_CON0 0x0360 +#define RK3568_LVDS0_SELECT(val) FIELD_PREP_WM16(GENMASK(5, 4), (val)) +#define RK3568_LVDS0_MSBSEL(val) FIELD_PREP_WM16(BIT(3), (val)) + +#define RK3568_GRF_VO_CON2 0x0368 +#define RK3568_LVDS0_DCLK_INV_SEL(val) FIELD_PREP_WM16(BIT(9), (val)) +#define RK3568_LVDS0_DCLK_DIV2_SEL(val) FIELD_PREP_WM16(BIT(8), (val)) +#define RK3568_LVDS0_MODE_EN(val) FIELD_PREP_WM16(BIT(1), (val)) +#define RK3568_LVDS0_P2S_EN(val) FIELD_PREP_WM16(BIT(0), (val)) + #endif /* _ROCKCHIP_LVDS_ */ --=20 2.43.0 From nobody Sat Jul 25 05:18:30 2026 Received: from th8-a.mail-neoserv.si (th8-a.mail-neoserv.si [152.89.234.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A4D93F824A; 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Received: from [193.77.36.193] (port=54788 helo=rok-trip.kanardia.eu) by th8.neoserv.si with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.99.4) (envelope-from ) id 1wkhHh-00000001fP1-22Ww; Fri, 17 Jul 2026 14:03:17 +0200 From: Rok Markovic To: Heiko Stuebner , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alibek Omarov , Rok Markovic Subject: [PATCH 4/4] arm64: dts: rockchip: rk356x: add LVDS node Date: Fri, 17 Jul 2026 14:00:05 +0200 Message-ID: <20260717120005.2087386-5-rok@kanardia.eu> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717120005.2087386-1-rok@kanardia.eu> References: <20260717120005.2087386-1-rok@kanardia.eu> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Authentication-Results: th8.neoserv.si; auth=pass (PLAIN) smtp.auth=rok@kanardia.eu X-NEOSERV-MailScanner-Information: Please contact the ISP for more information X-NEOSERV-MailScanner-ID: 1wkhHh-00000001fP1-22Ww X-NEOSERV-MailScanner: Found to be clean X-NEOSERV-MailScanner-SpamCheck: not spam, SpamAssassin (not cached, score=1.31, required 7, ALL_TRUSTED -1.00, BAYES_50 0.80, KAM_DMARC_QUARANTINE 1.50, KAM_DMARC_STATUS 0.01) X-NEOSERV-MailScanner-SpamScore: s X-NEOSERV-MailScanner-From: rok@kanardia.eu X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - th8.neoserv.si X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - kanardia.eu X-Get-Message-Sender-Via: th8.neoserv.si: authenticated_id: rok@kanardia.eu X-Authenticated-Sender: th8.neoserv.si: rok@kanardia.eu Content-Type: text/plain; charset="utf-8" Add the LVDS transmitter node. It has no register block of its own - it is programmed through the GRF and borrows the MIPI DSI0 D-PHY - so it carries no reg, only the DSITX_0 pclk, the phy and the VO power domain. Disabled by default; boards that route LVDS enable it along with dsi_dphy0 and wire lvds_in to a VOP2 video port. Signed-off-by: Rok Markovic Assisted-by: Claude:claude-opus-4-8 --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 64bdd8b..9244b55 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -878,6 +878,31 @@ }; }; =20 + lvds: lvds { + compatible =3D "rockchip,rk3568-lvds"; + clocks =3D <&cru PCLK_DSITX_0>; + clock-names =3D "pclk_lvds"; + phys =3D <&dsi_dphy0>; + phy-names =3D "dphy"; + power-domains =3D <&power RK3568_PD_VO>; + rockchip,grf =3D <&grf>; + rockchip,output =3D "lvds"; + status =3D "disabled"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + lvds_in: port@0 { + reg =3D <0>; + }; + + lvds_out: port@1 { + reg =3D <1>; + }; + }; + }; + qos_gpu: qos@fe128000 { compatible =3D "rockchip,rk3568-qos", "syscon"; reg =3D <0x0 0xfe128000 0x0 0x20>; --=20 2.43.0