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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH v5 1/4] dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA direction Date: Fri, 17 Jul 2026 14:38:21 +0530 Message-ID: <20260717090824.2364230-2-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717090824.2364230-1-srinivas.neeli@amd.com> References: <20260717090824.2364230-1-srinivas.neeli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|CY5PR12MB6083:EE_ X-MS-Office365-Filtering-Correlation-Id: 53e9e063-6407-40f2-7ba4-08dee3e301b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|376014|36860700016|7416014|10067099003|56012099006|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: LBId/1qYii6pq40tVMMunvKbpEEYhNvQncTGCznU/BYNG3Hrcx0BjLO9lZ9s6p3mOcerrGO+82RAskN7ZiScxcwEdTc19mEddy8tbMxHMJ/lc9QChkeIXtiuZ1HbC0UK/+nRAq3AGbgKu+xoSsKF9vNFeC4OaUBITPewKO97bSrGWV8d0Fr66k/F1KVs5c4k+TuQkPZsX1s6be6zEu+xC8LiYfhPMBRYAZHtdkEsADVCOYCprCsAtHBZzWblcHyRODKHcApRSs+Qg9q2RAjRcjSjRv0v90tELhlbHbzXhIGTPW2hK3LFj7Eok9f0gB+LFjP9GqMgkUFUlfrIHj8EoDKxs0D7PPngwWP5LJ7X8U7X7eZVcCbt+0uKdg0ENc0eMthZ4lHOAuh2E4ad1rJ976Q1NUzcZLtvk8cIKSXU1LlzwEVpnE8IzTN4qV1l7DlNPZIFMqsuSSWYE17PfPWwkElG+E4r7/oF7Pke/cMZGFuUK7p2ubw2AVee5MU7W19Jyt+6nrH1CkAhUtw2KJp0h0oSQ7rP9ae0NCHagDyncEQU7ZuSLCoDndzMAy/EB2aiZctfIHwOeKT+IEPlp1luTHegoEJTtPRnR6R1KvfwBHqTvf9BT41abdfepY4Iy7NrgrMzqmlhoCilPikJMn8nswJ883E9OiUTiKsPczZ5cktxyfDhvFGrWkhtzFAmK+LotCM5FeK419PyUf2ACQZHDw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(23010399003)(376014)(36860700016)(7416014)(10067099003)(56012099006)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MHEZHm0jLwF923Tsa883v9cuvYNu60eibnMTTziQ8xbvNUBjjOIVT4ipEsbXQG6ljB12yIsjg+tXfZqLGBUV4LoOzyVj8dnpwkmiCRUIcL8P5fn52iOlbQcDoM1AIeC0U0ecNtdWBUzg23r+cr3sKvPPZf3djcPJQh1PKknjB4YGjiC8CZMIYC+qoPlW2GfiDfQoY1BqkJMmLs4Rq5G0E0e/KzESpdhKp23Ctxc9OYE0toor0NWiBJ5i0yLqyqfLAROE/i+5Fz4H9fF92S+ZVdheAqH+vT7a+/F2PVNQpYRSJ7RRNmm+B4AV0f1WpJcUHw42jD0F4Hv+HbNDQ0uw2zCmzwSyq5FRa04uOwUSIoXZRME9W3Jb5iO0Oam/QuAaDrBHyhe0GOyYqW1MADEir/Rnqn+WyU7+B2dMhku+ee29/u5gb0fhCgXJdzUkPcze X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 09:08:45.8041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53e9e063-6407-40f2-7ba4-08dee3e301b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6083 Content-Type: text/plain; charset="utf-8" The MCDMA BD format differs between memory-to-device (MM2S) and device-to-memory (S2MM) directions, but the driver was using generic 'status' and 'sideband_status' fields for both. This led to incorrect residue calculations when the hardware updates direction-specific fields. Refactor the descriptor structure to use unions with direction-specific field mappings, and update the residue calculation logic to select the correct status field based on DMA direction. This matches the hardware descriptor layout and fixes incorrect residue reporting. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine dr= iver support") Reviewed-by: Radhey Shyam Pandey Signed-off-by: Srinivas Neeli --- Changes in V5: - No change. Changes in V4: - Added Reviewed-by: Radhey Shyam Pandey. Changes in V3: - Renamed subject from "for MM2S vs S2MM" to "based on DMA direction". - Reworded commit message for clarity. - Added XILINX_MCDMA_BD_HW_SIZE macro and static_assert to verify descriptor size at compile time. - Refactored residue calculation to separate addition and subtraction operations for better readability. Changes in V2: - No change. --- drivers/dma/xilinx/xilinx_dma.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 98b41b8f8915..ff5b29a808e9 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -223,6 +223,7 @@ #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) #define XILINX_MCDMA_BD_EOP BIT(30) #define XILINX_MCDMA_BD_SOP BIT(31) +#define XILINX_MCDMA_BD_HW_SIZE 64 =20 /** * struct xilinx_vdma_desc_hw - Hardware Descriptor @@ -277,8 +278,10 @@ struct xilinx_axidma_desc_hw { * @buf_addr_msb: MSB of Buffer address @0x0C * @rsvd: Reserved field @0x10 * @control: Control Information field @0x14 - * @status: Status field @0x18 - * @sideband_status: Status of sideband signals @0x1C + * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18 + * @s2mm_status: Status field for s2mm @0x18 + * @mm2s_status: Status field for mm2s @0x1C + * @s2mm_sideband_status: Sideband status for s2mm @0x1C * @app: APP Fields @0x20 - 0x30 */ struct xilinx_aximcdma_desc_hw { @@ -288,10 +291,17 @@ struct xilinx_aximcdma_desc_hw { u32 buf_addr_msb; u32 rsvd; u32 control; - u32 status; - u32 sideband_status; + union { + u32 mm2s_ctrl_sideband; + u32 s2mm_status; + }; + union { + u32 mm2s_status; + u32 s2mm_sideband_status; + }; u32 app[XILINX_DMA_NUM_APP_WORDS]; } __aligned(64); +static_assert(sizeof(struct xilinx_aximcdma_desc_hw) =3D=3D XILINX_MCDMA_B= D_HW_SIZE); =20 /** * struct xilinx_cdma_desc_hw - Hardware Descriptor @@ -1015,9 +1025,11 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_= chan *chan, struct xilinx_aximcdma_tx_segment, node); aximcdma_hw =3D &aximcdma_seg->hw; - residue +=3D - (aximcdma_hw->control & chan->xdev->max_buffer_len) - - (aximcdma_hw->status & chan->xdev->max_buffer_len); + residue +=3D aximcdma_hw->control & chan->xdev->max_buffer_len; + if (chan->direction =3D=3D DMA_DEV_TO_MEM) + residue -=3D aximcdma_hw->s2mm_status & chan->xdev->max_buffer_len; + else + residue -=3D aximcdma_hw->mm2s_status & chan->xdev->max_buffer_len; } } =20 --=20 2.43.0 From nobody Sat Jul 25 05:27:34 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013070.outbound.protection.outlook.com [40.93.201.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B79F439184B; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH v5 2/4] dmaengine: xilinx_dma: Move descriptors to done list based on completion bit Date: Fri, 17 Jul 2026 14:38:22 +0530 Message-ID: <20260717090824.2364230-3-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717090824.2364230-1-srinivas.neeli@amd.com> References: <20260717090824.2364230-1-srinivas.neeli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|BL1PR12MB5755:EE_ X-MS-Office365-Filtering-Correlation-Id: 49a001f5-571c-4c0e-8fa6-08dee3e30324 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|23010399003|7416014|376014|82310400026|10067099003|5023799004|11063799006|6133799003|56012099006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: 6/NJZT/5WpLgL5B7YLGvQ+DUCZX6HRZ+si6TB0KuSdUtzMCzWEmuSLZ7QAc2YC16674ZPcZfZNPNsAXBI7wS+JPXvJIa5E51xFXTOoKcVcM+bXj1kIjPEYRSD3Br59FAuqtORB8IbdnH7MPaRzKd6q2ze57isTEVWH8Q5pIqKM9KotPZ45hbWmD7BMFDmYmC6pkns2bqg3VYGiexV5xqElbiCl7zbqeUVGnvzoxu1GK/WsaW2rMpe5PdujplnsqOmGS+q9KcBZWdcXtmfmFuqLswgR/nVKPRP8ofm7QC/o2nZxci9GnSKA+mmJ44gc31Xghw44cNSCZ4m7UQOtbT/xEyB6FTCk9A5NX/yhd+UuFr/EW4Nw3eOKyjSiZQ6V1S4uISNYd1cXi8Xovx2GPFDafcMrdZg4jQQMbNzF4CyXCZ/OwGnZSy8rO34FfJxEIsM7/1kohL5N6nMjUL+fGeZBkTA6o8wElrbwSGxyhB74HVbKkUzWRfmLLyWFkQniA4Kl52lrYHAjqH3uOnrqq3UiYbQuAARqLOYFuOEROBbEJ4/IFrv3HVLofu06cwak7NA96XxjuWc1EbbpYqVbL4WKKGvyS7L4PiCJEe+i0vHw43sT9lOc5bYoCUWYF6D1JRF8YkYVcS6UY4dge652uG1dEpALvz7pFx6CMr8nZllCKNnlcJoD0Rq4uz0wG3GXPOiuKcEcn6UzLNBS8BO07b/w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(23010399003)(7416014)(376014)(82310400026)(10067099003)(5023799004)(11063799006)(6133799003)(56012099006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: o9+GtI70uCLUpBJKDhRZZbOFOhg/fXtdkBYIg3OHin47zG1OI0+V1+IR970MRV5a8pOPGKD9Qmkl0w6+YBtCs9PGCUx4Y1R0gFJldoqGHWnUIXh8QdaRffUt8dQCSO8C31dLT+cHhn89heK0VMaajpRB+Ta4yhCG4w1DVg6VeKD/kPdb6uDEf9zhztKuKq+Xz4P37C4SqrzlgdtMQnuehPSXzaRnVfk0GlIa2J6C/zZX+w4dD5GWuQjaeieSwMQ1RT1CnT3ujH0ytf8Svc9rUncArxC8oY5TFHwqyfeJ7K1h9qmLFtXxfO+EEwGvk9hHfic0ILzPJz2vbuAvpp6j7QZLpUnGnnCqP9692FGYukPXzFxeBeUetqO/0niFXNu8NTJ7dfapYKK7QpXkQ0XzDw8SGzR283SA7VwsVBjA/dGks03OXLoHK+ShuyrGjoqw X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 09:08:48.2368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49a001f5-571c-4c0e-8fa6-08dee3e30324 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5755 Content-Type: text/plain; charset="utf-8" In AXI MCDMA, xilinx_dma_complete_descriptor() walks the channel's active_list and unconditionally moves every entry to the done_list. The MCDMA IOC interrupt handler invokes this function on every interrupt-on-completion, but with interrupt coalescing (IRQThreshold > 1) an IOC interrupt may fire after only a subset of the queued descriptors have actually been processed by the hardware. As a result, descriptors whose completion bit is not yet set in the BD status were being reported as completed to client drivers. Add a check for the descriptor completion bit before moving entries from the active list to the done list, using the appropriate direction- specific status field (s2mm_status for DMA_DEV_TO_MEM, mm2s_status for DMA_MEM_TO_DEV). This mirrors the AXIDMA fix in commit 7bcdaa658102 ("dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit"). Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine dr= iver support") Reviewed-by: Radhey Shyam Pandey Signed-off-by: Srinivas Neeli --- Changes in V5: - No change. Changes in V4: - Reworded commit message to reference the AXIDMA fix it mirrors (commit 7bcdaa658102). - Added Reviewed-by: Radhey Shyam Pandey. Changes in V3: - Added Fixes tag. - Expanded commit message to explain the interrupt coalescing scenario and why the has_sg guard is omitted for MCDMA. - Changed local variable from 'bool completed' to 'u32 status' for cleaner status field access. - Simplified completion check logic. Changes in V2: - No change. --- drivers/dma/xilinx/xilinx_dma.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index ff5b29a808e9..1b5b00f08c5f 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -1784,6 +1784,17 @@ static void xilinx_dma_complete_descriptor(struct xi= linx_dma_chan *chan) struct xilinx_axidma_tx_segment, node); if (!(seg->hw.status & XILINX_DMA_BD_COMP_MASK) && chan->has_sg) break; + } else if (chan->xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; + u32 status; + + seg =3D list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, + node); + status =3D (chan->direction =3D=3D DMA_DEV_TO_MEM) ? + seg->hw.s2mm_status : seg->hw.mm2s_status; + if (!(status & XILINX_DMA_BD_COMP_MASK)) + break; } if (chan->has_sg && chan->xdev->dma_config->dmatype !=3D XDMA_TYPE_VDMA) --=20 2.43.0 From nobody Sat Jul 25 05:27:34 2026 Received: from CY3PR05CU001.outbound.protection.outlook.com (mail-westcentralusazon11013053.outbound.protection.outlook.com [40.93.201.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A61AB391E7F; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH v5 3/4] net: xilinx: axienet: Derive RX frame length from residue in dmaengine path Date: Fri, 17 Jul 2026 14:38:23 +0530 Message-ID: <20260717090824.2364230-4-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717090824.2364230-1-srinivas.neeli@amd.com> References: <20260717090824.2364230-1-srinivas.neeli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD0:EE_|PH8PR12MB7327:EE_ X-MS-Office365-Filtering-Correlation-Id: 7924a67b-38db-4a9f-12d4-08dee3e30472 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|7416014|376014|23010399003|6133799003|3023799007|18002099003|22082099003|11063799006|10067099003|56012099006; X-Microsoft-Antispam-Message-Info: ovfFIKaDQZVcJPUBskrEPSHHs3DNuoIs1HGOpwvQn+tZdZHrJUP9rQ0In3I37HpuZ7Le8xAd7DkYXxK0PeDGevj09DHa/GfnioJA0ZAFwZMy4qI5BMN5NqECCVKTlxruwKnbNbM46wkRl9asMVnzSI917jPnq8oqgNoyT1yqFcGafXsMVbhR4Lr4s4ZYGxiI9kpSlJ4SGv865zfXrCdWl6xmo1yG18YgNKpxh9zEl3eq2Of8DUP7nwCCNb9zBT639mx0gKoWlsEOMUEVt/jOXrDstqF+KK7ye+VJOVGCVpvONWbv01y52icr4HCUz38B4nAOv3yv8d7YhFG0l6f28bfjw6/cH7IUVb5lUUC3FrExFjE34cdcF5TwRA6Jf9oYzrh8DxSM7MrjbQavhiRf62M8971W1YxP5OEqgMMsfUkPN72yxy+TqqEmDIrQx3OoyU6OdPFp7g5bdUiTFT2AaTStX8rJR6lPA5IoEBpOGAXKuumPBfHwhJtTOPVyAuPratHU9hHZuolOWxTNX3R+L/oaAiBdAmvPkx1DBXB1ov+vHxA6TfjY1DnrhuAC/vxvYXE8+hHSd+9p0clwU7TsoCHSNDHUFWiKZFv4TlphganLOj5kYXt7ybmLOdgsl5DBy9pxIUZCIXentn7cGCRslgomADAQERamgwVyim/BT6j7bIe3nRXe6nHI68pUw1MXqD/rEARpCVtGHc4IcnNz8A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(36860700016)(1800799024)(7416014)(376014)(23010399003)(6133799003)(3023799007)(18002099003)(22082099003)(11063799006)(10067099003)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YsMmBIZCmxGIGIb3M1DjbShOL0hVNtUVs3OLthosXMwQ4mCliomoUaYQbY+XYKTiUeVUN46NIvcdo9BCqpLRy71bAXPXsVb//zszx1Siu5nvYYuCUNuT7mC7XuaY1T55pq/ES1Kzdi1iaJlg6cBcBeaOGAgIK4O1D/782y5/pTo40rNY3li2HChXtAa/gDxcwcx07WT2MgXKP6eFQ6IGyuxrP0sx9G2CZYlOL1mbOq/kcgBIIYKz+DsYA2KJCdArOGhVvScF0mjo6UNImX3DHfRUwHododPjSTnRMAYtZFdAcFA0Gi0uXAHPJfTu+YzZsyuQ87Z3Vm1iseHoXP93e9l8JGni3x8auQVrIF3llyKCnZKU+9gGq/vJULrLIbMrFe/L+fXgQK64MOinXH6KpJfT59o0B0GQvnYsTlnpuo0akqr3qJAFOcPeI53bSa7X X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 09:08:50.4215 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7924a67b-38db-4a9f-12d4-08dee3e30472 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7327 Content-Type: text/plain; charset="utf-8" The dmaengine RX path derived the received frame length from the descriptor APP metadata. That only works when the optional AXI4-Stream status/control interface is present, because the hardware populates the APP fields solely when that interface is enabled. On designs without it the length read back is invalid. The AXI DMA engine already reports how many bytes it wrote into the buffer through the standard dmaengine residue mechanism. Compute the RX frame length as the posted buffer length minus result->residue, which is independent of the status/control interface and correct across all designs, including multi-descriptor frames where the residue is summed over the chain. Drop the descriptor metadata lookup, which was only used for this purpose. Detect a failed transfer from dmaengine_result.result instead of the metadata pointer return value, and remove the now unused LEN_APP macro. The transmit path is unaffected. It still passes APP metadata for checksum offload and derives its length from the skb. Signed-off-by: Srinivas Neeli Reviewed-by: Radhey Shyam Pandey --- Changes in V5: - No change. Changes in V4: - Renamed subject to "Derive RX frame length from residue in dmaengine path". - Condensed the commit message. - Dropped the Fixes tag. Changes in V3: - New patch in this series. - This patch enables axienet to work on designs where the AXI4-Stream status/control interface is not present. By using the standard dmaengine residue mechanism, the driver no longer depends on APP fields being populated by hardware. - This approach replaces the V2 xferred_bytes mechanism (V2 patch 5/5), making the dt-bindings patch (V2 patch 4/5) for xlnx,include-stscntrl-st= rm also unnecessary. Both V2 patches are dropped in this series. --- drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/ne= t/ethernet/xilinx/xilinx_axienet_main.c index fcf517069d16..67d1b8e91d68 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -53,7 +53,6 @@ #define TX_BD_NUM_MAX 4096 #define RX_BD_NUM_MAX 4096 #define DMA_NUM_APP_WORDS 5 -#define LEN_APP 4 #define RX_BUF_NUM_DEFAULT 128 =20 /* Must be shorter than length of ethtool_drvinfo.driver field to fit */ @@ -1159,29 +1158,26 @@ axienet_start_xmit(struct sk_buff *skb, struct net_= device *ndev) static void axienet_dma_rx_cb(void *data, const struct dmaengine_result *r= esult) { struct skbuf_dma_descriptor *skbuf_dma; - size_t meta_len, meta_max_len, rx_len; struct axienet_local *lp =3D data; struct sk_buff *skb; - u32 *app_metadata; + size_t rx_len; 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Fri, 17 Jul 2026 04:08:49 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Fri, 17 Jul 2026 04:08:45 -0500 From: Srinivas Neeli To: Vinod Koul , Radhey Shyam Pandey CC: Frank Li , Michal Simek , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH v5 4/4] dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA Date: Fri, 17 Jul 2026 14:38:24 +0530 Message-ID: <20260717090824.2364230-5-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717090824.2364230-1-srinivas.neeli@amd.com> References: <20260717090824.2364230-1-srinivas.neeli@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD1:EE_|CH3PR12MB8933:EE_ X-MS-Office365-Filtering-Correlation-Id: b0396e30-165d-4ec0-f856-08dee3e3067c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|23010399003|36860700016|1800799024|10067099003|18002099003|22082099003|6133799003|56012099006|11063799006; X-Microsoft-Antispam-Message-Info: mHpVHfB35mY5jLNbziS4EYK8nT9wCQYwCGrBI+Suj9dyfqWk9+Qpt6NjiZRAWiuY296pvLEYWH3DwTkq1fFetQYykFsWVDa2iKiNyBfL7jEnzFksl8Sohn1LYJK1P2FVn1jYn9IVJT9SPKktmnw+a3UzhK3B3OVu5hmpWk2OMLH0i1fleLt13nrN+2cAaJax1S1KbttTAUrXATJjOIJ1DKZrgPbLrmAJHj3OOzVVB50bJdH0CnENAhgXA27eUZ5owd1qEitlHF956XYxAjJZlJXngOztBdkOkHMoWAabOpGuXmqp3Jqm69H2B1Y9NmkMDFMXa1DU7MWDy9x5PRy9ZnE72kCze/j9NcQTxz5UQxwaJGh+T5KTqY4eK1G2LKlk1HhzIFm4ieeNJmGx16aL7hcd7Vu8TLEbNZjHSDbeUYuqH/JPlVRHkhUxFDNpYXOpj1G8gNLznEuc3DsaB144zgqFT712Nj9OawzINzApA5h9DyRYINCiwLhdgWRVoi4dw9hYYrVbvLwSWB6+SxfMrhisy62GnQyil5RaFi6FLFVQZ4pJF8O5uM12Dr45ASKxqCX5cE7daLf8cVQPYrfAUoyy6tKIdLS0TwcYlvMTWL8+g0MUNh74mER0WAPd0kr4SuFc80RB/ypuKDp+1CldwzTYOwSgsmqsVCZj9pLOBaL5hHBqbL2CNGrxvJ+QV+fgzo5oiwW+uRfdb2VqBeCE7Q== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(23010399003)(36860700016)(1800799024)(10067099003)(18002099003)(22082099003)(6133799003)(56012099006)(11063799006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GWmgsgiU3qbPQbDVO+jlVEnYkrowiOR9UIIG6TKwfip2bqkiOAbwXDwPTSuR41KJlNjyn9cdKHQ3ajzNufFWrONMILEqfSvArbPubpetwNRhAJ96KOm5f9I27t8w/OtzYqP3gjHX5HK51qgemIobwL4++cQyTAy3Efw/W9eBw2QOZffJlx+w7n91XNenBLKDSx6wtKXpXRBgaXztTKuM5x0bCURv9Glw7aQp3cHDU6/Kz7MopUftKpkDogE2hBnnOCFNyo2nZKMk7WMhIk/pVDToS1NTfCxp1IvxoyjzZU4vUTAChC/g40JzoFQM9PKR9L06Hp2DefPEm8nP5hXKnc5wfGDz0G0aQrwzAL/Jlm6VJ2C5M+YR42rShn2ZB2z8StOhSAM0CbBZVKCm0UTcWlAb27swoCEEeZJzYGPEzGujwZ3a4KyykTzuk9W4YCiE X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 09:08:53.8242 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b0396e30-165d-4ec0-f856-08dee3e3067c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD1.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8933 Content-Type: text/plain; charset="utf-8" From: Suraj Gupta xilinx_dma_get_metadata_ptr() returns the AXI DMA APP words from the SOP descriptor in both directions. This is wrong for RX, where the hardware writes the APP words into the EOF descriptor. It also leaves AXI MCDMA without metadata support. Return the metadata from the SOP descriptor for TX and from the EOF descriptor for RX, matching where the hardware reads and writes the fields. For AXI DMA, expose the APP words (20 bytes). For AXI MCDMA, expose the control sideband, status, and APP fields (28 bytes). On TX the control sideband holds TID and TUSER configuration for the outgoing stream. On RX the sideband status holds the received TID, TDEST and TUSER from the incoming stream. The field layout differs between MM2S and S2MM, and the wider payload lets a consumer distinguish the two controllers. No in-tree consumer is affected. Read xlnx,axistream-connected for AXI MCDMA. Attach metadata_ops in xilinx_mcdma_prep_slave_sg() when an AXI4-Stream interface is present, so MCDMA clients use the metadata API the same way as AXI DMA clients. Signed-off-by: Suraj Gupta Co-developed-by: Srinivas Neeli Signed-off-by: Srinivas Neeli --- Changes in V5: - Take the metadata pointer from the SOP descriptor for TX and the EOF descriptor for RX, matching where the hardware reads and writes the fields (TX previously used the EOF descriptor). - AXI DMA now exposes only the APP words (20 bytes) in both directions, instead of the status word followed by APP (24 bytes). - AXI MCDMA exposes the control sideband, status and APP fields (28 bytes), with the sideband position differing between MM2S and S2MM. - Reworked the kernel-doc index table and commit message accordingly. Changes in V4: - Restructured xilinx_dma_get_metadata_ptr(): AXIDMA is now the fall-through path instead of a separate branch guarded by WARN_ON_ONCE()/ERR_PTR(). - Rewrote the kernel-doc as an index table covering AXI DMA, MCDMA S2MM and MCDMA MM2S, and documented that the pointer and payload length are the same for both MCDMA directions. - Added an inline comment explaining the union aliasing. - Condensed the commit message. Changes in V3: - Renamed subject to include "AXI DMA and MCDMA" (was "AXI MCDMA" only). - Complete rewrite of commit message and implementation. - Metadata pointer now returns status field at index 0 instead of APP fields, exposing status and sideband information to clients. - Changed from list_first_entry to list_last_entry to return the EOF descriptor where hardware writes status and APP fields. - Added explicit handling for both AXIDMA and MCDMA types with proper payload length calculation. - Added WARN_ON_ONCE for unsupported DMA types. - Removed the 'chan' field from struct xilinx_dma_tx_descriptor (was added in V2) as it's no longer needed; channel is obtained from tx->chan instead. - Dropped V2 patches 4/5 (dt-bindings xlnx,include-stscntrl-strm) and 5/5 (xferred_bytes support) as the approach changed to use residue. Changes in V2: - Added support for MCDMA metadata handling alongside AXIDMA. - Added 'chan' field to struct xilinx_dma_tx_descriptor. --- drivers/dma/xilinx/xilinx_dma.c | 48 +++++++++++++++++++++++++++++---- 1 file changed, 43 insertions(+), 5 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dm= a.c index 1b5b00f08c5f..6bf509d33e7c 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -651,17 +651,51 @@ static inline void xilinx_aximcdma_buf(struct xilinx_= dma_chan *chan, * @tx: async transaction descriptor * @payload_len: metadata payload length * @max_len: metadata max length - * Return: The app field pointer. + * + * The metadata lives in the SOP descriptor for TX and the EOF descriptor = for RX. + * Field order depends on dmatype and direction: + * + * AXI DMA: [0..] app + * AXI MCDMA (TX): [0] ctrl_sideband, [1] status, [2..] app + * AXI MCDMA (RX): [0] status, [1] sideband, [2..] app + * + * Return: Pointer to the first metadata word. */ static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor *t= x, size_t *payload_len, size_t *max_len) { struct xilinx_dma_tx_descriptor *desc =3D to_dma_tx_descriptor(tx); + struct xilinx_dma_chan *chan =3D to_xilinx_chan(tx->chan); + + if (chan->xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIMCDMA) { + struct xilinx_aximcdma_tx_segment *seg; + + if (chan->direction =3D=3D DMA_DEV_TO_MEM) { + seg =3D list_last_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, node); + *max_len =3D *payload_len =3D sizeof(seg->hw.s2mm_status) + + sizeof(seg->hw.s2mm_sideband_status) + + sizeof(seg->hw.app); + return &seg->hw.s2mm_status; + } + seg =3D list_first_entry(&desc->segments, + struct xilinx_aximcdma_tx_segment, node); + *max_len =3D *payload_len =3D sizeof(seg->hw.mm2s_ctrl_sideband) + + sizeof(seg->hw.mm2s_status) + + sizeof(seg->hw.app); + return &seg->hw.mm2s_ctrl_sideband; + } + struct xilinx_axidma_tx_segment *seg; =20 - *max_len =3D *payload_len =3D sizeof(u32) * XILINX_DMA_NUM_APP_WORDS; - seg =3D list_first_entry(&desc->segments, - struct xilinx_axidma_tx_segment, node); + if (chan->direction =3D=3D DMA_DEV_TO_MEM) + seg =3D list_last_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + else + seg =3D list_first_entry(&desc->segments, + struct xilinx_axidma_tx_segment, node); + + *max_len =3D *payload_len =3D sizeof(seg->hw.app); return seg->hw.app; } =20 @@ -2639,6 +2673,9 @@ xilinx_mcdma_prep_slave_sg(struct dma_chan *dchan, st= ruct scatterlist *sgl, segment->hw.control |=3D XILINX_MCDMA_BD_EOP; } =20 + if (chan->xdev->has_axistream_connected) + desc->async_tx.metadata_ops =3D &xilinx_dma_metadata_ops; + return &desc->async_tx; =20 error: @@ -3287,7 +3324,8 @@ static int xilinx_dma_probe(struct platform_device *p= dev) =20 dma_set_max_seg_size(xdev->dev, xdev->max_buffer_len); =20 - if (xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIDMA) { + if (xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIDMA || + xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIMCDMA) { xdev->has_axistream_connected =3D of_property_read_bool(node, "xlnx,axistream-connected"); } --=20 2.43.0