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charset="utf-8" Define the BAR-resident metadata format used by endpoint functions that expose an endpoint-integrated DMA controller to the host. A VSEC-based discovery scheme would be a natural fit, and existing dw-edma-pcie providers such as Synopsys EDDA and AMD (Xilinx) MDB/CPM6 already use VSECs for DMA discovery. However, some endpoint controllers cannot provide enough writable configuration-space storage for a complete, controller-defined payload. Keep the extensible metadata in a BAR instead, where the endpoint function controls the layout and size. The format describes the DMA register window, exported channel counts, descriptor windows, optional auxiliary windows, endpoint-local descriptor and auxiliary DMA addresses, and a ready bit that tells the host when the described BAR windows are usable. Channel entries keep the auxiliary window optional so layouts that need a separate data or auxiliary aperture can describe it without a format bump. Signed-off-by: Koichiro Den --- Changes in v5: - No changes. MAINTAINERS | 1 + include/linux/pci-ep-dma.h | 170 +++++++++++++++++++++++++++++++++++++ 2 files changed, 171 insertions(+) create mode 100644 include/linux/pci-ep-dma.h diff --git a/MAINTAINERS b/MAINTAINERS index 3af0fe95a92f..f2f5a42c6115 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20846,6 +20846,7 @@ F: Documentation/PCI/endpoint/* F: Documentation/misc-devices/pci-endpoint-test.rst F: drivers/misc/pci_endpoint_test.c F: drivers/pci/endpoint/ +F: include/linux/pci-ep-dma.h F: tools/testing/selftests/pci_endpoint/ =20 PCI ENHANCED ERROR HANDLING (EEH) FOR POWERPC diff --git a/include/linux/pci-ep-dma.h b/include/linux/pci-ep-dma.h new file mode 100644 index 000000000000..73f72455843c --- /dev/null +++ b/include/linux/pci-ep-dma.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __LINUX_PCI_EP_DMA_H +#define __LINUX_PCI_EP_DMA_H + +#include + +/* + * BAR metadata format used by PCI endpoint functions that expose an + * endpoint-integrated DMA controller to a PCI host. + * + * Offsets are relative to the beginning of the metadata blob. Multi-byte + * fields are little-endian. The blob is normally placed at offset 0 of a + * function BAR selected by the endpoint function and discovered by the ho= st + * driver using device-specific policy. Other data in the same BAR, such a= s a + * standard MSI-X table or PBA, is outside this metadata format. + * + * 31 = 0 + * +-------------------------------------------------------------= --+ + * +0x000 | metadata magic = | + * +-------------------------------------------------------------= --+ + * 31 16 15 8 7 = 0 + * +-------------------------------+---------------+-------------= --+ + * +0x004 | metadata length | reserved | revision = | + * +-------------------------------+---------------+-------------= --+ + * 31 30 29 27 26 19 18 11 10 3 2= 0 + * +--+--+--------+--------------+--------------+--------------+-= --+ + * +0x008 |R |H |reserved| ch entry size| RD count | WR count |B= AR| + * +--+--+--------+--------------+--------------+--------------+-= --+ + * +0x00c | register window offset[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x010 | register window offset[63:32] = | + * +-------------------------------------------------------------= --+ + * 31 16 15 8 7 = 0 + * +-------------------------------+---------------+-------------= --+ + * +0x014 | reserved | layout data | layout = | + * +-------------------------------+---------------+-------------= --+ + * +0x018 | register window size = | + * +-------------------------------------------------------------= --+ + * +0x01c | write table = | + * | ( channel table entries #0 ~ #N ) = | + * +-------------------------------------------------------------= --+ + * | read table = | + * | ( channel table entries #0 ~ #N ) = | + * +-------------------------------------------------------------= --+ + * + * metadata magic: PCI_EP_DMA_METADATA_MAGIC. + * metadata length: byte size of the whole metadata blob. The val= ue + * must fit in PCI_EP_DMA_METADATA_HDR_LEN_FIELD= and + * in the BAR allocation that contains the metad= ata. + * revision: metadata format revision. + * R: ready bit. Set only by the endpoint after all fields and BAR + * windows described by this metadata have been programmed and= can + * be used by the host. The host must not consume the windows + * before observing this bit. + * H: host-request bit. Set only by the host driver after it has = found + * this metadata. The endpoint may use this as the trigger to + * program DMA window BAR subrange mappings, and may clear it = while + * revoking R during teardown or reinitialization. + * ch entry size: byte stride between consecutive channel table + * entries. Revision 1 requires at least + * PCI_EP_DMA_METADATA_CH_ENTRY_SIZE bytes. + * RD count: number of exposed RC-to-endpoint DMA read channels a= nd + * read channel-table entries. + * WR count: number of exposed endpoint-to-RC DMA write channels = and + * write channel-table entries. + * BAR: BAR that contains the DMA controller register window. + * register window offset: BAR-local byte offset of the DMA contr= oller + * register window in BAR. + * register window size: DMA controller register window size in b= ytes. + * layout: DMA controller register layout identifier. + * layout data: layout-specific data. For + * PCI_EP_DMA_METADATA_REG_LAYOUT_DW_EDMA this is the + * DesignWare eDMA/HDMA map format. + * write table: starts at PCI_EP_DMA_METADATA_HDR_LEN if write ch= annel + * count is non-zero. + * read table: starts at PCI_EP_DMA_METADATA_HDR_LEN plus the wri= te + * table size if read channel count is non-zero. + * reserved fields and bits: write zero and ignore on read. + * + * + * Channel table entry: + * + * 31 17 16 15 14 12 11 10 8 7 = 0 + * +--------------------+--+--+-------+--+--------+--------------= --+ + * +0x000 | reserved |A |rs|aux BAR|rs|desc BAR|hardware chann= el| + * +--------------------+--+--+-------+--+--------+--------------= --+ + * +0x004 | descriptor window BAR offset[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x008 | descriptor window BAR offset[63:32] = | + * +-------------------------------------------------------------= --+ + * +0x00c | descriptor window size = | + * +-------------------------------------------------------------= --+ + * +0x010 | descriptor DMA address[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x014 | descriptor DMA address[63:32] = | + * +-------------------------------------------------------------= --+ + * +0x018 | auxiliary window BAR offset[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x01c | auxiliary window BAR offset[63:32] = | + * +-------------------------------------------------------------= --+ + * +0x020 | auxiliary window size = | + * +-------------------------------------------------------------= --+ + * +0x024 | auxiliary DMA address[31:0] = | + * +-------------------------------------------------------------= --+ + * +0x028 | auxiliary DMA address[63:32] = | + * +-------------------------------------------------------------= --+ + * + * A: auxiliary-window-valid bit. If clear, aux BAR and auxiliary + * window fields are ignored. + * aux BAR: BAR that contains the optional auxiliary window. + * desc BAR: BAR that contains the descriptor window. + * hardware channel: DMA controller's hardware channel number. + * Revision 1 entries are currently consumed in= dense + * 0-based order. + * descriptor window BAR offset: BAR-local byte offset of the + * descriptor window in desc BAR. + * descriptor window size: descriptor window size in bytes. + * descriptor DMA address: endpoint-local address used by the DMA + * controller to fetch descriptors. + * auxiliary window BAR offset: BAR-local byte offset of the auxi= liary + * window in aux BAR. + * auxiliary window size: auxiliary window size in bytes. + * auxiliary DMA address: endpoint-local address corresponding to= the + * auxiliary window. + * reserved fields and bits: write zero and ignore on read. + */ +#define PCI_EP_DMA_METADATA_MAGIC 0x4d444550 /* "PEDM" */ +#define PCI_EP_DMA_METADATA_REV 0x1 + +#define PCI_EP_DMA_METADATA_HDR_LEN 0x1c + +#define PCI_EP_DMA_METADATA_HDR 0x04 +#define PCI_EP_DMA_METADATA_HDR_REV GENMASK(7, 0) +#define PCI_EP_DMA_METADATA_HDR_LEN_FIELD GENMASK(31, 16) + +#define PCI_EP_DMA_METADATA_CTRL 0x08 +#define PCI_EP_DMA_METADATA_CTRL_REG_BAR GENMASK(2, 0) +#define PCI_EP_DMA_METADATA_CTRL_WR_CH_COUNT GENMASK(10, 3) +#define PCI_EP_DMA_METADATA_CTRL_RD_CH_COUNT GENMASK(18, 11) +#define PCI_EP_DMA_METADATA_CTRL_CH_ENTRY_SIZE GENMASK(26, 19) +#define PCI_EP_DMA_METADATA_CTRL_HOST_REQ BIT(30) +#define PCI_EP_DMA_METADATA_CTRL_READY BIT(31) + +#define PCI_EP_DMA_METADATA_REG_OFF_LO 0x0c +#define PCI_EP_DMA_METADATA_REG_OFF_HI 0x10 +#define PCI_EP_DMA_METADATA_REG_LAYOUT 0x14 +#define PCI_EP_DMA_METADATA_REG_LAYOUT_ID GENMASK(7, 0) +#define PCI_EP_DMA_METADATA_REG_LAYOUT_DATA GENMASK(15, 8) +#define PCI_EP_DMA_METADATA_REG_SIZE 0x18 + +#define PCI_EP_DMA_METADATA_REG_LAYOUT_DW_EDMA 0x1 + +#define PCI_EP_DMA_METADATA_CH_ENTRY_SIZE 0x2c +#define PCI_EP_DMA_METADATA_CH_CTRL 0x00 +#define PCI_EP_DMA_METADATA_CH_CTRL_HW_CH GENMASK(7, 0) +#define PCI_EP_DMA_METADATA_CH_CTRL_DESC_BAR GENMASK(10, 8) +#define PCI_EP_DMA_METADATA_CH_CTRL_AUX_BAR GENMASK(14, 12) +#define PCI_EP_DMA_METADATA_CH_CTRL_AUX_VALID BIT(16) +#define PCI_EP_DMA_METADATA_CH_DESC_OFF_LO 0x04 +#define PCI_EP_DMA_METADATA_CH_DESC_OFF_HI 0x08 +#define PCI_EP_DMA_METADATA_CH_DESC_SIZE 0x0c +#define PCI_EP_DMA_METADATA_CH_DESC_ADDR_LO 0x10 +#define PCI_EP_DMA_METADATA_CH_DESC_ADDR_HI 0x14 +#define PCI_EP_DMA_METADATA_CH_AUX_OFF_LO 0x18 +#define PCI_EP_DMA_METADATA_CH_AUX_OFF_HI 0x1c +#define PCI_EP_DMA_METADATA_CH_AUX_SIZE 0x20 +#define PCI_EP_DMA_METADATA_CH_AUX_ADDR_LO 0x24 +#define PCI_EP_DMA_METADATA_CH_AUX_ADDR_HI 0x28 + +#endif /* __LINUX_PCI_EP_DMA_H */ --=20 2.51.0 From nobody Sat Jul 25 06:09:21 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11020124.outbound.protection.outlook.com [52.101.229.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 861EC3750C9; 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charset="utf-8" Extend EPC auxiliary resource metadata so endpoint functions can discover controller-owned DMA registers, logical DMA channels, and descriptor memory. The DMA metadata is intentionally generic at the EPC layer. A backend reports the register layout, channel counts, logical channel resources, and descriptor memory resources. Logical channels carry hardware channel numbers and refer to descriptor memory by ID; reserving or delegating those channels is handled by separate EPC operations so resource metadata stays independent of any backend-specific DMA provider. Descriptor memory is identified separately so one memory resource can be shared by multiple channels. For DesignWare controllers, reg_layout_data carries the eDMA/HDMA map format so a consumer can distinguish legacy, unroll, HDMA compatible, and HDMA native register layouts without making the EPC API itself DesignWare-specific. Signed-off-by: Koichiro Den --- Changes in v5: - No changes. include/linux/pci-epc.h | 46 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index f247cf9bcf1a..8c89cb6d6733 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -65,6 +65,9 @@ struct pci_epc_map { * enum pci_epc_aux_resource_type - auxiliary resource type identifiers * @PCI_EPC_AUX_DOORBELL_MMIO: Doorbell MMIO, that might be outside the DMA * controller register window + * @PCI_EPC_AUX_DMA_CTRL_MMIO: DMA controller MMIO register window + * @PCI_EPC_AUX_DMA_CHAN: Logical DMA channel + * @PCI_EPC_AUX_DMA_DESC_MEM: DMA descriptor memory * * EPC backends may expose auxiliary blocks (e.g. DMA engines) by mapping = their * register windows and descriptor memories into BAR space. This enum @@ -72,6 +75,29 @@ struct pci_epc_map { */ enum pci_epc_aux_resource_type { PCI_EPC_AUX_DOORBELL_MMIO, + PCI_EPC_AUX_DMA_CTRL_MMIO, + PCI_EPC_AUX_DMA_CHAN, + PCI_EPC_AUX_DMA_DESC_MEM, +}; + +/** + * enum pci_epc_aux_dma_reg_layout - DMA controller register layout + * @PCI_EPC_AUX_DMA_REG_LAYOUT_UNKNOWN: unknown or uninitialized layout + * @PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA: Synopsys DesignWare eDMA/HDMA layo= ut + */ +enum pci_epc_aux_dma_reg_layout { + PCI_EPC_AUX_DMA_REG_LAYOUT_UNKNOWN =3D 0, + PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA, +}; + +/** + * enum pci_epc_aux_dma_dir - DMA channel direction relative to the endpoi= nt + * @PCI_EPC_AUX_DMA_EP_TO_RC: channel moves data from endpoint to root com= plex + * @PCI_EPC_AUX_DMA_RC_TO_EP: channel moves data from root complex to endp= oint + */ +enum pci_epc_aux_dma_dir { + PCI_EPC_AUX_DMA_EP_TO_RC, + PCI_EPC_AUX_DMA_RC_TO_EP, }; =20 /** @@ -99,6 +125,26 @@ struct pci_epc_aux_resource { int irq; /* IRQ number for the doorbell handler */ u32 data; /* write value to ring the doorbell */ } db_mmio; + + /* PCI_EPC_AUX_DMA_CTRL_MMIO */ + struct { + enum pci_epc_aux_dma_reg_layout reg_layout; + u32 reg_layout_data; + u16 ep_to_rc_ch_cnt; + u16 rc_to_ep_ch_cnt; + } dma_ctrl; + + /* PCI_EPC_AUX_DMA_CHAN */ + struct { + enum pci_epc_aux_dma_dir dir; + u16 hw_ch; + u16 desc_mem_id; + } dma_chan; + + /* PCI_EPC_AUX_DMA_DESC_MEM */ + struct { + u16 id; + } dma_desc; } u; }; =20 --=20 2.51.0 From nobody Sat Jul 25 06:09:21 2026 Received: from TY3P286CU002.outbound.protection.outlook.com (mail-japaneastazon11020124.outbound.protection.outlook.com [52.101.229.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D1A437268B; Fri, 17 Jul 2026 05:06:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.229.124 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784264810; cv=fail; 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charset="utf-8" Some endpoint functions expose an EPC-integrated DMA controller to the host. The endpoint function should not need to know the backend-specific mechanism used to reserve a channel locally and hand its programming interface to the host. Add pci_epc_delegate_dma_chan() and pci_epc_reclaim_dma_chan(). Add matching EPC operations. The public API returns an opaque handle, while the EPC backend keeps any private channel state. This lets generic endpoint functions delegate channels without depending on a specific DMAengine provider. Let reclaim callers tell the backend whether hardware exposed to host programming needs to be quiesced before local ownership is restored. The quiesce may cover a provider-defined sharing group, so callers must hold every delegated member and stop peer programming before reclaim. Bind failure paths that only unwind local reservations can skip quiesce. Reclaim is best-effort because it runs from teardown paths that cannot be aborted. The backend always consumes the delegation and reports any quiesce failure itself. The opaque handle is always freed. Signed-off-by: Koichiro Den --- Changes in v5: - Document provider-defined sharing groups and the best-effort reclaim contract. drivers/pci/endpoint/pci-epc-core.c | 105 ++++++++++++++++++++++++++++ include/linux/pci-epc.h | 16 +++++ 2 files changed, 121 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci= -epc-core.c index 831b40458dcd..344e54677bfa 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -18,6 +18,13 @@ static const struct class pci_epc_class =3D { .name =3D "pci_epc", }; =20 +struct pci_epc_dma_chan { + struct pci_epc *epc; + u8 func_no; + u8 vfunc_no; + void *data; +}; + static void devm_pci_epc_release(struct device *dev, void *res) { struct pci_epc *epc =3D *(struct pci_epc **)res; @@ -236,6 +243,104 @@ int pci_epc_get_aux_resources(struct pci_epc *epc, u8= func_no, u8 vfunc_no, } EXPORT_SYMBOL_GPL(pci_epc_get_aux_resources); =20 +/** + * pci_epc_delegate_dma_chan() - delegate an EPC-owned DMA channel to the = host + * @epc: EPC device + * @func_no: function number + * @vfunc_no: virtual function number + * @dir: DMA channel direction relative to the endpoint + * @hw_ch: hardware channel number + * @chan: output delegated-channel handle + * + * Some EPC backends integrate DMA channels that can be exposed to the hos= t. + * This helper asks the backend to reserve the specified channel locally a= nd + * place it in a state where the host driver may program it through the ex= posed + * register window. + * + * Return: 0 on success, -EOPNOTSUPP if the backend does not support DMA c= hannel + * delegation, or another -errno on failure. + */ +int pci_epc_delegate_dma_chan(struct pci_epc *epc, u8 func_no, u8 vfunc_no, + enum pci_epc_aux_dma_dir dir, u16 hw_ch, + struct pci_epc_dma_chan **chan) +{ + struct pci_epc_dma_chan *epc_chan; + void *data =3D NULL; + int ret; + + if (!pci_epc_function_is_valid(epc, func_no, vfunc_no)) + return -EINVAL; + + if (!chan) + return -EINVAL; + *chan =3D NULL; + + if (dir !=3D PCI_EPC_AUX_DMA_EP_TO_RC && + dir !=3D PCI_EPC_AUX_DMA_RC_TO_EP) + return -EINVAL; + + if (!epc->ops->delegate_dma_chan || !epc->ops->reclaim_dma_chan) + return -EOPNOTSUPP; + + epc_chan =3D kzalloc_obj(*epc_chan, GFP_KERNEL); + if (!epc_chan) + return -ENOMEM; + + mutex_lock(&epc->lock); + ret =3D epc->ops->delegate_dma_chan(epc, func_no, vfunc_no, dir, hw_ch, + &data); + mutex_unlock(&epc->lock); + if (ret) { + kfree(epc_chan); + return ret; + } + + epc_chan->epc =3D epc; + epc_chan->func_no =3D func_no; + epc_chan->vfunc_no =3D vfunc_no; + epc_chan->data =3D data; + *chan =3D epc_chan; + + return 0; +} +EXPORT_SYMBOL_GPL(pci_epc_delegate_dma_chan); + +/** + * pci_epc_reclaim_dma_chan() - reclaim a delegated EPC-owned DMA channel + * @chan: delegated-channel handle returned by pci_epc_delegate_dma_chan() + * @quiesce: quiesce affected hardware before reclaiming the channel + * + * Reclaim a channel previously delegated to the host. Set @quiesce for ch= annels + * that may have been exposed to host programming. Bind failure paths that= are + * unwinding local reservations before exposure may leave it clear. + * + * Some providers share enable and interrupt controls among channels. The + * caller must retain every delegated member of that sharing group and pre= vent + * further peer programming before requesting reclaim. + * + * Reclaim is best-effort because it runs from teardown paths that cannot = be + * aborted. The backend always consumes the delegation and reports any qui= esce + * failure itself. + */ +void pci_epc_reclaim_dma_chan(struct pci_epc_dma_chan *chan, bool quiesce) +{ + struct pci_epc *epc; + + if (!chan) + return; + + epc =3D chan->epc; + if (epc && epc->ops && epc->ops->reclaim_dma_chan) { + mutex_lock(&epc->lock); + epc->ops->reclaim_dma_chan(epc, chan->func_no, chan->vfunc_no, + chan->data, quiesce); + mutex_unlock(&epc->lock); + } + + kfree(chan); +} +EXPORT_SYMBOL_GPL(pci_epc_reclaim_dma_chan); + /** * pci_epc_stop() - stop the PCI link * @epc: the link of the EPC device that has to be stopped diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index 8c89cb6d6733..2d15194a126b 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -11,7 +11,9 @@ =20 #include =20 +struct device; struct pci_epc; +struct pci_epc_dma_chan; =20 enum pci_epc_interface_type { UNKNOWN_INTERFACE =3D -1, @@ -174,6 +176,11 @@ struct pci_epc_aux_resource { * @get_aux_resources_count: ops to get the number of controller-owned * auxiliary resources * @get_aux_resources: ops to retrieve controller-owned auxiliary resources + * @delegate_dma_chan: ops to delegate a controller-owned DMA channel to t= he + * host + * @reclaim_dma_chan: ops to reclaim a previously delegated DMA channel. + * The callback quiesces the channel or its provider-defined + * sharing group when requested. * @owner: the module owner containing the ops */ struct pci_epc_ops { @@ -210,6 +217,11 @@ struct pci_epc_ops { int (*get_aux_resources)(struct pci_epc *epc, u8 func_no, u8 vfunc_no, struct pci_epc_aux_resource *resources, int num_resources); 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charset="utf-8" Expose the DesignWare endpoint-integrated eDMA register window, logical DMA channels, and linked-list descriptor memories through the EPC auxiliary resource API. This lets endpoint functions decide which channels to publish to the host. When the DMA register window is already visible through a reserved BAR region, report its BAR and offset. Otherwise report it as a normal physical resource so an endpoint function can map it. DMA channel resources carry hardware channel selectors and refer to linked-list descriptor memory by ID. Expose DMA controller and channel resources only after the local DW eDMA provider has been registered, and only expose channels whose linked-list descriptor memory is available. The interrupt-emulation doorbell remains reported when the local DW eDMA provider is registered and its offset is valid, even if linked-list resources are unavailable. DWC non-LL exposure needs a metadata ABI and host parser extension, so leave it unsupported for now. Reject VF auxiliary resource queries because the RC-programmable DWC eDMA/HDMA register window is assigned to a PF BAR only. Signed-off-by: Koichiro Den --- Changes in v5: - Keep reporting the standalone doorbell for a registered provider when linked-list DMA resources are unavailable. (Sashiko) .../pci/controller/dwc/pcie-designware-ep.c | 120 +++++++++++++++++- 1 file changed, 116 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index 7d2794945704..ef1e2b6d85cf 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -858,6 +858,36 @@ dw_pcie_ep_find_bar_rsvd_region(struct dw_pcie_ep *ep, return NULL; } =20 +static bool dw_pcie_ep_has_edma_ll_resources(struct dw_edma_chip *edma) +{ + unsigned int i; + + if (!edma->dw) + return false; + + for (i =3D 0; i < edma->ll_wr_cnt; i++) + if (!edma->ll_region_wr[i].sz) + return false; + + for (i =3D 0; i < edma->ll_rd_cnt; i++) + if (!edma->ll_region_rd[i].sz) + return false; + + return true; +} + +static int dw_pcie_ep_check_edma_vfunc(u8 vfunc_no) +{ + /* + * The DWC endpoint databook says it is not possible to assign the + * DMA/HDMA registers to any Virtual Function. + */ + if (vfunc_no) + return -EOPNOTSUPP; + + return 0; +} + static int dw_pcie_ep_get_aux_resources_count(struct pci_epc *epc, u8 func_no, u8 vfunc_no) @@ -865,14 +895,23 @@ dw_pcie_ep_get_aux_resources_count(struct pci_epc *ep= c, u8 func_no, struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); struct dw_edma_chip *edma =3D &pci->edma; + int ret; + int count =3D 0; =20 if (!pci->edma_reg_size) return 0; =20 - if (edma->db_offset =3D=3D ~0) - return 0; + ret =3D dw_pcie_ep_check_edma_vfunc(vfunc_no); + if (ret) + return ret; =20 - return 1; + if (dw_pcie_ep_has_edma_ll_resources(edma)) + count +=3D 1 + 2 * (edma->ll_wr_cnt + edma->ll_rd_cnt); + + if (edma->dw && edma->db_offset !=3D ~0) + count++; + + return count; } =20 static int @@ -888,6 +927,8 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 fu= nc_no, u8 vfunc_no, resource_size_t db_offset =3D edma->db_offset; resource_size_t dma_ctrl_bar_offset =3D 0; resource_size_t dma_reg_size; + bool has_edma_ll_resources; + unsigned int i; int count; =20 count =3D dw_pcie_ep_get_aux_resources_count(epc, func_no, vfunc_no); @@ -901,6 +942,7 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 fu= nc_no, u8 vfunc_no, return 0; =20 dma_reg_size =3D pci->edma_reg_size; + has_edma_ll_resources =3D dw_pcie_ep_has_edma_ll_resources(edma); =20 rsvd =3D dw_pcie_ep_find_bar_rsvd_region(ep, PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO, @@ -909,6 +951,76 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8 f= unc_no, u8 vfunc_no, if (rsvd && rsvd->size < dma_reg_size) dma_reg_size =3D rsvd->size; =20 + count =3D 0; + if (has_edma_ll_resources) { + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CTRL_MMIO, + .phys_addr =3D pci->edma_reg_phys, + .size =3D dma_reg_size, + .bar =3D dma_ctrl_bar, + .bar_offset =3D dma_ctrl_bar_offset, + .u.dma_ctrl =3D { + .reg_layout =3D PCI_EPC_AUX_DMA_REG_LAYOUT_DW_EDMA, + .reg_layout_data =3D edma->mf, + .ep_to_rc_ch_cnt =3D edma->ll_wr_cnt, + .rc_to_ep_ch_cnt =3D edma->ll_rd_cnt, + }, + }; + + for (i =3D 0; i < edma->ll_wr_cnt; i++) { + struct dw_edma_region *ll =3D &edma->ll_region_wr[i]; + u16 desc_mem_id =3D i; + + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CHAN, + .bar =3D NO_BAR, + .u.dma_chan =3D { + .dir =3D PCI_EPC_AUX_DMA_EP_TO_RC, + .hw_ch =3D i, + .desc_mem_id =3D desc_mem_id, + }, + }; + + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_DESC_MEM, + .phys_addr =3D ll->paddr, + .size =3D ll->sz, + .bar =3D NO_BAR, + .u.dma_desc =3D { + .id =3D desc_mem_id, + }, + }; + } + + for (i =3D 0; i < edma->ll_rd_cnt; i++) { + struct dw_edma_region *ll =3D &edma->ll_region_rd[i]; + u16 desc_mem_id =3D edma->ll_wr_cnt + i; + + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_CHAN, + .bar =3D NO_BAR, + .u.dma_chan =3D { + .dir =3D PCI_EPC_AUX_DMA_RC_TO_EP, + .hw_ch =3D i, + .desc_mem_id =3D desc_mem_id, + }, + }; + + resources[count++] =3D (struct pci_epc_aux_resource) { + .type =3D PCI_EPC_AUX_DMA_DESC_MEM, + .phys_addr =3D ll->paddr, + .size =3D ll->sz, + .bar =3D NO_BAR, + .u.dma_desc =3D { + .id =3D desc_mem_id, + }, + }; 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charset="utf-8" Endpoint functions that expose endpoint-local DesignWare eDMA channels to a remote host need to reserve exact hardware channels and hand interrupt ownership to the remote side before publishing the channels. Add DW eDMA-specific helpers that request a write/read hardware channel through DMAengine, keep the hardware-channel filter private to dw-edma, and switch the selected endpoint-local channel to remote interrupt routing after the channel has been successfully reserved. The matching release helper can quiesce the channel while it is still remote-routed, then restores the channel's default routing before releasing the DMAengine reservation. This lets callers skip quiesce when unwinding a reservation that was never exposed to host programming. Release is best-effort because its callers cannot abort teardown. Report a quiesce failure locally, but always restore the default routing and release the DMAengine reservation. Signed-off-by: Koichiro Den --- Changes in v5: - Keep release best-effort while reporting quiesce failures. - Serialize irq_mode restoration with channel state updates. (Sashiko) - Use guard()/scoped_guard() for new code. drivers/dma/dw-edma/dw-edma-core.c | 91 ++++++++++++++++++++++++++++++ include/linux/dma/edma.h | 14 +++++ 2 files changed, 105 insertions(+) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-ed= ma-core.c index 43f8280b5811..89781d1c1d6e 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -1162,6 +1162,97 @@ int dw_edma_remove(struct dw_edma_chip *chip) } EXPORT_SYMBOL_GPL(dw_edma_remove); =20 +struct dw_edma_delegated_chan_filter_args { + struct device *dma_dev; + bool write; + u16 id; +}; + +static bool dw_edma_delegated_chan_filter(struct dma_chan *dchan, void *pa= ram) +{ + struct dw_edma_delegated_chan_filter_args *filter =3D param; + struct dw_edma_chan *chan; + + if (!filter || dchan->device->dev !=3D filter->dma_dev) + return false; + + chan =3D dchan2dw_edma_chan(dchan); + + return chan->dir =3D=3D (filter->write ? EDMA_DIR_WRITE : EDMA_DIR_READ) = && + chan->id =3D=3D filter->id; +} + +static int dw_edma_delegate_chan(struct dma_chan *dchan) +{ + struct dw_edma_chan *chan =3D dchan2dw_edma_chan(dchan); + int ret =3D 0; + + if (!(chan->dw->chip->flags & DW_EDMA_CHIP_LOCAL)) + return -EINVAL; + + guard(spinlock_irqsave)(&chan->vc.lock); + + if (chan->configured || chan->status !=3D EDMA_ST_IDLE || + chan->request !=3D EDMA_REQ_NONE) + ret =3D -EBUSY; + else + chan->irq_mode =3D DW_EDMA_CH_IRQ_REMOTE; + + return ret; +} + +struct dma_chan *dw_edma_request_delegated_chan(struct device *dma_dev, + bool write, u16 id) +{ + struct dw_edma_delegated_chan_filter_args filter =3D { + .dma_dev =3D dma_dev, + .write =3D write, + .id =3D id, + }; + struct dma_chan *dchan; + dma_cap_mask_t mask; + + if (!dma_dev) + return NULL; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + dchan =3D dma_request_channel(mask, dw_edma_delegated_chan_filter, + &filter); + if (!dchan) + return NULL; + + if (dw_edma_delegate_chan(dchan)) { + dma_release_channel(dchan); + return NULL; + } + + return dchan; +} +EXPORT_SYMBOL_GPL(dw_edma_request_delegated_chan); + +void dw_edma_release_delegated_chan(struct dma_chan *dchan, bool quiesce) +{ + struct dw_edma_chan *chan; + + if (!dchan) + return; + + chan =3D dchan2dw_edma_chan(dchan); + if (quiesce && dw_edma_core_ch_quiesce(chan)) + dev_warn(chan->dw->chip->dev, + "failed to quiesce delegated %s channel %u\n", + chan->dir =3D=3D EDMA_DIR_WRITE ? "write" : "read", + chan->id); + + scoped_guard(spinlock_irqsave, &chan->vc.lock) + chan->irq_mode =3D dw_edma_get_default_irq_mode(chan); + + dma_release_channel(dchan); +} +EXPORT_SYMBOL_GPL(dw_edma_release_delegated_chan); + MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("Synopsys DesignWare eDMA controller core driver"); MODULE_AUTHOR("Gustavo Pimentel "); diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 45f66fc523d7..1c932e5addb4 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -151,6 +151,9 @@ struct dw_edma_chip { #if IS_REACHABLE(CONFIG_DW_EDMA) int dw_edma_probe(struct dw_edma_chip *chip); int dw_edma_remove(struct dw_edma_chip *chip); +struct dma_chan *dw_edma_request_delegated_chan(struct device *dma_dev, + bool write, u16 id); +void dw_edma_release_delegated_chan(struct dma_chan *chan, bool quiesce); #else static inline int dw_edma_probe(struct dw_edma_chip *chip) { @@ -161,6 +164,17 @@ static inline int dw_edma_remove(struct dw_edma_chip *= chip) { return 0; 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charset="utf-8" Implement the EPC DMA channel delegation operations for DesignWare endpoint controllers. The DWC backend uses the local DesignWare eDMA provider to reserve the requested hardware channel and returns it as an opaque EPC DMA channel handle to generic endpoint functions. Validate the requested direction and hardware channel against the linked-list channel counts before delegation. DWC eDMA/HDMA generates DMA requests with a programmable requester function number. For delegated channels, the host-side dw-edma-pcie instance bound to the exposed DMA function reserves the channel and programs its own PCI_FUNC() into the per-channel requester field; the endpoint-side chip func_no does not participate in that handoff. Reject VF requests because the RC-programmable DWC eDMA/HDMA register window is assigned to a PF BAR only. Reclaim releases the delegated local channel through the DesignWare eDMA provider, which returns it to endpoint ownership. Propagate the EPC quiesce request so bind failure paths can release unexposed reservations without touching DMA engine state. Signed-off-by: Koichiro Den --- Changes in v5: - No changes. .../pci/controller/dwc/pcie-designware-ep.c | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/= controller/dwc/pcie-designware-ep.c index ef1e2b6d85cf..13ba3122c9cc 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1045,6 +1045,59 @@ dw_pcie_ep_get_aux_resources(struct pci_epc *epc, u8= func_no, u8 vfunc_no, return 0; } =20 +static int dw_pcie_ep_delegate_dma_chan(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, + enum pci_epc_aux_dma_dir dir, u16 hw_ch, + void **data) +{ + struct dw_pcie_ep *ep =3D epc_get_drvdata(epc); + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + struct dw_edma_chip *edma =3D &pci->edma; + struct dma_chan *chan; + int ret; + bool write; + + if (!data) + return -EINVAL; + *data =3D NULL; + + ret =3D dw_pcie_ep_check_edma_vfunc(vfunc_no); + if (ret) + return ret; + + if (!edma->dw) + return -ENODEV; + + switch (dir) { + case PCI_EPC_AUX_DMA_EP_TO_RC: + if (hw_ch >=3D edma->ll_wr_cnt) + return -EINVAL; + write =3D true; + break; + case PCI_EPC_AUX_DMA_RC_TO_EP: + if (hw_ch >=3D edma->ll_rd_cnt) + return -EINVAL; + write =3D false; + break; + default: + return -EINVAL; + } + + chan =3D dw_edma_request_delegated_chan(edma->dev, write, hw_ch); + if (!chan) + return -EBUSY; + + *data =3D chan; + + return 0; +} + +static void dw_pcie_ep_reclaim_dma_chan(struct pci_epc *epc, u8 func_no, + u8 vfunc_no, void *data, bool quiesce) +{ + dw_edma_release_delegated_chan(data, quiesce); +} + static const struct pci_epc_ops epc_ops =3D { .write_header =3D dw_pcie_ep_write_header, .set_bar =3D dw_pcie_ep_set_bar, @@ -1062,6 +1115,8 @@ static const struct pci_epc_ops epc_ops =3D { .get_features =3D dw_pcie_ep_get_features, .get_aux_resources_count =3D dw_pcie_ep_get_aux_resources_count, .get_aux_resources =3D dw_pcie_ep_get_aux_resources, + .delegate_dma_chan =3D dw_pcie_ep_delegate_dma_chan, + .reclaim_dma_chan =3D dw_pcie_ep_reclaim_dma_chan, }; =20 /** --=20 2.51.0