From nobody Sat Jul 25 04:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 372A729405; Sat, 18 Jul 2026 00:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784333828; cv=none; b=PmEdJmY9/v8rruWmr2aKxnTF08Ecsd/YvSGdOfNxjlOeECo1YfDtymLFIH1Plx1yM5V3bhyWIDduxIepuL76EuiPSC9XFmfz57evp0b8yOZ/rNPzfLaL8Fjg7EwKjE867/5CTkbZdmvUhde9ZGDZ7X/WEG0XTQIS3M6rtHky98g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784333828; c=relaxed/simple; bh=IjhF3bJG7lpE5hPCToTh4KEJBQS+j04w+NF+bWNNLRk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AfY24N+77Joa8guKzXxA+YwrjxAQ9+sqoypqw+WsCxPp0BZ/dAd1ulBl8AbZT5SyAasnC+5hpPrvzJ/YN+0T+4RFj3KSUBZWAl5jEE1yxfCVxqWce4+5vN2/cRWUD3nnfHQlhWAVkWMeIERQT2TI3x6SgNvkuze1ai/IBt4DIH4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Iwbd1lyV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Iwbd1lyV" Received: by smtp.kernel.org (Postfix) with ESMTPS id C6B10C2BCB8; Sat, 18 Jul 2026 00:17:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784333827; bh=IjhF3bJG7lpE5hPCToTh4KEJBQS+j04w+NF+bWNNLRk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=Iwbd1lyVu8QzOIKwVq2l5yUP10AVcgG8R4uExGWX6F5+5/TWXmwkdV870ClfDIlrm xtgHkpAVwANzywyBiIuG/ymc74NzcMwrDrN88kwMAMIw3MR56TN7PxZFOlZVJ5GHOH Ugvuvdt0S2vr23kYlGISX0v4BPH21oQc+cqWxA4DZ1VIRWqwYuL9RfGGEy60OE1vPx XFfh3lOwu7FA0j2sjQFSSM1rDuy98Od7nppIzY+HpGYVGdnZfhwkKmjlyXiu85XDyR LrRUOKjRhVL+aQpcD33M5j5hwHf4kfNzAaAOE59mtrvuh0kww172TIDlalBrvprd2+ id1xRKR2P+Tgg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5E83C4451B; Sat, 18 Jul 2026 00:17:07 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Fri, 17 Jul 2026 19:17:02 -0500 Subject: [PATCH 1/2] dt-bindings: soc: tegra: pmc: Document Tegra210B01 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-t210b01-pmc-v1-1-bf776be8b3a7@gmail.com> References: <20260717-t210b01-pmc-v1-0-bf776be8b3a7@gmail.com> In-Reply-To: <20260717-t210b01-pmc-v1-0-bf776be8b3a7@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter Cc: Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784333826; l=1159; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=z8MVuT3Opy0H7p0Pt9awDs1uMy1qRf8KVNgyT854Yos=; b=XsB/DS8y6v/k7RXEqzTUnFyXB+PzGvsNxv3DGFJa+UywfR4Tug+7qmEZfUfvVifwri9xsCiaf lSg31jpknrAACPljVcVo3UTVPiQ1wB2z640kiNQMbjk+Qro6E9EpqkX X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Aaron Kling The PMC in Tegra210B01 is very similar to the one in the original Tegra210, but has a few powergate and pad differences. Document this soc. Signed-off-by: Aaron Kling --- Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml | 5 ++= ++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc= .yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml index f516960dbbefb..8ec36c49f9594 100644 --- a/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml +++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml @@ -18,6 +18,7 @@ properties: - nvidia,tegra114-pmc - nvidia,tegra124-pmc - nvidia,tegra210-pmc + - nvidia,tegra210b01-pmc =20 reg: maxItems: 1 @@ -346,7 +347,9 @@ allOf: properties: compatible: contains: - const: nvidia,tegra210-pmc + enum: + - nvidia,tegra210-pmc + - nvidia,tegra210b01-pmc then: properties: pinmux: --=20 2.54.0 From nobody Sat Jul 25 04:54:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3727DCA5A; Sat, 18 Jul 2026 00:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784333828; cv=none; b=mZ2dJR4GKNTdwo6lz9fcw+AekTm/fdHMJeYA/ijWM4QwoDS1WKupeoli5pIiLqBnzJzeTuCcJ7hHdmqH8gY1lzjDTxoL4YCG5IO3tWKwuLuGyOx0BdEsasvGSunBwhbcEj7ki/ab2l6Xt+j/yJK9wO7e1WjUZC8J1KZvcPfYNYY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784333828; c=relaxed/simple; bh=/vafxQxx1ICs6jDSq1iGlulHcZH0tKwkiYcwuhFdlzE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Zr6sRBMS+p81jsYMbnT6H4uX+Soa3DWahCrU8L97a5mYO8Fyblwps4c+7J9cjQL21zwf34McmDBwOMc+ooSw9D9dr+wTOJCK1bLBlYdI6+dGxL7EPRKRrXTGcpS6r5dImVeDLZ6XtbsoO6hBTaCl7MUNF8Be0E6sHjE+QZ6DRwU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WQK2R4W5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WQK2R4W5" Received: by smtp.kernel.org (Postfix) with ESMTPS id D4D3FC2BCF4; Sat, 18 Jul 2026 00:17:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784333827; bh=/vafxQxx1ICs6jDSq1iGlulHcZH0tKwkiYcwuhFdlzE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=WQK2R4W5bAybkfl4mR+eR5LgyrGV7VUgmg+fwRkz27ImdoLSGkDR4ykT1LgcmQS+A RMNaJAtb8iorOJEP+23PYWtrpgHUgiTbWRhvKKbq4Fdk38K5skYWv3r5CPbJrIQ7hP G0Wy1mjuRPaqC2FSbo4QcVzLJQCUnhZCr+gX5oL/o8CH2gBidBiA6NDHnakPdEhVnp zt6ldGsD2n/DAfLUXataTD81rpcaNgtw5vG74qrgF8spHzPICBfYCIOR73twk3E/Bn LQ+NpfEIsdCqvMmMjE4cxhXWFjdmOyBfe1IxiyARJQpC3H5Frrw8P/BGf3ymrsA4eC VtjbElbl8MHrg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5886C44523; Sat, 18 Jul 2026 00:17:07 +0000 (UTC) From: Aaron Kling via B4 Relay Date: Fri, 17 Jul 2026 19:17:03 -0500 Subject: [PATCH 2/2] soc/tegra: pmc: Add Tegra210B01 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-t210b01-pmc-v1-2-bf776be8b3a7@gmail.com> References: <20260717-t210b01-pmc-v1-0-bf776be8b3a7@gmail.com> In-Reply-To: <20260717-t210b01-pmc-v1-0-bf776be8b3a7@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter Cc: Thierry Reding , devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Aaron Kling , Azkali Manad , Thomas Makin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784333826; l=9501; i=webgeek1234@gmail.com; s=20250217; h=from:subject:message-id; bh=OCQonk6jGTpoZZXZxgWdn6dt1IMUFa28q+B6W0rxEWc=; b=zrJSCM70nwdjvdIxOUl62PP0w5YCTLKd/jXQo7oNePjcq69OmsfLPQxoZTsrVWY0+FaXRFp9o ljccunzp8wXASUpezwWtoLxIsyjUOCkzbdolB4zFHqXchiAD/f5z2X+ X-Developer-Key: i=webgeek1234@gmail.com; a=ed25519; pk=TQwd6q26txw7bkK7B8qtI/kcAohZc7bHHGSD7domdrU= X-Endpoint-Received: by B4 Relay for webgeek1234@gmail.com/20250217 with auth_id=342 X-Original-From: Aaron Kling Reply-To: webgeek1234@gmail.com From: Azkali Manad The PMC in Tegra210B01 is very similar to the one in the original Tegra210, but has a few powergate and pad differences. Add support for this soc. Signed-off-by: Azkali Manad Co-developed-by: Thomas Makin Signed-off-by: Thomas Makin Co-developed-by: Aaron Kling Signed-off-by: Aaron Kling --- drivers/soc/tegra/pmc.c | 160 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 160 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index f419a5395545f..4d77aa66d690c 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -3744,6 +3744,32 @@ static const char * const tegra210_powergates[] =3D { [TEGRA_POWERGATE_VE2] =3D "ve2", }; =20 +static const char * const tegra210b01_powergates[] =3D { + [TEGRA_POWERGATE_CPU] =3D "crail", + [TEGRA_POWERGATE_3D] =3D "3d", + [TEGRA_POWERGATE_PCIE] =3D "pcie", + [TEGRA_POWERGATE_MPE] =3D "mpe", + [TEGRA_POWERGATE_SATA] =3D "sata", + [TEGRA_POWERGATE_CPU1] =3D "cpu1", + [TEGRA_POWERGATE_CPU2] =3D "cpu2", + [TEGRA_POWERGATE_CPU3] =3D "cpu3", + [TEGRA_POWERGATE_CPU0] =3D "cpu0", + [TEGRA_POWERGATE_C0NC] =3D "c0nc", + [TEGRA_POWERGATE_SOR] =3D "sor", + [TEGRA_POWERGATE_DIS] =3D "dis", + [TEGRA_POWERGATE_DISB] =3D "disb", + [TEGRA_POWERGATE_XUSBA] =3D "xusba", + [TEGRA_POWERGATE_XUSBB] =3D "xusbb", + [TEGRA_POWERGATE_XUSBC] =3D "xusbc", + [TEGRA_POWERGATE_VIC] =3D "vic", + [TEGRA_POWERGATE_IRAM] =3D "iram", + [TEGRA_POWERGATE_NVDEC] =3D "nvdec", + [TEGRA_POWERGATE_NVJPG] =3D "nvjpg", + [TEGRA_POWERGATE_AUD] =3D "aud", + [TEGRA_POWERGATE_DFD] =3D "dfd", +}; + + static const u8 tegra210_cpu_powergates[] =3D { TEGRA_POWERGATE_CPU0, TEGRA_POWERGATE_CPU1, @@ -3897,6 +3923,139 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = =3D { .has_single_mmio_aperture =3D true, }; =20 +static const struct tegra_io_pad_soc tegra210b01_io_pads[] =3D { + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO, 17, 0x1b8, 0x1bc, "audio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_AUDIO_HV, 29, 0x1c0, 0x1c4, "audio-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CAM, 4, 0x1c0, 0x1c4, "cam"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x1b8, 0x1bc, "csia"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x1b8, 0x1bc, "csib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 10, 0x1c0, 0x1c4, "csic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 11, 0x1c0, 0x1c4, "csid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 12, 0x1c0, 0x1c4, "csie"), + TEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 13, 0x1c0, 0x1c4, "csif"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DBG, 25, 0x1b8, 0x1bc, "dbg"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DEBUG_NONAO, 26, 0x1b8, 0x1bc, "debug-nonao"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DMIC, 18, 0x1c0, 0x1c4, "dmic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DP, 19, 0x1c0, 0x1c4, "dp"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSI, 2, 0x1b8, 0x1bc, "dsi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIB, 7, 0x1c0, 0x1c4, "dsib"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSIC, 8, 0x1c0, 0x1c4, "dsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_DSID, 9, 0x1c0, 0x1c4, "dsid"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC, 3, 0x1c0, 0x1c4, "emmc"), + TEGRA_IO_PAD(TEGRA_IO_PAD_EMMC2, 5, 0x1c0, 0x1c4, "emmc2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_GPIO, 27, 0x1b8, 0x1bc, "gpio"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HDMI, 28, 0x1b8, 0x1bc, "hdmi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_HSIC, 19, 0x1b8, 0x1bc, "hsic"), + TEGRA_IO_PAD(TEGRA_IO_PAD_LVDS, 25, 0x1c0, 0x1c4, "lvds"), + TEGRA_IO_PAD(TEGRA_IO_PAD_MIPI_BIAS, 3, 0x1b8, 0x1bc, "mipi-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_BIAS, 4, 0x1b8, 0x1bc, "pex-bias"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK1, 5, 0x1b8, 0x1bc, "pex-clk1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CLK2, 6, 0x1b8, 0x1bc, "pex-clk2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, UINT_MAX, UINT_MAX, "pex-c= ntrl"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 1, 0x1c0, 0x1c4, "sdmmc1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC3, 2, 0x1c0, 0x1c4, "sdmmc3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SPI, 14, 0x1c0, 0x1c4, "spi"), + TEGRA_IO_PAD(TEGRA_IO_PAD_SPI_HV, 15, 0x1c0, 0x1c4, "spi-hv"), + TEGRA_IO_PAD(TEGRA_IO_PAD_UART, 14, 0x1b8, 0x1bc, "uart"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB0, 9, 0x1b8, 0x1bc, "usb0"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB1, 10, 0x1b8, 0x1bc, "usb1"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB2, 11, 0x1b8, 0x1bc, "usb2"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB3, 18, 0x1b8, 0x1bc, "usb3"), + TEGRA_IO_PAD(TEGRA_IO_PAD_USB_BIAS, 12, 0x1b8, 0x1bc, "usb-bias"), +}; + +static const struct tegra_io_pad_vctrl tegra210b01_io_pad_vctrls[] =3D { + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO, PMC_PWR_DET_VALUE, 5), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_AUDIO_HV, PMC_PWR_DET_VALUE, 18), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_CAM, PMC_PWR_DET_VALUE, 10), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DBG, PMC_PWR_DET_VALUE, 19), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_DMIC, PMC_PWR_DET_VALUE, 20), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_GPIO, PMC_PWR_DET_VALUE, 21), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_PEX_CNTRL, PMC_PWR_DET_VALUE, 11), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1, PMC_PWR_DET_VALUE, 12), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC3, PMC_PWR_DET_VALUE, 13), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI, PMC_PWR_DET_VALUE, 22), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_SPI_HV, PMC_PWR_DET_VALUE, 23), + TEGRA_IO_PAD_VCTRL(TEGRA_IO_PAD_UART, PMC_PWR_DET_VALUE, 2), +}; + +static const struct pinctrl_pin_desc tegra210b01_pin_descs[] =3D { + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO, "audio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_AUDIO_HV, "audio-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CAM, "cam"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, "csia"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, "csib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, "csic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, "csid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, "csie"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, "csif"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DBG, "dbg"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DEBUG_NONAO, "debug-nonao"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DMIC, "dmic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DP, "dp"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSI, "dsi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIB, "dsib"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSIC, "dsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_DSID, "dsid"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC, "emmc"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EMMC2, "emmc2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_GPIO, "gpio"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI, "hdmi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HSIC, "hsic"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_LVDS, "lvds"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_MIPI_BIAS, "mipi-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_BIAS, "pex-bias"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK1, "pex-clk1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CLK2, "pex-clk2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_PEX_CNTRL, "pex-cntrl"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, "sdmmc1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC3, "sdmmc3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI, "spi"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SPI_HV, "spi-hv"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UART, "uart"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB0, "usb0"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB1, "usb1"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB2, "usb2"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB3, "usb3"), + TEGRA_IO_PIN_DESC(TEGRA_IO_PAD_USB_BIAS, "usb-bias"), +}; + +static const struct tegra_pmc_soc tegra210b01_pmc_soc =3D { + .supports_core_domain =3D false, + .num_powergates =3D ARRAY_SIZE(tegra210b01_powergates), + .powergates =3D tegra210b01_powergates, + .num_cpu_powergates =3D ARRAY_SIZE(tegra210_cpu_powergates), + .cpu_powergates =3D tegra210_cpu_powergates, + .has_tsense_reset =3D true, + .has_gpu_clamps =3D true, + .needs_mbist_war =3D false, + .has_io_pad_wren =3D false, + .maybe_tz_only =3D true, + .num_io_pads =3D ARRAY_SIZE(tegra210b01_io_pads), + .io_pads =3D tegra210b01_io_pads, + .num_io_pad_vctrls =3D ARRAY_SIZE(tegra210b01_io_pad_vctrls), + .io_pad_vctrls =3D tegra210b01_io_pad_vctrls, + .num_pin_descs =3D ARRAY_SIZE(tegra210b01_pin_descs), + .pin_descs =3D tegra210b01_pin_descs, + .regs =3D &tegra20_pmc_regs, + .init =3D tegra20_pmc_init, + .setup_irq_polarity =3D tegra20_pmc_setup_irq_polarity, + .powergate_set =3D tegra114_powergate_set, + .irq_set_wake =3D tegra210_pmc_irq_set_wake, + .irq_set_type =3D tegra210_pmc_irq_set_type, + .reset_sources =3D tegra210_reset_sources, + .num_reset_sources =3D ARRAY_SIZE(tegra210_reset_sources), + .reset_levels =3D NULL, + .num_reset_levels =3D 0, + .num_wake_events =3D ARRAY_SIZE(tegra210_wake_events), + .wake_events =3D tegra210_wake_events, + .pmc_clks_data =3D tegra_pmc_clks_data, + .num_pmc_clks =3D ARRAY_SIZE(tegra_pmc_clks_data), + .has_blink_output =3D true, + .has_usb_sleepwalk =3D true, + .has_single_mmio_aperture =3D true, +}; + static const struct tegra_io_pad_soc tegra186_io_pads[] =3D { TEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x74, 0x78, "csia"), TEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x74, 0x78, "csib"), @@ -4824,6 +4983,7 @@ static const struct of_device_id tegra_pmc_match[] = =3D { { .compatible =3D "nvidia,tegra194-pmc", .data =3D &tegra194_pmc_soc }, { .compatible =3D "nvidia,tegra186-pmc", .data =3D &tegra186_pmc_soc }, { .compatible =3D "nvidia,tegra210-pmc", .data =3D &tegra210_pmc_soc }, + { .compatible =3D "nvidia,tegra210b01-pmc", .data =3D &tegra210b01_pmc_so= c }, { .compatible =3D "nvidia,tegra132-pmc", .data =3D &tegra124_pmc_soc }, { .compatible =3D "nvidia,tegra124-pmc", .data =3D &tegra124_pmc_soc }, { .compatible =3D "nvidia,tegra114-pmc", .data =3D &tegra114_pmc_soc }, --=20 2.54.0