From nobody Sat Jul 25 04:56:32 2026 Received: from mail-ot1-f48.google.com (mail-ot1-f48.google.com [209.85.210.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CB39429032 for ; Fri, 17 Jul 2026 17:34:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784309670; cv=none; b=Ft/5dko/tYCs09SgXPj/SROSBlhl/TRpuEc0w1cp+4am8rC0qKSCDGYc+98/jbFyzmulftHPA561sX4oyEiOOJ9ZOmeW/m+bCY1OsKnLou/Z8bW5FZOLeMeIn7JnnpWPu1/tQ2qE4WvBHu7IlElLSMynZKo3D9fpd6el408wwjw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784309670; c=relaxed/simple; bh=f+Q3D9sl+haJbd8q6IQSARPqlTZdxv8bfThP1g3/NoA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Oz4PfQwPL8oPcC4t26yDvwBQaWpg1idUM6cp8bSJ3twKvcwYnlcdJoAGm2fRn9BlB613/o2C583Za46EKJdD3p9UR5UTx7i3ZN3og5nay9+TQGUp+/rYhSmAOQmiYhEdYieL/DvDjHY4p510m6ompbhDXcLrhElkyc4ziFycbRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lMhxuQmT; arc=none smtp.client-ip=209.85.210.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lMhxuQmT" Received: by mail-ot1-f48.google.com with SMTP id 46e09a7af769-7ec3b429a3aso3204705a34.1 for ; Fri, 17 Jul 2026 10:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784309668; x=1784914468; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=VlsKLWHzuG2ZqAxSmlNnrAEdRDdQeGiW44cbYcWz6fU=; b=lMhxuQmTG8gKTuQdNMH/kPL3bjOEKhbS5+xL1GWHEXmMSDR8/4pusK4Sz4FQLByTBk hzIfJGzgXhu5926RGc7iTI7sjWfhLdMpoEndqvRKJn/GwySCwg48fbpod1MludirdHZ2 /ST/mql8GC0BUk8up4PbIfiFb0HJwtXrMOdoi0x2pbRRP6bVcDy5jWgWYV4amzYZ3WUs ixsVquJSI/ou1Sqa8QKM02xHzEUHo4qyHK0phb2LH4vqFE/SK04yUb4gR2aGt1pT9bBF AwpDPLj3GstoG1lNGsL+GChZM8OkpOY83qxjPYaiNnKkO9jD0Xi1FdeTto7JGpUKRUir VaaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784309668; x=1784914468; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=VlsKLWHzuG2ZqAxSmlNnrAEdRDdQeGiW44cbYcWz6fU=; b=Z/fGhYfDVSmCthLdfl8d4+xELaI3RJHhJ4uJPxPyO3HxMVI1GXJE9TsZMshpUQ1QSm O7pPOhFTHa9NNAHEr+q6X5baGr6ujaCS+bCC+ETDLe4RA3arhlFzEyQMsriSEKjuGYeE SfYAPRIz3xBd5e5zJiM/esSJSF0Ju/qrxwYzUTGX5WphLvnuVWS3QcVn1/8yZ1t5Q3nI 64C4rWxstwnGJsFlj0P7t+X5hTE8AoaZqudUaUfykpxtrsQiH+jAhd08UE6N542lti30 hwXMZydFp3MkvoEQFv33R2LfMwmLO6OHc9DeaoFQMvC+WncMH9jbqudpwLndCSj58jiL 7aNg== X-Forwarded-Encrypted: i=1; AHgh+RqYBriBmrWmRmZZiCaGIWiG2UGAiuDNERz3knEjJc1UHletLuZWVQEGmJB/yhrEsUvZWOqSBMTenPVO8Ms=@vger.kernel.org X-Gm-Message-State: AOJu0YyFtFXvbOAGZebUc+O93rU70kc/bF9F/nwURHJlZA19iWewsR91 fd0bL3e68HipubcogIlwUYB7G4bdluy462P+1ixFxY3SBMFzyzi9dYOM5CPHjrwp3I8= X-Gm-Gg: AfdE7cmTbu4BrGieHb7qwUGIVXQTnyzFSiDfxXYX4/Uir+vsWIbjr/yHF8ImDEzm5IB phixfwMRvJeCpUiOmnweJE6JTJYeEjYJLx4S57jrAhd+we3chr/jkwd2fVxhcel3YMwrTXLkLpO jtmxelvGt5avurccU/a7WEnbH16sOWxpxTyoAFeqjZNyuI6Fif4ny7sWvT6+65cwnHCG4Eriq4u hZJFnGyANIaFm3GJDcGUkNvUkashYtljnvylR0bGYG8eoSo+7AuItRRJBvhI7Xt4ZiYW1OdaeJt tlyFibpw1QOwJRXQ+NdsmxV4etPI2U/cJnehLycXoZIHgB+XyjIjGCo0mwiUVLAJQHPwxioEsUp 1nG2ER2kfL/0awWT+iVFXF4pi4TxU4n/SAyu03LEX4tGPruxTDiXjR1oqZwXx1rFa24zfRVSbz+ laMdFnSBX1jtis2uBip/BWWG0ZM3rdlev4eNQ1GmM8rQnbysAe9Mk5GuRiGvsC3rWXPKs6NI20E 8zkJK3EUk+LikvSDNimRiT0mz9Pw9lfvUa4ynw/vxbg3krf72llGA== X-Received: by 2002:a05:6830:6afa:b0:7e6:f4a3:1df5 with SMTP id 46e09a7af769-7eda08ae511mr1817637a34.1.1784309667752; Fri, 17 Jul 2026 10:34:27 -0700 (PDT) Received: from [127.0.1.1] (174-29-11-8.hlrn.qwest.net. [174.29.11.8]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7edad965130sm1677212a34.11.2026.07.17.10.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 10:34:25 -0700 (PDT) From: James Hilliard Date: Fri, 17 Jul 2026 11:33:57 -0600 Subject: [PATCH v2 1/3] mtd: rawnand: sunxi: group controller delay tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-submit-sunxi-nand-h6-h616-timings-v2-1-225515107640@gmail.com> References: <20260717-submit-sunxi-nand-h6-h616-timings-v2-0-225515107640@gmail.com> In-Reply-To: <20260717-submit-sunxi-nand-h6-h616-timings-v2-0-225515107640@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Genoud Cc: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The tWB and tRHW timing field encodings are controller properties, but they currently live in standalone lookup tables. Group them in a timing descriptor selected through the controller capability data. Point every existing controller at the legacy values so this is a pure preparation change. Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/sunxi_nand.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 02647565c8ba..d12cbb3c813c 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -237,6 +237,14 @@ struct sunxi_nand_hw_ecc { u32 ecc_ctl; }; =20 +#define SUNXI_NFC_TIMING_STEPS 4 + +/* Delay arrays contain internal NDFC clock cycles for field values 0 to 3= . */ +struct sunxi_nfc_timings { + s32 tWB[SUNXI_NFC_TIMING_STEPS]; + s32 tRHW[SUNXI_NFC_TIMING_STEPS]; +}; + /** * struct sunxi_nand_chip - stores NAND chip device related information * @@ -301,6 +309,7 @@ static inline struct sunxi_nand_chip *to_sunxi_nand(str= uct nand_chip *nand) * bytes to write * @nuser_data_tab: Size of @user_data_len_tab * @sram_size: Size of the NAND controller SRAM + * @timings: Controller timing characteristics */ struct sunxi_nfc_caps { bool has_mdma; @@ -327,6 +336,7 @@ struct sunxi_nfc_caps { unsigned int nuser_data_tab; unsigned int max_ecc_steps; int sram_size; + const struct sunxi_nfc_timings *timings; }; =20 /** @@ -1667,8 +1677,10 @@ static int sunxi_nfc_hw_ecc_write_oob(struct nand_ch= ip *nand, int page) return nand_prog_page_end_op(nand); } =20 -static const s32 tWB_lut[] =3D {6, 12, 16, 20}; -static const s32 tRHW_lut[] =3D {4, 8, 12, 20}; +static const struct sunxi_nfc_timings sun4i_a10_nfc_timings =3D { + .tWB =3D { 6, 12, 16, 20 }, + .tRHW =3D { 4, 8, 12, 20 }, +}; =20 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 dur= ation, u32 clk_period) @@ -1693,6 +1705,7 @@ static int sunxi_nfc_setup_interface(struct nand_chip= *nand, int csline, { struct sunxi_nand_chip *sunxi_nand =3D to_sunxi_nand(nand); struct sunxi_nfc *nfc =3D to_sunxi_nfc(sunxi_nand->nand.controller); + const struct sunxi_nfc_timings *nfc_timings =3D nfc->caps->timings; const struct nand_sdr_timings *timings; u32 min_clk_period =3D 0; s32 tWB, tADL, tWHR, tRHW, tCAD; @@ -1763,8 +1776,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, min_clk_period =3D DIV_ROUND_UP(timings->tWC_min, 2); =20 /* T16 - T19 + tCAD */ - if (timings->tWB_max > (min_clk_period * 20)) - min_clk_period =3D DIV_ROUND_UP(timings->tWB_max, 20); + if (timings->tWB_max > + (min_clk_period * nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tWB_max, + nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1]); =20 if (timings->tADL_min > (min_clk_period * 32)) min_clk_period =3D DIV_ROUND_UP(timings->tADL_min, 32); @@ -1772,8 +1787,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, if (timings->tWHR_min > (min_clk_period * 32)) min_clk_period =3D DIV_ROUND_UP(timings->tWHR_min, 32); =20 - if (timings->tRHW_min > (min_clk_period * 20)) - min_clk_period =3D DIV_ROUND_UP(timings->tRHW_min, 20); + if (timings->tRHW_min > + (min_clk_period * nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tRHW_min, + nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1]); =20 /* * In non-EDO, tREA should be less than tRP to guarantee that the @@ -1789,7 +1806,7 @@ static int sunxi_nfc_setup_interface(struct nand_chip= *nand, int csline, if (timings->tREA_max > min_clk_period && !timings->tRLOH_min) min_clk_period =3D timings->tREA_max; =20 - tWB =3D sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, + tWB =3D sunxi_nand_lookup_timing(nfc_timings->tWB, timings->tWB_max, min_clk_period); if (tWB < 0) { dev_err(nfc->dev, "unsupported tWB\n"); @@ -1808,7 +1825,7 @@ static int sunxi_nfc_setup_interface(struct nand_chip= *nand, int csline, return -EINVAL; } =20 - tRHW =3D sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, + tRHW =3D sunxi_nand_lookup_timing(nfc_timings->tRHW, timings->tRHW_min, min_clk_period); if (tRHW < 0) { dev_err(nfc->dev, "unsupported tRHW\n"); @@ -2595,6 +2612,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a10_caps= =3D { .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), .max_ecc_steps =3D 16, .sram_size =3D 1024, + .timings =3D &sun4i_a10_nfc_timings, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_a23_caps =3D { @@ -2617,6 +2635,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_a23_caps= =3D { .nstrengths =3D ARRAY_SIZE(sunxi_ecc_strengths_a10), .max_ecc_steps =3D 16, .sram_size =3D 1024, + .timings =3D &sun4i_a10_nfc_timings, }; =20 static const struct sunxi_nfc_caps sunxi_nfc_h616_caps =3D { @@ -2641,6 +2660,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_h616_cap= s =3D { .nuser_data_tab =3D ARRAY_SIZE(sunxi_user_data_len_h6), .max_ecc_steps =3D 32, .sram_size =3D 8192, + .timings =3D &sun4i_a10_nfc_timings, }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D { --=20 2.53.0 From nobody Sat Jul 25 04:56:32 2026 Received: from mail-ot1-f53.google.com (mail-ot1-f53.google.com [209.85.210.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82E0B3ED5D4 for ; Fri, 17 Jul 2026 17:34:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784309672; cv=none; b=JVzaSsATZb4EbnYRxe8Gao+ZYI7x4QeBpIm9iaHu4N4tRUp1DAGZ2OsjJCJ+uYlu0GHSE2cCwfBFD80+wJmd0Xv17v1UQEEQkN4C/yT11SPjnf8CL0zMCYKH1LkbsM9XtQ1cQPvNFNm+ua08RrGSd+8q6fO9+kvLSZ/XJr0SVLQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784309672; c=relaxed/simple; bh=44TY2dOMwcJODONgQHSuiNADRv/0XYu2Y2Iil3nCRsk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=kEz+UrOR9aQHkkLgxo5JSFmGDxXpZyLpBl8Y4PYlFqHUd0qTfFIbgzBOleYmMJPh1HUBNE0yjWans2VOu61PDIAkZlJY/3/7N0tv6padZ9GxEZR14GQ4CcphZyxeYBag568zK52m446eIa5dAl/DgcJeoy2rIGf91fQq0LwmFLg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=N0Qw0Vnk; arc=none smtp.client-ip=209.85.210.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="N0Qw0Vnk" Received: by mail-ot1-f53.google.com with SMTP id 46e09a7af769-7e6b554044fso6491323a34.0 for ; Fri, 17 Jul 2026 10:34:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784309669; x=1784914469; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fU/T4ePwxMvnfrbedCWGcOi9RX0frxKmTN5hi5W5USU=; b=N0Qw0VnkV9VIMaiwczEv7+YWI6QBlLBR61EduCNp+noYzWoJlh2mVHhy4HdbESacYM IEp2jvA0dyS5WG+0frTfsrBe4IHaYHiLazGnqApr4ixVaIoQ5cvQyp+MCQ6YjUJCedj4 1bKQXPV2a17vqmqSDqBYVM2CDjrpNTaQY2m03I9goN54DrtdJV5lfxRCbnEKRFfvSumq xt2DbtMvt5kzmM65joTssGqQEZsSoPpS8FGWpTWAG1oJbZHSh5tW0TgbgldSKYkmeYZo 7Q07hre21n1pmsJbjg5urZphLmlN6hTkMljIEnWOLNhNEMtuaXVUiWLK71p0HFni2NBL 0eEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784309669; x=1784914469; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=fU/T4ePwxMvnfrbedCWGcOi9RX0frxKmTN5hi5W5USU=; b=EGqHOcTKl5V7v3uVRe4JhybJr1uXsfiN+K+1hPgnVrHRg6Y+86saI33RTo9nONkMzK 3xM1VWmD/cPBNFg6cdYYa+870lgu0Ly8zFPaaRtSHSNX50svz3wGgmCKLUcaoo1a/MvG g2+eX1KlRvIJB++zRSNKra8PMk4zaGe+pJjBJPmM2pgTyzykhP13bHFk5V4sxFQuU28f VWfgaOF0rAeQsZ/KyCTdA70JfQHt+W/EdFSTNGLp9ol0zvwzD5ndR3DJKsHm3f3qFAV1 mEyL0f/DS6FawqQu1M2wlv2tij94psrqfXpKQMN0B0wcDk6fu7Jxj6GSp9iAsL7QaRAL 3Qog== X-Forwarded-Encrypted: i=1; AHgh+Rro0v567jPAOcTT2tIHLYPK6k24P0rGQbFBskAOWF0/BS7IUsr7557Tj6fMMOUx9TEWyySy0VtfWTzp/zo=@vger.kernel.org X-Gm-Message-State: AOJu0Yz7jKyUrq6pesoIxUUHNCHiVNssqI44soxp2o1AI9DHBWDUYSpz JSL8lpfrfOplyDZfy99zNWHb3udfz99TDlqXZ6zqos0Bua09779qIz9h X-Gm-Gg: AfdE7ckUGyuNDS9wf1+EfsyJWhO2I4Lh7YM7CV2mrlKkTpMdmunfkYfZATyKR+L+x4H 1eu7gMJXQ0LHtucfD0Cm0KizoZNkpvBHu2q+US7wvfkg96HVEZkQW3l9AvYzdaBYTuABxbIVPUQ 3S+MKNGB2qeAbNclCn4iFj/8oSnPlVEAiEdD1JRo3dO71CqqsKML+L5DcnjnF8aiQCRKdN9Q6xl nPpmkoYfC0p5KS6v69/AozcnfjiqLipqzGSd6zMTL5Qta/3SLsLedSj+qvz/QGuUeEk50C3IN8q udBAxHno1xfALFabv0x+ATW/VtYlRiGsgzLmS9nigjqPbEcGeiRo7fjNh2YQt26qhS03Sa46UIS +rWzHpOsi1gKfsXC6ceeKbGRkkFObVxYlbZsHkJ0g6AHgUlW/335SwrkRQoFJrdqxCc8OtfPzu+ zh8tFulJMISMWCrdT5QejEyvzLmAXOptS9fN56/JioNdiiHxX9cU6zcNhsCOHy1rnn0Ie2j3FpR QW+9UvW8wQGsnj97HRCHicBh8NweAoy00MGQ9/vhuLlDRQgLNlT8A== X-Received: by 2002:a05:6830:4888:b0:7e9:cdf6:230d with SMTP id 46e09a7af769-7eda154706fmr1996146a34.24.1784309669083; Fri, 17 Jul 2026 10:34:29 -0700 (PDT) Received: from [127.0.1.1] (174-29-11-8.hlrn.qwest.net. [174.29.11.8]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7edad965130sm1677212a34.11.2026.07.17.10.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 10:34:28 -0700 (PDT) From: James Hilliard Date: Fri, 17 Jul 2026 11:33:58 -0600 Subject: [PATCH v2 2/3] mtd: rawnand: sunxi: describe tADL and tWHR delays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-submit-sunxi-nand-h6-h616-timings-v2-2-225515107640@gmail.com> References: <20260717-submit-sunxi-nand-h6-h616-timings-v2-0-225515107640@gmail.com> In-Reply-To: <20260717-submit-sunxi-nand-h6-h616-timings-v2-0-225515107640@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Genoud Cc: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The tADL and tWHR timing fields use four encoded delays, but the driver currently derives their values with a shift. This hides the actual controller timing characteristics and lets the clock solver select a 32-cycle delay that the fields cannot encode. Describe the legacy 7, 15, 23 and 31 cycle thresholds explicitly and use the tables for both clock selection and field lookup. This prepares the driver for controllers with different encodings. Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/sunxi_nand.c | 30 ++++++++++++++++++++---------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index d12cbb3c813c..791f495f6e82 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -242,6 +242,8 @@ struct sunxi_nand_hw_ecc { /* Delay arrays contain internal NDFC clock cycles for field values 0 to 3= . */ struct sunxi_nfc_timings { s32 tWB[SUNXI_NFC_TIMING_STEPS]; + s32 tADL[SUNXI_NFC_TIMING_STEPS]; + s32 tWHR[SUNXI_NFC_TIMING_STEPS]; s32 tRHW[SUNXI_NFC_TIMING_STEPS]; }; =20 @@ -1679,6 +1681,8 @@ static int sunxi_nfc_hw_ecc_write_oob(struct nand_chi= p *nand, int page) =20 static const struct sunxi_nfc_timings sun4i_a10_nfc_timings =3D { .tWB =3D { 6, 12, 16, 20 }, + .tADL =3D { 7, 15, 23, 31 }, + .tWHR =3D { 7, 15, 23, 31 }, .tRHW =3D { 4, 8, 12, 20 }, }; =20 @@ -1781,11 +1785,15 @@ static int sunxi_nfc_setup_interface(struct nand_ch= ip *nand, int csline, min_clk_period =3D DIV_ROUND_UP(timings->tWB_max, nfc_timings->tWB[SUNXI_NFC_TIMING_STEPS - 1]); =20 - if (timings->tADL_min > (min_clk_period * 32)) - min_clk_period =3D DIV_ROUND_UP(timings->tADL_min, 32); + if (timings->tADL_min > + (min_clk_period * nfc_timings->tADL[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tADL_min, + nfc_timings->tADL[SUNXI_NFC_TIMING_STEPS - 1]); =20 - if (timings->tWHR_min > (min_clk_period * 32)) - min_clk_period =3D DIV_ROUND_UP(timings->tWHR_min, 32); + if (timings->tWHR_min > + (min_clk_period * nfc_timings->tWHR[SUNXI_NFC_TIMING_STEPS - 1])) + min_clk_period =3D DIV_ROUND_UP(timings->tWHR_min, + nfc_timings->tWHR[SUNXI_NFC_TIMING_STEPS - 1]); =20 if (timings->tRHW_min > (min_clk_period * nfc_timings->tRHW[SUNXI_NFC_TIMING_STEPS - 1])) @@ -1813,16 +1821,18 @@ static int sunxi_nfc_setup_interface(struct nand_ch= ip *nand, int csline, return tWB; } =20 - tADL =3D DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; - if (tADL > 3) { + tADL =3D sunxi_nand_lookup_timing(nfc_timings->tADL, + timings->tADL_min, min_clk_period); + if (tADL < 0) { dev_err(nfc->dev, "unsupported tADL\n"); - return -EINVAL; + return tADL; } =20 - tWHR =3D DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; - if (tWHR > 3) { + tWHR =3D sunxi_nand_lookup_timing(nfc_timings->tWHR, + timings->tWHR_min, min_clk_period); + if (tWHR < 0) { dev_err(nfc->dev, "unsupported tWHR\n"); - return -EINVAL; + return tWHR; } =20 tRHW =3D sunxi_nand_lookup_timing(nfc_timings->tRHW, timings->tRHW_min, --=20 2.53.0 From nobody Sat Jul 25 04:56:32 2026 Received: from mail-ot1-f53.google.com (mail-ot1-f53.google.com [209.85.210.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 986E23EBF04 for ; Fri, 17 Jul 2026 17:34:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784309675; cv=none; b=Vzh2ZnFkjACbU8MUuFRDCXDXHiWoPeMKXJ48rnEpQWnTXsVIgLxJ1VwhcBfmQZimUFperlsFBmzOYDuZm6DrjKuuvLrRnSZplG9cZFHQyWKzdCg9wSNh3NDlTYGAsGkqrREl2GYDJPVbw3h7TVcnfVV0/6r6abRBO/VneSy5cP4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784309675; c=relaxed/simple; bh=cKHutGHLndJN3BZmJco0fGWbxTiby9/tAM3iiXN6y5I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rujft+pezfXf6dQQWiGUp8JuIs36MRlWeBowV8NwyKdbS++q6/6tiCy/0eFS3R3Bn4eoDNHKyXP1Ss+1MovJ7GdCEOf0AU5qAdHCy+sNXxOX7Iypa7mb11XzB2d8KUJJ+uZGNJfZyvRKKUUQxdjJTm0B/VQzr/ZpI+cHeQaFw+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=S8xWwyDV; arc=none smtp.client-ip=209.85.210.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="S8xWwyDV" Received: by mail-ot1-f53.google.com with SMTP id 46e09a7af769-7e9ef94c0e2so2169861a34.3 for ; Fri, 17 Jul 2026 10:34:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784309671; x=1784914471; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=sBTwbiP2C8OFdHLB83ZBc1RdHRd7b7uHmQhCjRYWMAk=; b=S8xWwyDVeNH23aiNVLKclRS+3cjZSmuPAVL82ELDh6+7E4F2SlON+Kywpv00eYeNjg NH2RwNb8eHx9A/YUr6F+Bi0wKspdxI9DXwNv7D7+AZCsiKUt2qdOpdGZeWSouaAQ3xV0 7gmAC3uGyluh/FU91CAKkPO4RpXFECwovrP9fDXHXg03kqEe0LJenUYEbJa4Nu3cVS7L oBQhRftIm0qfoRT6m21BJ6SC2g+3Vj3HzAYhw44XCLIeQ+Q2clBSiyXdPFqyqweUtc91 pt28uOItCMHjeRtMH4CVVQnncdtakEiY01sVqhn80c0Q7JjIPzVmmegp+ne+unNPe9HE 333g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784309671; x=1784914471; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=sBTwbiP2C8OFdHLB83ZBc1RdHRd7b7uHmQhCjRYWMAk=; b=QlYaMm6TsS6ZTEZTknz+Wc9ocdNe7oDZO7uYXUBP+XkK4rH1DFNtEUo5ESpIXmAtCX JHswf/xTht7p+GH49VMUN8GCcX0KB6496J2ReEA/N1/jNe/pAFvyAGjctaipDUIOI46f LWF/RtGpgViaQLNnYdbqY1+1y7TRM01rSLY+Illts9HDniDrCkqLYkuvbzma+ixRf9Or I/0Rve65upwGmzFYQmrA3f9pouikfQHLpqhMrGEcZLhl62PJKAqm3i9N5Ttgo7Km3cfU E24WNJnBsid0stL3D2mvO6PtPVhP1qhlNX6Tu0jgt0eYjPXvB88UZtm0LXkm2PO4Q00i J5sA== X-Forwarded-Encrypted: i=1; AHgh+RqkSvx6U1StSffbvp/rCsIUrj7/r40/lArPKgyzwCxGZY6wHrh1Ef6SPUgUT9tjD2zp/f2j2YLFCU78y64=@vger.kernel.org X-Gm-Message-State: AOJu0YwCJwc3xZF0lnifIPPuOY0CEdWSA/JDsYy2/d7sf3ajb9jRl3e/ Mgg24ve5tiRyBp5/nOYTE0QtweGhBwUFBIXkcfiV6RQ9qqk4MV9TLprV X-Gm-Gg: AfdE7cm9tMpCzl9OnswzKj67uQ3bnmFcq4JNJWg3OPa/LRrKs4t2wMfJ0TtJpDV/N6h jHJzXvz/HmZcQwGZmcGdY2JncpCruWKnUc8t9IkbDZNonrbPAtnSRXe6RSzzzDapQDs4HHyn7vD x6C71hf2yhx8KZhV8l9gygOkUP7GN7JOgsreoeCgd3EKoP53NuRHUqayrHiEDGlwoq9DZ7+7PvL +iYCVkzsGxNYMHIpKR+Z2mbdO2Vh1htxE2InCiJ+rbu/t/2tCr/kQry8MySGv2Al+narAsbCYti DKMxQHpTLHvbgpdgipf3SowAwInO8NbNHxkltB/ifPB0ZLlCP/fsXC3IKBZqjdU4SU9kUfg4PtN DMuLTk3nuIBKxcv8KcFURJSUcfo5XXd4X38upm9AGLEIlgIt23cbE133bhmUrtc8xvu80vMz0MN 1p/+lMyodZwcOu919jac44HBMu9+VvNI+2xY4eaB0j7S4Ccq/D8XfGlFg/ASYdixNE+NygBiNf5 YGglhvp3izlKmyKM/r8ot+ilZ7LzVcjGZrZgFvc6YkaUXwcTkIZKA== X-Received: by 2002:a05:6830:2a0e:b0:7e7:571:114e with SMTP id 46e09a7af769-7eda08eb88cmr1835909a34.20.1784309671288; Fri, 17 Jul 2026 10:34:31 -0700 (PDT) Received: from [127.0.1.1] (174-29-11-8.hlrn.qwest.net. [174.29.11.8]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7edad965130sm1677212a34.11.2026.07.17.10.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 10:34:29 -0700 (PDT) From: James Hilliard Date: Fri, 17 Jul 2026 11:33:59 -0600 Subject: [PATCH v2 3/3] mtd: rawnand: sunxi: fix H6/H616 controller timings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-submit-sunxi-nand-h6-h616-timings-v2-3-225515107640@gmail.com> References: <20260717-submit-sunxi-nand-h6-h616-timings-v2-0-225515107640@gmail.com> In-Reply-To: <20260717-submit-sunxi-nand-h6-h616-timings-v2-0-225515107640@gmail.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Richard Genoud Cc: linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard , stable@vger.kernel.org X-Mailer: b4 0.15.2 The NAND timing calculation assumes that command and address setup and hold intervals T1-T4, T7 and T11 each take one controller clock. It also uses the original A10 delay encodings for tWB, tADL, tWHR and tRHW. The H6/H616 NDFC defines the setup and hold intervals as two internal clock cycles and uses different delay encodings. Add the H616 timing characteristics and select them through the controller capability data so the clock solver and timing fields match the hardware. Fixes: 88fd4e4deae8 ("mtd: rawnand: sunxi: Add support for H616 nand contro= ller") Cc: stable@vger.kernel.org Signed-off-by: James Hilliard --- drivers/mtd/nand/raw/sunxi_nand.c | 49 ++++++++++++++++++++++++++++-------= ---- 1 file changed, 36 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/nand/raw/sunxi_nand.c b/drivers/mtd/nand/raw/sunxi= _nand.c index 791f495f6e82..3d91533a9f13 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.c +++ b/drivers/mtd/nand/raw/sunxi_nand.c @@ -241,6 +241,8 @@ struct sunxi_nand_hw_ecc { =20 /* Delay arrays contain internal NDFC clock cycles for field values 0 to 3= . */ struct sunxi_nfc_timings { + /* Internal clock cycles used by T1-T4, T7 and T11. */ + u8 setup_cycles; s32 tWB[SUNXI_NFC_TIMING_STEPS]; s32 tADL[SUNXI_NFC_TIMING_STEPS]; s32 tWHR[SUNXI_NFC_TIMING_STEPS]; @@ -1680,12 +1682,21 @@ static int sunxi_nfc_hw_ecc_write_oob(struct nand_c= hip *nand, int page) } =20 static const struct sunxi_nfc_timings sun4i_a10_nfc_timings =3D { + .setup_cycles =3D 1, .tWB =3D { 6, 12, 16, 20 }, .tADL =3D { 7, 15, 23, 31 }, .tWHR =3D { 7, 15, 23, 31 }, .tRHW =3D { 4, 8, 12, 20 }, }; =20 +static const struct sunxi_nfc_timings sun50i_h616_nfc_timings =3D { + .setup_cycles =3D 2, + .tWB =3D { 28, 44, 60, 76 }, + .tADL =3D { 0, 12, 28, 44 }, + .tWHR =3D { 0, 12, 28, 44 }, + .tRHW =3D { 8, 24, 40, 56 }, +}; + static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 dur= ation, u32 clk_period) { @@ -1720,20 +1731,28 @@ static int sunxi_nfc_setup_interface(struct nand_ch= ip *nand, int csline, return -ENOTSUPP; =20 /* T1 <=3D> tCLS */ - if (timings->tCLS_min > min_clk_period) - min_clk_period =3D timings->tCLS_min; + if (timings->tCLS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCLS_min, + nfc_timings->setup_cycles); =20 /* T2 <=3D> tCLH */ - if (timings->tCLH_min > min_clk_period) - min_clk_period =3D timings->tCLH_min; + if (timings->tCLH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCLH_min, + nfc_timings->setup_cycles); =20 /* T3 <=3D> tCS */ - if (timings->tCS_min > min_clk_period) - min_clk_period =3D timings->tCS_min; + if (timings->tCS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCS_min, + nfc_timings->setup_cycles); =20 /* T4 <=3D> tCH */ - if (timings->tCH_min > min_clk_period) - min_clk_period =3D timings->tCH_min; + if (timings->tCH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tCH_min, + nfc_timings->setup_cycles); =20 /* T5 <=3D> tWP */ if (timings->tWP_min > min_clk_period) @@ -1744,8 +1763,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, min_clk_period =3D timings->tWH_min; =20 /* T7 <=3D> tALS */ - if (timings->tALS_min > min_clk_period) - min_clk_period =3D timings->tALS_min; + if (timings->tALS_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tALS_min, + nfc_timings->setup_cycles); =20 /* T8 <=3D> tDS */ if (timings->tDS_min > min_clk_period) @@ -1760,8 +1781,10 @@ static int sunxi_nfc_setup_interface(struct nand_chi= p *nand, int csline, min_clk_period =3D DIV_ROUND_UP(timings->tRR_min, 3); =20 /* T11 <=3D> tALH */ - if (timings->tALH_min > min_clk_period) - min_clk_period =3D timings->tALH_min; + if (timings->tALH_min > + min_clk_period * nfc_timings->setup_cycles) + min_clk_period =3D DIV_ROUND_UP(timings->tALH_min, + nfc_timings->setup_cycles); =20 /* T12 <=3D> tRP */ if (timings->tRP_min > min_clk_period) @@ -2670,7 +2693,7 @@ static const struct sunxi_nfc_caps sunxi_nfc_h616_cap= s =3D { .nuser_data_tab =3D ARRAY_SIZE(sunxi_user_data_len_h6), .max_ecc_steps =3D 32, .sram_size =3D 8192, - .timings =3D &sun4i_a10_nfc_timings, + .timings =3D &sun50i_h616_nfc_timings, }; =20 static const struct of_device_id sunxi_nfc_ids[] =3D { --=20 2.53.0