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Fri, 17 Jul 2026 06:34:16 -0700 (PDT) From: Luca Weiss Date: Fri, 17 Jul 2026 15:33:03 +0200 Subject: [PATCH v2 1/2] dt-bindings: interconnect: OSM L3: Document Milos OSM L3 compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-milos-cpu-opp-v2-1-428813fafd52@fairphone.com> References: <20260717-milos-cpu-opp-v2-0-428813fafd52@fairphone.com> In-Reply-To: <20260717-milos-cpu-opp-v2-0-428813fafd52@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784295239; l=893; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=HFSTrk43zyzNsRY27xvVNkH801KFPO7/o86KOmtZ658=; b=/t1sZp8Zx+PC4pDijJkMxs119lQoymRHzjhpNhzRRiFpi0uwSLJpXkz/a+ta6tM0XuibepT7N MYF66BCUTRiD4et4OkbzF1uWI0FnWLHu1kL5k7/8Em3RM//kDbGCyr8 X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Document the OSM L3 found in the Qualcomm Milos SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yam= l b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index 41b9f758bf8b..17690ff34489 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -29,6 +29,7 @@ properties: - items: - enum: - qcom,eliza-epss-l3 + - qcom,milos-epss-l3 - qcom,sa8775p-epss-l3 - qcom,sc7280-epss-l3 - qcom,sc8280xp-epss-l3 --=20 2.55.0 From nobody Sat Jul 25 05:18:23 2026 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7357923ABA7 for ; Fri, 17 Jul 2026 13:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 17 Jul 2026 06:34:17 -0700 (PDT) Received: from [172.18.170.139] ([185.104.138.147]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f63e49ab8sm4361547f8f.5.2026.07.17.06.34.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Jul 2026 06:34:17 -0700 (PDT) From: Luca Weiss Date: Fri, 17 Jul 2026 15:33:04 +0200 Subject: [PATCH v2 2/2] arm64: dts: qcom: milos: add CPU OPP table with DDR & L3 bandwidths Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-milos-cpu-opp-v2-2-428813fafd52@fairphone.com> References: <20260717-milos-cpu-opp-v2-0-428813fafd52@fairphone.com> In-Reply-To: <20260717-milos-cpu-opp-v2-0-428813fafd52@fairphone.com> To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784295239; l=12661; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=C198r3gCqIY/J6Fr9Vk6dgw0/uX+Jq8YQlIxFo6EDYI=; b=J5h8jexeERNkt8ITTPhYzqpmuvlh1tfP2Wi7h6vmcTY9sx1EnZ2guiaf4+WuvqHRmdbTJ++am C5KP8pPZJxOBVG7hWNlJkrng9cyShmlAiIpYhKSbSBW72A58YQk5yDt X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add the OSC L3 Cache controller node, interconnect entry for each CPU, with 2 different paths (CPU to DDR, L3 Cache from CPU to DDR interface), and add the OPP tables for each CPU clusters (cpu0-3, cpu4-6 & cpu7) to permit scaling the DDR and L3 cache frequency by aggregating bandwidth requests of all CPU core with reference to the current OPP they are configured in by the LMH/EPSS hardware. The effect is a proper caches & DDR frequency scaling when CPU cores change frequency. The OPP tables were built using the downstream memlat ddr & l3 tables for each cluster type with the actual EPSS cpufreq LUT tables from running devices. Note, that higher frequencies than SM7635 are available on QCS6690, those have been added here as far as possible but may not be fully complete. Additional OPPs may need to be added for that SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/milos.dtsi | 344 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 344 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 8c9232988953..974afd7a582e 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,13 @@ cpu0: cpu@0 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_0: l2-cache { @@ -98,6 +106,13 @@ cpu1: cpu@100 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; }; =20 @@ -118,6 +133,13 @@ cpu2: cpu@200 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_2: l2-cache { @@ -145,6 +167,13 @@ cpu3: cpu@300 { =20 qcom,freq-domain =3D <&cpufreq_hw 0>; =20 + operating-points-v2 =3D <&cpu0_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; }; =20 @@ -165,6 +194,13 @@ cpu4: cpu@400 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + operating-points-v2 =3D <&cpu4_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_4: l2-cache { @@ -192,6 +228,13 @@ cpu5: cpu@500 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + operating-points-v2 =3D <&cpu4_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_5: l2-cache { @@ -219,6 +262,13 @@ cpu6: cpu@600 { =20 qcom,freq-domain =3D <&cpufreq_hw 1>; =20 + operating-points-v2 =3D <&cpu4_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_6: l2-cache { @@ -246,6 +296,13 @@ cpu7: cpu@700 { =20 qcom,freq-domain =3D <&cpufreq_hw 2>; =20 + operating-points-v2 =3D <&cpu7_opp_table>; + + interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, + <&epss_l3 MASTER_EPSS_L3_APPS + &epss_l3 SLAVE_EPSS_L3_SHARED>; + #cooling-cells =3D <2>; =20 l2_7: l2-cache { @@ -394,6 +451,281 @@ memory@0 { reg =3D <0 0 0 0>; }; =20 + cpu0_opp_table: opp-table-cpu0 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-441600000 { + opp-hz =3D /bits/ 64 <441600000>; + opp-peak-kBps =3D <(547000 * 4) (364800 * 32)>; + }; + + opp-595200000 { + opp-hz =3D /bits/ 64 <595200000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(547000 * 4) (710400 * 32)>; + }; + + opp-902400000 { + opp-hz =3D /bits/ 64 <902400000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 32)>; + }; + + opp-1017600000 { + opp-hz =3D /bits/ 64 <1017600000>; + opp-peak-kBps =3D <(547000 * 4) (998400 * 32)>; + }; + + opp-1113600000 { + opp-hz =3D /bits/ 64 <1113600000>; + opp-peak-kBps =3D <(547000 * 4) (998400 * 32)>; + }; + + opp-1228800000 { + opp-hz =3D /bits/ 64 <1228800000>; + opp-peak-kBps =3D <(768000 * 4) (1094400 * 32)>; + }; + + opp-1344000000 { + opp-hz =3D /bits/ 64 <1344000000>; + opp-peak-kBps =3D <(768000 * 4) (1209600 * 32)>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + opp-peak-kBps =3D <(768000 * 4) (1363200 * 32)>; + }; + + opp-1593600000 { + opp-hz =3D /bits/ 64 <1593600000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1363200 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1497600 * 32)>; + }; + + opp-1804800000 { + opp-hz =3D /bits/ 64 <1804800000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1516800 * 32)>; + }; + + opp-2054400000 { + opp-hz =3D /bits/ 64 <2054400000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1804800 * 32)>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-peak-kBps =3D <(547000 * 4) (364800 * 32)>; + }; + + opp-633600000 { + opp-hz =3D /bits/ 64 <633600000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-940800000 { + opp-hz =3D /bits/ 64 <940800000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-1056000000 { + opp-hz =3D /bits/ 64 <1056000000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (710400 * 32)>; + }; + + opp-1190400000 { + opp-hz =3D /bits/ 64 <1190400000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (710400 * 32)>; + }; + + opp-1286400000 { + opp-hz =3D /bits/ 64 <1286400000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (902400 * 32)>; + }; + + opp-1401600000 { + opp-hz =3D /bits/ 64 <1401600000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 32)>; + }; + + opp-1497600000 { + opp-hz =3D /bits/ 64 <1497600000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 32)>; + }; + + opp-1612800000 { + opp-hz =3D /bits/ 64 <1612800000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 1555000 */ + opp-peak-kBps =3D <(1555000 * 4) (1363200 * 32)>; + }; + + opp-1708800000 { + opp-hz =3D /bits/ 64 <1708800000>; + opp-peak-kBps =3D <(1708000 * 4) (1363200 * 32)>; + }; + + opp-1824000000 { + opp-hz =3D /bits/ 64 <1824000000>; + opp-peak-kBps =3D <(1708000 * 4) (1497600 * 32)>; + }; + + opp-1920000000 { + opp-hz =3D /bits/ 64 <1920000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1497600 * 32)>; + }; + + opp-2016000000 { + opp-hz =3D /bits/ 64 <2016000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1497600 * 32)>; + }; + + opp-2073600000 { + opp-hz =3D /bits/ 64 <2073600000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1497600 * 32)>; + }; + + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1516800 * 32)>; + }; + + opp-2400000000 { + opp-hz =3D /bits/ 64 <2400000000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1516800 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1804800 * 32)>; + }; + }; + + cpu7_opp_table: opp-table-cpu7 { + compatible =3D "operating-points-v2"; + opp-shared; + + opp-480000000 { + opp-hz =3D /bits/ 64 <480000000>; + opp-peak-kBps =3D <(547000 * 4) (364800 * 32)>; + }; + + opp-633600000 { + opp-hz =3D /bits/ 64 <633600000>; + opp-peak-kBps =3D <(547000 * 4) (556800 * 32)>; + }; + + opp-787200000 { + opp-hz =3D /bits/ 64 <787200000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 32)>; + }; + + opp-960000000 { + opp-hz =3D /bits/ 64 <960000000>; + opp-peak-kBps =3D <(547000 * 4) (806400 * 32)>; + }; + + opp-1094400000 { + opp-hz =3D /bits/ 64 <1094400000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (998400 * 32)>; + }; + + opp-1209600000 { + opp-hz =3D /bits/ 64 <1209600000>; + /* TODO: ddr4 =3D 1017000, ddr5 =3D 768000 */ + opp-peak-kBps =3D <(768000 * 4) (998400 * 32)>; + }; + + opp-1324800000 { + opp-hz =3D /bits/ 64 <1324800000>; + opp-peak-kBps =3D <(1555000 * 4) (998400 * 32)>; + }; + + opp-1459200000 { + opp-hz =3D /bits/ 64 <1459200000>; + opp-peak-kBps =3D <(1555000 * 4) (1209600 * 32)>; + }; + + opp-1651200000 { + opp-hz =3D /bits/ 64 <1651200000>; + opp-peak-kBps =3D <(1708000 * 4) (1209600 * 32)>; + }; + + opp-1766400000 { + opp-hz =3D /bits/ 64 <1766400000>; + /* TODO: ddr4 =3D 1708000, ddr5 =3D 2092000 */ + opp-peak-kBps =3D <(2092000 * 4) (1363200 * 32)>; + }; + + opp-1900800000 { + opp-hz =3D /bits/ 64 <1900800000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1497600 * 32)>; + }; + + opp-2208000000 { + opp-hz =3D /bits/ 64 <2208000000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1497600 * 32)>; + }; + + opp-2304000000 { + opp-hz =3D /bits/ 64 <2304000000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1516800 * 32)>; + }; + + opp-2496000000 { + opp-hz =3D /bits/ 64 <2496000000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1516800 * 32)>; + }; + + opp-2707200000 { + opp-hz =3D /bits/ 64 <2707200000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1804800 * 32)>; + }; + + opp-2918400000 { + opp-hz =3D /bits/ 64 <2918400000>; + /* TODO: ddr4 =3D 2092000, ddr5 =3D 3196000 */ + opp-peak-kBps =3D <(3196000 * 4) (1804800 * 32)>; + }; + }; + pmu-a520 { compatible =3D "arm,cortex-a520-pmu"; interrupts =3D ; @@ -2639,6 +2971,18 @@ rpmhpd_opp_turbo_l1: opp-416 { }; }; =20 + epss_l3: interconnect@17d90000 { + compatible =3D "qcom,milos-epss-l3", "qcom,epss-l3"; + reg =3D <0x0 0x17d90000 0x0 0x1000>; + + clocks =3D <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_GPLL0>; + clock-names =3D "xo", + "alternate"; + + #interconnect-cells =3D <1>; + }; + cpufreq_hw: cpufreq@17d91000 { compatible =3D "qcom,milos-cpufreq-epss", "qcom,cpufreq-epss"; reg =3D <0x0 0x17d91000 0x0 0x1000>, --=20 2.55.0