From nobody Sat Jul 25 05:59:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C65537997E; Fri, 17 Jul 2026 07:49:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784274578; cv=none; b=nEZb0TyvEwAWWNXc/b8S2vX9PKJ6P+JXsXHvxk7/lki5G186Wiqmdpe2TgVeMrtN5FqF6feNEYFgxppmM6FYF3KPCf2c3IjoZDbkbN/KxJvfH+Pjk45c9sRWGl2mmILT/tFLSAbVBvVEJlUpmwxp4FTYW783Ey2eMBVuTjqReQ0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784274578; c=relaxed/simple; bh=kH1x/C+bNVBFlqTXRh62APgCks1TYJKRNSlv2U2wXio=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k55EW/fJLdrAMbLN4DPf/eA92lW+Q3XmbUlP9b1l0hkSsH1TN5OEF6i34Q+sDd8A9gFR7qcU09Qxld5eLK4U1dbDW5qrB14WUcLCFuD1DxJzeHC1YD+K+6o+SBrbHWJaIc/O9/DgfZ5R8Y60/arVy0Rt1vAOCH+7YREuYGmQxTo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SZn+1La8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SZn+1La8" Received: by smtp.kernel.org (Postfix) with ESMTPS id 879C8C2BCB8; Fri, 17 Jul 2026 07:49:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784274577; bh=kH1x/C+bNVBFlqTXRh62APgCks1TYJKRNSlv2U2wXio=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=SZn+1La8IZHMj/F+Hft3XimmAhNKNBbBpY7btB2nCkYzh5uASuYLZCLE0ENd+fKFM hLCcGPga89ooNFyPAyyJZRrmKSWi44Erww+XM0IOqA+KgHfrKmlVHeDmsDarY2jS3g acI83Xe7Vfl5sYCeUa/+WoJuMZVc1WuhM5+RwZYK6ZmsFgbHHnkWl3hHRr1ty3pY0P AAE2g/LLq0uTWmY3UC+deytZfXFP58pRC0XTG6KdS/ESDzb8OGc8cdFT5XTKKOxpEl TkfeEdxImARuwBu9QAnvwjVF7Q/78L14vJWDU7gdAkqLhqNVGX7X9YS5NruwMCds/i cUBw6dqwl25Nw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 67BB0C44514; Fri, 17 Jul 2026 07:49:37 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 17 Jul 2026 07:49:33 +0000 Subject: [PATCH 1/3] spi: dt-bindings: amlogic: spisg: Document A9-specific properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-a9-spisg-v1-1-2eeea77be19f@amlogic.com> References: <20260717-a9-spisg-v1-0-2eeea77be19f@amlogic.com> In-Reply-To: <20260717-a9-spisg-v1-0-2eeea77be19f@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784274574; l=2098; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=S01FdKqQU8iANSc5yRkrElydRThefyYyd4gl5octfjc=; b=RG0aRoS+AIlkg4WEA5oEP0heq1kmYDL6XWlS3kIBwjMtntWgPInjtakXqV/ijUzySpVddZLBU g1Na4VBY1l6CqcEd8EvWb2p+bXp+8rqZwcb9IglYC6vBAwyXTkrYxvV X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao Document the Amlogic A9 SPISG controller and its additional Device Tree properties. Add the "amlogic,a9-spisg" compatible string and define the A9-specific "amlogic,mo-idle-output" and "amlogic,word-gap" properties, which configure the MOSI idle output level and the inter-word gap, respectively. Signed-off-by: Xianwei Zhao --- .../devicetree/bindings/spi/amlogic,a4-spisg.yaml | 36 ++++++++++++++++++= +--- 1 file changed, 32 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml b/= Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml index 9bfb8089f7ea..7efdc748d566 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spisg.yaml @@ -11,12 +11,11 @@ maintainers: - Xianwei Zhao - Sunny Luo =20 -allOf: - - $ref: spi-controller.yaml# - properties: compatible: - const: amlogic,a4-spisg + enum: + - amlogic,a4-spisg + - amlogic,a9-spisg =20 reg: maxItems: 1 @@ -42,6 +41,35 @@ required: - clocks - clock-names =20 +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - amlogic,a9-spisg + then: + properties: + amlogic,mo-idle-output: + description: | + Controls the MOSI output level when the controller is idle. + + 0 - Drive MOSI low + 1 - Drive MOSI high + 2 - Follow the last transmitted bit + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 0 + + amlogic,word-gap: + description: | + Number of idle clock cycles inserted between consecutive SPI + words. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 1 + unevaluatedProperties: false =20 examples: --=20 2.52.0 From nobody Sat Jul 25 05:59:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C7FC37E5CF; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pcf9SKFD" Received: by smtp.kernel.org (Postfix) with ESMTPS id 99418C2BCF5; Fri, 17 Jul 2026 07:49:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784274577; bh=rVssC21U/QDQdBOXC2oY3s+Mk18yYKdEpNvdGVASwp8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=pcf9SKFDUGvghwUE45WVYABcY3UbLwA9v2oYGM4CFL3aPZ5aLP+6QZA/CyCmk8zNp tQGO7lJQxVciAPokKB0lzKqAT6kMI+mmsmZmzb2r1EbDIrzo0IA/9rEL8o9W+S9mx+ COHVCb7zqTzn5e8JVZWU4CaxncS/vX0vySA8rS+iMrMraQ8APCRKstwyCeJIY58U0p CA3WeX6pN9qpFfJ/vtpIOS1oIrCBXAXk5GcnlZDAssPIgLqUtmrChyGaDYpZGR6iDT zowMpwyj/NRDjWObkdX+cG1YzKKX9C6GMQXGYniz4fLGByiy+ZYlYwOQBU57NIM+dz IVEO9tfRCB4Sw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79D5FC44517; Fri, 17 Jul 2026 07:49:37 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 17 Jul 2026 07:49:34 +0000 Subject: [PATCH 2/3] spi: amlogic: spisg: Fix the incorrect keep_ss of the last descriptor Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-a9-spisg-v1-2-2eeea77be19f@amlogic.com> References: <20260717-a9-spisg-v1-0-2eeea77be19f@amlogic.com> In-Reply-To: <20260717-a9-spisg-v1-0-2eeea77be19f@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784274574; l=2503; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=jkQLA6xWlywdjSsQl2U+CAG0++S5LTk9ZPS6pBUGm6g=; b=PXxinu3SBPGoS2bj1k8oC2+9+s3J4vn0sOqvhp9OTs57NDUHxQWy83zsh+akV2RBOTmo/uy+x CdWXAERlkepCnMQ0BwMBb395YGijg+4eVICF+4dUXmcDsSyCXta20jx X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Sunny Luo The driver currently unconditionally clears CFG_KEEP_SS on the last descriptor, causing the last transfer's cs_change setting to be ignored. Record the cs_change value of the last SPI transfer and use it to program CFG_KEEP_SS on the final descriptor. When a null descriptor is inserted to implement the cs-hold delay, keep CFG_KEEP_SS set on the preceding transfer descriptor and apply the recorded value to the final descriptor instead. This ensures the controller handles chip select correctly for the last transfer regardless of whether a cs-hold delay is required. Fixes: cef9991e04ae ("spi: Add Amlogic SPISG driver") Signed-off-by: Sunny Luo Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index afc8af04638d..0f026d3e43e0 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -489,6 +489,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, struct spisg_descriptor_extra *exdescs, *exdesc; dma_addr_t descs_paddr; int desc_num =3D 1, descs_len; + bool last_xfer_keep_ss =3D false; u32 cs_hold_in_sclk =3D 0; int ret =3D -EIO; =20 @@ -529,9 +530,11 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup)); =20 /* calculate cs-hold delay with the last xfer speed */ - if (list_is_last(&xfer->transfer_list, &msg->transfers)) + if (list_is_last(&xfer->transfer_list, &msg->transfers)) { cs_hold_in_sclk =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_hold); + last_xfer_keep_ss =3D xfer->cs_change; + } =20 desc++; exdesc++; @@ -539,13 +542,17 @@ static int aml_spisg_transfer_one_message(struct spi_= controller *ctlr, xfer->effective_speed_hz); } =20 - if (cs_hold_in_sclk) + if (cs_hold_in_sclk) { /* additional null-descriptor to achieve the cs-hold delay */ aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk); - else desc--; + desc->cfg_bus |=3D FIELD_PREP(CFG_KEEP_SS, 1); + desc++; + } else { + desc--; + } =20 - desc->cfg_bus |=3D FIELD_PREP(CFG_KEEP_SS, 0); + FIELD_MODIFY(CFG_KEEP_SS, &desc->cfg_bus, last_xfer_keep_ss); desc->cfg_start |=3D FIELD_PREP(CFG_EOC, 1); =20 /* some tolerances */ --=20 2.52.0 From nobody Sat Jul 25 05:59:52 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C72E37DABD; Fri, 17 Jul 2026 07:49:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 17 Jul 2026 07:49:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784274577; bh=qS2DLzuRq1fyJA41MJOJ8kFpVv3gdzDCD3kTwkTmt6A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=eNeG6Ntf+UJgsZK9CAj3BQGtEF0EUB5NDYFX3KnQ5TLuIHznHjieVFYbkvWqgms7g AquXiV3RlHyla0/D0DLSqeSf0SUIybEiY7vUWUEiD/CNXXZn75wu4AJ322HQrJYTiy TCQBFu2ME/dfYG5voxbJD4d1VsQ4J/7uq7MNsiTLa/oaprhAv/pi9H8VJQlUspmHc1 EKMmqJPluf38SfsEfCHq3AaUSVpKxrs4yMPy231ws9vcGilm2ZXGwx/Y2GGu6BJp7b RT4Gkp6c9jckOX1WLO5H9am5PslcyUs8ZliBpm+UqJcUJqP2rY1xLhIt7CwUXuFTVR P/1z8mpDNLDVA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AFF8C44515; Fri, 17 Jul 2026 07:49:37 +0000 (UTC) From: Xianwei Zhao via B4 Relay Date: Fri, 17 Jul 2026 07:49:35 +0000 Subject: [PATCH 3/3] spi: amlogic: spisg: Add support for A9 controller features Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260717-a9-spisg-v1-3-2eeea77be19f@amlogic.com> References: <20260717-a9-spisg-v1-0-2eeea77be19f@amlogic.com> In-Reply-To: <20260717-a9-spisg-v1-0-2eeea77be19f@amlogic.com> To: Sunny Luo , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-amlogic@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Xianwei Zhao X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784274574; l=5993; i=xianwei.zhao@amlogic.com; s=20251216; h=from:subject:message-id; bh=hSBlHqyRKAFzXRe5Mipf9iWE55K2Qe+NrDF5i5K4r+4=; b=oJ1QsKwU7s3BAluM3mGKO9WRC4zRwLYDoY+4s6U5EPkqNgmGIe7vUcOeypBUE1oHw6hxR2dVa XfpSOOFoTCRA8vjc421OToQlLakawI22icz4mguovajuGe6u7QescAl X-Developer-Key: i=xianwei.zhao@amlogic.com; a=ed25519; pk=dWwxtWCxC6FHRurOmxEtr34SuBYU+WJowV/ZmRJ7H+k= X-Endpoint-Received: by B4 Relay for xianwei.zhao@amlogic.com/20251216 with auth_id=578 X-Original-From: Xianwei Zhao Reply-To: xianwei.zhao@amlogic.com From: Xianwei Zhao The Amlogic A9 SPISG controller extends the A4 controller with additional configuration options, including: - Extended CS setup timing - Hardware-controlled CS hold timing - MOSI idle output configuration - Configurable word gap Add SoC-specific capability data and configure these features when they are supported by the underlying hardware while keeping compatibility with existing A4 controllers. Signed-off-by: Xianwei Zhao --- drivers/spi/spi-amlogic-spisg.c | 65 +++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-amlogic-spisg.c b/drivers/spi/spi-amlogic-spis= g.c index 0f026d3e43e0..845eb81d483a 100644 --- a/drivers/spi/spi-amlogic-spisg.c +++ b/drivers/spi/spi-amlogic-spisg.c @@ -37,6 +37,12 @@ #define CFG_HW_POS BIT(6) /* start on vsync falling */ #define CFG_HW_NEG BIT(7) +#define CFG_WORD_GAP GENMASK(9, 8) +#define CFG_MO_IDLE_OUTPUT GENMASK(11, 10) +/* cs hold time in pclk */ +#define CFG_CS_HOLD GENMASK(26, 12) +/* high 4 bits of cs setup time in sclk */ +#define CFG_CS_SETUP_EXTEND GENMASK(30, 27) =20 #define SPISG_REG_CFG_START 0x08 #define CFG_BLOCK_NUM GENMASK(19, 0) @@ -143,6 +149,13 @@ struct spisg_descriptor_extra { int rx_ccsg_len; }; =20 +struct aml_spisg_data { + bool mo_idle_output_ctrl; + bool word_gap_ctrl; + bool cs_hold_ctrl; + bool cs_setup_extend_ctrl; +}; + struct spisg_device { struct spi_controller *controller; struct platform_device *pdev; @@ -152,6 +165,7 @@ struct spisg_device { struct clk *sclk; struct clk_div_table *tbl; struct completion completion; + const struct aml_spisg_data *data; u32 status; u32 speed_hz; u32 effective_speed_hz; @@ -483,6 +497,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, { struct spisg_device *spisg =3D spi_controller_get_devdata(ctlr); struct device *dev =3D &spisg->pdev->dev; + const struct aml_spisg_data *data =3D spisg->data; unsigned long long ms =3D 0; struct spi_transfer *xfer; struct spisg_descriptor *descs, *desc; @@ -491,6 +506,7 @@ static int aml_spisg_transfer_one_message(struct spi_co= ntroller *ctlr, int desc_num =3D 1, descs_len; bool last_xfer_keep_ss =3D false; u32 cs_hold_in_sclk =3D 0; + u32 val; int ret =3D -EIO; =20 if (!aml_spisg_sem_down_read(spisg)) { @@ -525,9 +541,17 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, } =20 /* calculate cs-setup delay with the first xfer speed */ - if (list_is_first(&xfer->transfer_list, &msg->transfers)) - desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, - spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup)); + if (list_is_first(&xfer->transfer_list, &msg->transfers)) { + val =3D spi_delay_to_sclk(xfer->effective_speed_hz, &msg->spi->cs_setup= ); + if (data && data->cs_setup_extend_ctrl) { + val =3D min_t(u32, 0xFF, val); + desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, val & 0xF); + FIELD_MODIFY(CFG_CS_SETUP_EXTEND, &spisg->cfg_spi, val >> 4); + } else { + val =3D min_t(u32, 0xF, val); + desc->cfg_bus |=3D FIELD_PREP(CFG_CS_SETUP, val); + } + } =20 /* calculate cs-hold delay with the last xfer speed */ if (list_is_last(&xfer->transfer_list, &msg->transfers)) { @@ -542,7 +566,12 @@ static int aml_spisg_transfer_one_message(struct spi_c= ontroller *ctlr, xfer->effective_speed_hz); } =20 - if (cs_hold_in_sclk) { + if (data && data->cs_hold_ctrl) { + cs_hold_in_sclk =3D cs_hold_in_sclk ? : 1; + val =3D cs_hold_in_sclk * (FIELD_GET(CFG_CLK_DIV, spisg->cfg_bus) + 1); + FIELD_MODIFY(CFG_CS_HOLD, &spisg->cfg_spi, val); + desc--; + } else if (cs_hold_in_sclk) { /* additional null-descriptor to achieve the cs-hold delay */ aml_spisg_setup_null_desc(spisg, desc, cs_hold_in_sclk); desc--; @@ -722,6 +751,7 @@ static int aml_spisg_probe(struct platform_device *pdev) struct spisg_device *spisg; struct device *dev =3D &pdev->dev; void __iomem *base; + u32 val =3D 0; int ret, irq; =20 const struct regmap_config aml_regmap_config =3D { @@ -740,6 +770,7 @@ static int aml_spisg_probe(struct platform_device *pdev) =20 spisg =3D spi_controller_get_devdata(ctlr); spisg->controller =3D ctlr; + spisg->data =3D (struct aml_spisg_data *)of_device_get_match_data(dev); =20 spisg->pdev =3D pdev; platform_set_drvdata(pdev, spisg); @@ -770,6 +801,21 @@ static int aml_spisg_probe(struct platform_device *pde= v) =20 spisg->cfg_spi =3D FIELD_PREP(CFG_SFLASH_WP, 1) | FIELD_PREP(CFG_SFLASH_HD, 1); + + if (spisg->data && spisg->data->mo_idle_output_ctrl) { + if (!of_property_read_u32(dev->of_node, "amlogic,mo-idle-output", &val)) + spisg->cfg_spi |=3D FIELD_PREP(CFG_MO_IDLE_OUTPUT, val); + else + spisg->cfg_spi |=3D FIELD_PREP(CFG_MO_IDLE_OUTPUT, 0); + } + + if (spisg->data && spisg->data->word_gap_ctrl) { + if (!of_property_read_u32(dev->of_node, "amlogic,word-gap", &val)) + spisg->cfg_spi |=3D FIELD_PREP(CFG_WORD_GAP, val); + else + spisg->cfg_spi |=3D FIELD_PREP(CFG_WORD_GAP, 1); + } + if (spi_controller_is_target(ctlr)) { spisg->cfg_spi |=3D FIELD_PREP(CFG_SLAVE_EN, 1); spisg->cfg_bus =3D FIELD_PREP(CFG_TX_TUNING, 0xf); @@ -856,6 +902,13 @@ static int spisg_resume_runtime(struct device *dev) return 0; } =20 +static const struct aml_spisg_data a9_spisg_data =3D { + .mo_idle_output_ctrl =3D true, + .word_gap_ctrl =3D true, + .cs_hold_ctrl =3D true, + .cs_setup_extend_ctrl =3D true, +}; + static const struct dev_pm_ops amlogic_spisg_pm_ops =3D { .runtime_suspend =3D spisg_suspend_runtime, .runtime_resume =3D spisg_resume_runtime, @@ -865,6 +918,10 @@ static const struct of_device_id amlogic_spisg_of_matc= h[] =3D { { .compatible =3D "amlogic,a4-spisg", }, + { + .compatible =3D "amlogic,a9-spisg", + .data =3D &a9_spisg_data, + }, =20 { /* sentinel */ } }; --=20 2.52.0