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[14.13.71.96]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf1055de44sm22917255ad.51.2026.07.16.10.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 10:17:53 -0700 (PDT) From: Akari Tsuyukusa To: Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Akari Tsuyukusa , Flora Fu , Alexandre Mergnat Cc: linux-pm@vger.kernel.org (open list:MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS), mfd@lists.linux.dev (open list:MULTIFUNCTION DEVICES (MFD)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 1/3] dt-bindings: soc: mediatek: pwrap: Add compatible for MT6589 SoC Date: Fri, 17 Jul 2026 02:17:31 +0900 Message-ID: <20260716171733.300885-2-akkun11.open@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260716171733.300885-1-akkun11.open@gmail.com> References: <20260716171733.300885-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string for MediaTek MT6589 PWRAP. Also update the description since MT6589 has pwrap bridge. Signed-off-by: Akari Tsuyukusa --- .../devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.= yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index e7c4a3984c60..a487ed39e6cb 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -19,8 +19,8 @@ description: =20 IP Pairing =20 - On MT8135 the pins of some SoC internal peripherals can be on the PMIC. - The signals of these pins are routed over the SPI bus using the pwrap + On MT6589 and MT8135, the pins of some SoC internal peripherals can be o= n the + PMIC. The signals of these pins are routed over the SPI bus using the pw= rap bridge. In the binding description below the properties needed for bridg= ing are marked with "IP Pairing". These are optional on SoCs which do not su= pport IP Pairing @@ -31,6 +31,7 @@ properties: - items: - enum: - mediatek,mt2701-pwrap + - mediatek,mt6589-pwrap - mediatek,mt6765-pwrap - mediatek,mt6779-pwrap - mediatek,mt6795-pwrap --=20 2.54.0 From nobody Mon Jul 27 18:58:42 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88EEF435532 for ; Thu, 16 Jul 2026 17:18:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784222289; cv=none; b=dQj7w/XxirNLB8YtmSvrH+feJnu2m4LWJY7CnZlnowNVTuyusdIQ6dDcZi62vd0HNdbWM68P8dhePJIzI1S7o3F97zpFZuVVVorUSnOEMOg9WgjT5nM1wEhV+8gQXZhb0Af1AZ/WT9rOvPbc3yAoKvKYJ35Up1KplqcRYx4tUNM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784222289; c=relaxed/simple; bh=Y8Yhg9LDZgOOn4IYBYFpDiXxdAtcDCdbUesWkE9/tns=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=reJTNVZTOf7wT1Y+PVN1aq699W9r4+is+Yzv95XvVJA7wGidrGumqQ6DadC0v7W6LAxmiclIN0X2jiz1Ve5VrpNSU3LvDByuaSzKrnDefUAFffI9CKuZj99WwB94iL/iqq5gS9MRZbSx5TaM+tNJIcEAC85U+89xtZz5gM/Khpo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=hCdB7emv; arc=none smtp.client-ip=209.85.214.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="hCdB7emv" Received: by mail-pl1-f176.google.com with SMTP id d9443c01a7336-2cac59f8b64so80970285ad.0 for ; Thu, 16 Jul 2026 10:18:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784222277; x=1784827077; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=x+VQUfT4E2jpzaVYfn1xTQo+PWwjs/hsb3t7kl1meuo=; b=hCdB7emv+75h4IkFh1xMx+pBtbjzjmnsR+CZnIl33l6AMh1Kga4EuQntgWs6bTNZsk 07eZprtW3kOQAg4y0WiCLa+/4HOuVC0mfvmTspbg/IT/0Ltu0xZwLnj3hNSinR/PJ63s KmtfLgmRAWsusaU2Li5fvO8/DokvmNh370EIiRDOa2gsMZpmQLnu15PFtAhHvZnnBzPZ brFwP3gg80TJhb/g9b2FoDIp/890dKtQmX/VOhFG2FvwJ7bihzVK47XobpkQr5YRErC2 40BbJcHaYVZLGzeCCZweOGxG+aTBU3dD/fr0akQS3wwn2+Q885uHwlKIla1c6naSNFUN X93Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784222277; x=1784827077; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=x+VQUfT4E2jpzaVYfn1xTQo+PWwjs/hsb3t7kl1meuo=; b=Ek/Kt0vzjEGaBeOB1H/SrrQUJRgpEZ4yiAf3WRR6eHH5DcE6JzNe/T7Ud+JY2hjmYf E7oTaeu1x5KrRmS0LZYLJ7gTZr04sdQlxwnaHKGJbQotGcXBGI5OkqhaP9MeUTsLSpx0 t2leX6i+o4ng8Pe4bVwHMFz85UQtbbMiFtB8rSbG/2j4Gt6tbwaKNA73v4C5WtguoKJq spp7UCM4JpPfWJHkxsYFkfFrwisLilMFvS+56fKvo6LNvS99ovD1CGT/BvJIDqnaOqZh TRMJPAJZUTZOKBHG53YQF1+ve0s1/zgcThLD3xQNMoF5QjlrNvawon+iD+oLpWlQCyKk pguw== X-Forwarded-Encrypted: i=1; AHgh+RpEFrJz0SM/itRc/fTPZjVm4m5MgGTdRvj6zlNy1QugSDZ7CK8+SLQPhBn47zRHhJAVRG39tkYiuM7+4oM=@vger.kernel.org X-Gm-Message-State: AOJu0YzCd/PqJ6u3TqbgLLkuVbjw08zwUNwkYo3oYqrWcf+x6pCKjCrb f1CpGACBPUdVLfB99ipQSdk3AG7hz943N1h95dWIQ/nV1qHS+9U+gv+U X-Gm-Gg: AfdE7cm43aoX4yXinZqHZ5ZtjHwiGqPmUVXc/oonc7AqTE3CJLl/ZNMw8Yzv5hjjlM6 d35FUolHOhJppYJuFc193mtvdD/kh1ZVAgj11gJQMGhC5b8sUSCdEQKRlM/1LXdWbto6vrSZODq lJDZKw9tZx60ZJRcYUROAeqZz4c+gdOt8MPZU8+ZmuHLkblYbVuyWIY8dKYq69FZXPX7TSIdbSF mSwvNO9YXgN6PVM7l/cMq8Hk5kq1RjRRXMN4q1SF9CGfmdNzJbingpZ520aCQRHF9932WFU1iHZ SvNdTR7YZfNW1/oYCYHvBrt3AHKuWZ7PQg/aRTiAJCtYV63isSZ/O4ujahIrbeXkAv8621LTUaR xvROaaZY2nyO0zeX+HAw3H1jgZgnA/N5BWB5N4iHdjIM6TuIeSh/jj/PCJ9pq4DXc3ezCpuupwK iz1Xz45/2SfHvmBb4MZTCpP6Ktf3L1CWOXIg== X-Received: by 2002:a17:902:da81:b0:2ca:e19c:986 with SMTP id d9443c01a7336-2cf03c7c756mr75109205ad.1.1784222276928; Thu, 16 Jul 2026 10:17:56 -0700 (PDT) Received: from buffalo-ssd (M014013071096.v4.enabler.ne.jp. [14.13.71.96]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf1055de44sm22917255ad.51.2026.07.16.10.17.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 10:17:56 -0700 (PDT) From: Akari Tsuyukusa To: Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Akari Tsuyukusa , Flora Fu , Alexandre Mergnat Cc: linux-pm@vger.kernel.org (open list:MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS), mfd@lists.linux.dev (open list:MULTIFUNCTION DEVICES (MFD)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 2/3] dt-bindings: mfd: mediatek: mt6397: add MT6320 compatible string Date: Fri, 17 Jul 2026 02:17:32 +0900 Message-ID: <20260716171733.300885-3-akkun11.open@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260716171733.300885-1-akkun11.open@gmail.com> References: <20260716171733.300885-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatible string for the MT6320 PMIC. Signed-off-by: Akari Tsuyukusa --- Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/D= ocumentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 3cbc0dc12c31..f2823338cccd 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -34,6 +34,7 @@ properties: compatible: oneOf: - enum: + - mediatek,mt6320 - mediatek,mt6323 - mediatek,mt6331 # "mediatek,mt6331" for PMIC MT6331 and MT6332. - mediatek,mt6328 --=20 2.54.0 From nobody Mon Jul 27 18:58:42 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA73A3B19D5 for ; Thu, 16 Jul 2026 17:18:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784222290; cv=none; b=XSOc410Q6ossv2yokBpqbw+vpU34cy8x5OdruqDu5tAzmV4WuW2C4gIN2sleU43LnmhbTmFyqG5je3A5fasu/w6TLQjdGoudmYZkh/WZYOjisCloiQSz8L5+vfJAC1gPJHOzDsbooU6RIs4d/pGU/xs+ucDwylSsItWRIjvrtK8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784222290; c=relaxed/simple; bh=iLUDkY4SFCq9gFI8/CTxjIMroozhOs4ZSJ3zk3UDbiw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iF1V9qzGQnVuutm0p1I+l+lTSSd1frk/5EFfHKdlFpsbp3g5EO+nnjS1nsoyDcyJZmjgC6Zm5mpcipBO4Q/L+nAzaW4y39Cq4IcWtsQLsY5w+u9Vxvwyfk5CKKB29xjvrvdhk8u3Ple/yVOnVvdOhxIUz/WoZ/15qZqwpsF4BhQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ZnNdha8v; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ZnNdha8v" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-2ceb096e675so63703355ad.0 for ; Thu, 16 Jul 2026 10:18:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784222280; x=1784827080; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=HFJ+p81BjdB00DrwvkVTq99s5PhB9C18F6cOkBhmFnM=; b=ZnNdha8vklW3lEkQeUdVLH0PU28uYrdakl5lfUx6ijzCKIf+v5s+UW7N3oWzQI1Pki oaPUuV5yy41t1OxB13rm7BUB/xuFlfC9Uaf49Jnjb6sAxarvpd8wCWVd7V13eXLyPaw0 /bCYJ3UH7CZXN23TGgN7FyWge4OhITe50JtL82gzQxdE66FnfSsKLvx2DcJhKzXB4pRP T18HDqfw8WyRWMzXdrX4wp6qCM2t77NQEwccWS3gxOIVCCsLHcZ5ApZs3dy0CP/FQNzk 5U425rkLEhvJ7sAKhaPyooqz6gvNDH+hiYLj44bNMuBhUYw27hQjhytX8Ta/C0xo/I77 iJPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784222280; x=1784827080; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=HFJ+p81BjdB00DrwvkVTq99s5PhB9C18F6cOkBhmFnM=; b=g9q/KseP4BDzqbEMSNjYJPKoWB1EBNdA07dLphxw45yJQjHDlJ98vkNq0O3UW0n3Z2 pwIFJfMi+xJisJiH5BsnnMIyxBU7hdvXa7LXqAyDUVKxN7GQAg3kCJDD35DhtpYmV0iC 2iTKzwgB+qRUXLivnvYBgn6xl0XTiEiCkU8iKiU9Yd0fIBhRIRTllJ6Px5SUeQuyb4RS 2v05b9HoEIzq+wFnrLUYj+Q5Pojrl71TNYjE6KKoNj5MXwDrCPC9bftcdO9C9qp+4Ax8 hlAfJ0SZ9hY9cf10haapHzLHpJ1b+HDi9HIQlURsfx3EXdD5lJq0d/lXDzG3jRHG5mOY OjfA== X-Forwarded-Encrypted: i=1; AHgh+RrncEahl1+xLA+vAKdbYW2uJ3rCTTD+DcklP95dudmUjPmciXqo3U67HL7BEOqSGIDAN2vclEXAn5uB2XI=@vger.kernel.org X-Gm-Message-State: AOJu0Yxd9fXYp9bPIgSmeQdtDvCP0he6CM3wuJ1r1wp/tRXEWmrL94yc NN9jnCmPv9xHNP9RBLSFidIIpSEfC5awAOtTwPFfnJ3MZ0xbKfMWYObd X-Gm-Gg: AfdE7cld7AKbBIeI6g5Su9lGiFRf0RxEzgrqd3weaVmCeivk2Nx5WqKDCWILkWwtaUV QhKHA52yMY/ikiTh4cmPX408/eKar1IN+jlUul+lqOKQhp0mRrCV4mGX0Hjpme0YTRDY57F2Gbw odpN7h2f9+bmAJlY7+lMdRrQahppUaegRWYeEOHdcdgp2psIgcfazxf2Cr71eDY2LvPb5GgmANn NRMt39/xNVcY5+GAqD/uN6TNToHR0eV1KLhPjNCVymtjpgGLpj1PKVf1olhF8HxrWfuZQf6UXTr ptlEqjGyLzFFrs2VhP4YbVFHgPiP2icluvpW1JmG1zRqHHcpZqXfb5lMtzTdOC3rgzQ+g2TWfo7 fJEJTo9cZLk8lOUgFS+VOeRLt9kXfd687achHwmEOVFndzjnET94f+ojK4U5rLJKIc7M3XUveG5 SFHOp1Jg43buPWkj5nRIJEoKgaDZaTeGerbg== X-Received: by 2002:a17:903:19ec:b0:2c2:be43:39bc with SMTP id d9443c01a7336-2cf03cef84dmr84481775ad.22.1784222280297; Thu, 16 Jul 2026 10:18:00 -0700 (PDT) Received: from buffalo-ssd (M014013071096.v4.enabler.ne.jp. [14.13.71.96]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2cf1055de44sm22917255ad.51.2026.07.16.10.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 10:17:59 -0700 (PDT) From: Akari Tsuyukusa To: Sen Chu , Sean Wang , Macpaul Lin , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Akari Tsuyukusa , Flora Fu , Alexandre Mergnat Cc: linux-pm@vger.kernel.org (open list:MEDIATEK BOARD LEVEL SHUTDOWN DRIVERS), mfd@lists.linux.dev (open list:MULTIFUNCTION DEVICES (MFD)), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list:ARM/Mediatek SoC support), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 3/3] soc: mediatek: pwrap: add MT6589 PWARP and MT6320 PMIC support Date: Fri, 17 Jul 2026 02:17:33 +0900 Message-ID: <20260716171733.300885-4-akkun11.open@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260716171733.300885-1-akkun11.open@gmail.com> References: <20260716171733.300885-1-akkun11.open@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for MediaTek MT6589 PWRAP and MT6320 PMIC which are used together. Since the PWRAP Bridge hardware on MT6589 is identical to the one on MT8135, refactor the existing register definitions: - Rename the MT8135-specific "PWRAP_MT8135_BRIDGE_" prefix to a generic "PWRAP_BRIDGE_" prefix to reflect that they are shared across SoCs. - Add the full set of PWRAP Bridge registers to match the hardware specification, rather than defining only a subset of them. Signed-off-by: Akari Tsuyukusa --- drivers/soc/mediatek/mtk-pmic-wrap.c | 292 +++++++++++++++++++++------ 1 file changed, 235 insertions(+), 57 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mt= k-pmic-wrap.c index 0bcd85826375..3a5b007d60f5 100644 --- a/drivers/soc/mediatek/mtk-pmic-wrap.c +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c @@ -17,15 +17,31 @@ #define PWRAP_POLL_DELAY_US 10 #define PWRAP_POLL_TIMEOUT_US 10000 =20 -#define PWRAP_MT8135_BRIDGE_IORD_ARB_EN 0x4 -#define PWRAP_MT8135_BRIDGE_WACS3_EN 0x10 -#define PWRAP_MT8135_BRIDGE_INIT_DONE3 0x14 -#define PWRAP_MT8135_BRIDGE_WACS4_EN 0x24 -#define PWRAP_MT8135_BRIDGE_INIT_DONE4 0x28 -#define PWRAP_MT8135_BRIDGE_INT_EN 0x38 -#define PWRAP_MT8135_BRIDGE_TIMER_EN 0x48 -#define PWRAP_MT8135_BRIDGE_WDT_UNIT 0x50 -#define PWRAP_MT8135_BRIDGE_WDT_SRC_EN 0x54 +/* MT6589 and MT8135 specific PWARP Bridge registers */ +#define PWRAP_BRIDGE_IARB_INIT 0x0 +#define PWRAP_BRIDGE_IORD_ARB_EN 0x4 +#define PWRAP_BRIDGE_IARB_STA0 0x8 +#define PWRAP_BRIDGE_IARB_STA1 0xc +#define PWRAP_BRIDGE_WACS3_EN 0x10 +#define PWRAP_BRIDGE_INIT_DONE3 0x14 +#define PWRAP_BRIDGE_WACS3_CMD 0x18 +#define PWRAP_BRIDGE_WACS3_RDATA 0x1c +#define PWRAP_BRIDGE_WACS3_VLDCLR 0x20 +#define PWRAP_BRIDGE_WACS4_EN 0x24 +#define PWRAP_BRIDGE_INIT_DONE4 0x28 +#define PWRAP_BRIDGE_WACS4_CMD 0x2c +#define PWRAP_BRIDGE_WACS4_RDATA 0x30 +#define PWRAP_BRIDGE_WACS4_VLDCLR 0x34 +#define PWRAP_BRIDGE_INT_EN 0x38 +#define PWRAP_BRIDGE_INT_FLG_RAW 0x3c +#define PWRAP_BRIDGE_INT_FLG 0x40 +#define PWRAP_BRIDGE_INT_CLR 0x44 +#define PWRAP_BRIDGE_TIMER_EN 0x48 +#define PWRAP_BRIDGE_TIMER_STA 0x4c +#define PWRAP_BRIDGE_WDT_UNIT 0x50 +#define PWRAP_BRIDGE_WDT_SRC_EN 0x54 +#define PWRAP_BRIDGE_WDT_FLG 0x58 +#define PWRAP_BRIDGE_DEBUG_INT_SEL 0x5c =20 /* macro for wrapper status */ #define PWRAP_GET_WACS_RDATA(x) (((x) >> 0) & 0x0000ffff) @@ -100,6 +116,24 @@ enum dew_regs { PWRAP_DEW_CIPHER_MODE, PWRAP_DEW_CIPHER_SWRST, =20 + /* MT6320 only regs */ + PWRAP_DEW_CIPHER_IV0, + PWRAP_DEW_CIPHER_IV1, + PWRAP_DEW_CIPHER_IV2, + PWRAP_DEW_CIPHER_IV3, + PWRAP_DEW_CIPHER_IV4, + PWRAP_DEW_CIPHER_IV5, + + /* MT6320 and MT6397 only regs */ + PWRAP_DEW_EVENT_OUT_EN, + PWRAP_DEW_EVENT_SRC_EN, + PWRAP_DEW_EVENT_SRC, + PWRAP_DEW_EVENT_FLAG, + PWRAP_DEW_MON_FLAG_SEL, + PWRAP_DEW_EVENT_TEST, + PWRAP_DEW_CIPHER_LOAD, + PWRAP_DEW_CIPHER_START, + /* MT6323 only regs */ PWRAP_DEW_CIPHER_EN, PWRAP_DEW_RDDMY_NO, @@ -142,16 +176,34 @@ enum dew_regs { PWRAP_DEW_RG_WDATA_MASK, PWRAP_DEW_RG_SPI_RECORD_CLR, PWRAP_DEW_RG_CMD_ALERT_CLR, +}; =20 - /* MT6397 only regs */ - PWRAP_DEW_EVENT_OUT_EN, - PWRAP_DEW_EVENT_SRC_EN, - PWRAP_DEW_EVENT_SRC, - PWRAP_DEW_EVENT_FLAG, - PWRAP_DEW_MON_FLAG_SEL, - PWRAP_DEW_EVENT_TEST, - PWRAP_DEW_CIPHER_LOAD, - PWRAP_DEW_CIPHER_START, +static const u32 mt6320_regs[] =3D { + [PWRAP_DEW_EVENT_OUT_EN] =3D 0x0000, + [PWRAP_DEW_DIO_EN] =3D 0x0002, + [PWRAP_DEW_EVENT_SRC_EN] =3D 0x0004, + [PWRAP_DEW_EVENT_SRC] =3D 0x0006, + [PWRAP_DEW_EVENT_FLAG] =3D 0x0008, + [PWRAP_DEW_READ_TEST] =3D 0x000a, + [PWRAP_DEW_WRITE_TEST] =3D 0x000c, + [PWRAP_DEW_CRC_EN] =3D 0x000e, + [PWRAP_DEW_CRC_VAL] =3D 0x0010, + [PWRAP_DEW_MON_GRP_SEL] =3D 0x0012, + [PWRAP_DEW_MON_FLAG_SEL] =3D 0x0014, + [PWRAP_DEW_EVENT_TEST] =3D 0x0016, + [PWRAP_DEW_CIPHER_KEY_SEL] =3D 0x0018, + [PWRAP_DEW_CIPHER_IV_SEL] =3D 0x001a, + [PWRAP_DEW_CIPHER_LOAD] =3D 0x001c, + [PWRAP_DEW_CIPHER_START] =3D 0x001e, + [PWRAP_DEW_CIPHER_RDY] =3D 0x0020, + [PWRAP_DEW_CIPHER_MODE] =3D 0x0022, + [PWRAP_DEW_CIPHER_SWRST] =3D 0x0024, + [PWRAP_DEW_CIPHER_IV0] =3D 0x0026, + [PWRAP_DEW_CIPHER_IV1] =3D 0x0028, + [PWRAP_DEW_CIPHER_IV2] =3D 0x002a, + [PWRAP_DEW_CIPHER_IV3] =3D 0x002c, + [PWRAP_DEW_CIPHER_IV4] =3D 0x002e, + [PWRAP_DEW_CIPHER_IV5] =3D 0x0030, }; =20 static const u32 mt6323_regs[] =3D { @@ -386,6 +438,22 @@ enum pwrap_regs { PWRAP_EINT_STA1_ADR, PWRAP_SWINF_2_WDATA_31_0, PWRAP_SWINF_2_RDATA_31_0, + PWRAP_DVFS_ADR0, + PWRAP_DVFS_WDATA0, + PWRAP_DVFS_ADR1, + PWRAP_DVFS_WDATA1, + PWRAP_DVFS_ADR2, + PWRAP_DVFS_WDATA2, + PWRAP_DVFS_ADR3, + PWRAP_DVFS_WDATA3, + PWRAP_DVFS_ADR4, + PWRAP_DVFS_WDATA4, + PWRAP_DVFS_ADR5, + PWRAP_DVFS_WDATA5, + PWRAP_DVFS_ADR6, + PWRAP_DVFS_WDATA6, + PWRAP_DVFS_ADR7, + PWRAP_DVFS_WDATA7, =20 /* MT2701 only regs */ PWRAP_ADC_CMD_ADDR, @@ -394,6 +462,24 @@ enum pwrap_regs { PWRAP_ADC_RDATA_ADDR1, PWRAP_ADC_RDATA_ADDR2, =20 + /* MT6589 only regs */ + PWRAP_CIPHER_IV0, + PWRAP_CIPHER_IV1, + PWRAP_CIPHER_IV2, + + /* MT6589 and MT8135 only regs */ + PWRAP_CSHEXT, + PWRAP_EVENT_IN_EN, + PWRAP_EVENT_DST_EN, + PWRAP_RRARB_INIT, + PWRAP_RRARB_EN, + PWRAP_RRARB_STA0, + PWRAP_RRARB_STA1, + PWRAP_EVENT_STA, + PWRAP_EVENT_STACLR, + PWRAP_CIPHER_LOAD, + PWRAP_CIPHER_START, + /* MT7622 only regs */ PWRAP_STA, PWRAP_CLR, @@ -422,38 +508,9 @@ enum pwrap_regs { PWRAP_DVFS_STEP_CTRL2, PWRAP_SPI2_CTRL, =20 - /* MT8135 only regs */ - PWRAP_CSHEXT, - PWRAP_EVENT_IN_EN, - PWRAP_EVENT_DST_EN, - PWRAP_RRARB_INIT, - PWRAP_RRARB_EN, - PWRAP_RRARB_STA0, - PWRAP_RRARB_STA1, - PWRAP_EVENT_STA, - PWRAP_EVENT_STACLR, - PWRAP_CIPHER_LOAD, - PWRAP_CIPHER_START, - /* MT8173 only regs */ PWRAP_RDDMY, PWRAP_SI_CK_CON, - PWRAP_DVFS_ADR0, - PWRAP_DVFS_WDATA0, - PWRAP_DVFS_ADR1, - PWRAP_DVFS_WDATA1, - PWRAP_DVFS_ADR2, - PWRAP_DVFS_WDATA2, - PWRAP_DVFS_ADR3, - PWRAP_DVFS_WDATA3, - PWRAP_DVFS_ADR4, - PWRAP_DVFS_WDATA4, - PWRAP_DVFS_ADR5, - PWRAP_DVFS_WDATA5, - PWRAP_DVFS_ADR6, - PWRAP_DVFS_WDATA6, - PWRAP_DVFS_ADR7, - PWRAP_DVFS_WDATA7, PWRAP_SPMINF_STA, PWRAP_CIPHER_EN, =20 @@ -569,6 +626,98 @@ static const int mt2701_regs[] =3D { [PWRAP_ADC_RDATA_ADDR2] =3D 0x154, }; =20 +static const int mt6589_regs[] =3D { + [PWRAP_MUX_SEL] =3D 0x0, + [PWRAP_WRAP_EN] =3D 0x4, + [PWRAP_DIO_EN] =3D 0x8, + [PWRAP_SIDLY] =3D 0xc, + [PWRAP_CSHEXT] =3D 0x10, + [PWRAP_CSHEXT_WRITE] =3D 0x14, + [PWRAP_CSHEXT_READ] =3D 0x18, + [PWRAP_CSLEXT_START] =3D 0x1c, + [PWRAP_CSLEXT_END] =3D 0x20, + [PWRAP_STAUPD_PRD] =3D 0x24, + [PWRAP_STAUPD_GRPEN] =3D 0x28, + [PWRAP_STAUPD_MAN_TRIG] =3D 0x2c, + [PWRAP_STAUPD_STA] =3D 0x30, + [PWRAP_EVENT_IN_EN] =3D 0x34, + [PWRAP_EVENT_DST_EN] =3D 0x38, + [PWRAP_WRAP_STA] =3D 0x3c, + [PWRAP_RRARB_INIT] =3D 0x40, + [PWRAP_RRARB_EN] =3D 0x44, + [PWRAP_RRARB_STA0] =3D 0x48, + [PWRAP_RRARB_STA1] =3D 0x4c, + [PWRAP_HARB_INIT] =3D 0x50, + [PWRAP_HARB_HPRIO] =3D 0x54, + [PWRAP_HIPRIO_ARB_EN] =3D 0x58, + [PWRAP_HARB_STA0] =3D 0x5c, + [PWRAP_HARB_STA1] =3D 0x60, + [PWRAP_MAN_EN] =3D 0x64, + [PWRAP_MAN_CMD] =3D 0x68, + [PWRAP_MAN_RDATA] =3D 0x6c, + [PWRAP_MAN_VLDCLR] =3D 0x70, + [PWRAP_WACS0_EN] =3D 0x74, + [PWRAP_INIT_DONE0] =3D 0x78, + [PWRAP_WACS0_CMD] =3D 0x7c, + [PWRAP_WACS0_RDATA] =3D 0x80, + [PWRAP_WACS0_VLDCLR] =3D 0x84, + [PWRAP_WACS1_EN] =3D 0x88, + [PWRAP_INIT_DONE1] =3D 0x8c, + [PWRAP_WACS1_CMD] =3D 0x90, + [PWRAP_WACS1_RDATA] =3D 0x94, + [PWRAP_WACS1_VLDCLR] =3D 0x98, + [PWRAP_WACS2_EN] =3D 0x9c, + [PWRAP_INIT_DONE2] =3D 0xa0, + [PWRAP_WACS2_CMD] =3D 0xa4, + [PWRAP_WACS2_RDATA] =3D 0xa8, + [PWRAP_WACS2_VLDCLR] =3D 0xac, + [PWRAP_INT_EN] =3D 0xb0, + [PWRAP_INT_FLG_RAW] =3D 0xb4, + [PWRAP_INT_FLG] =3D 0xb8, + [PWRAP_INT_CLR] =3D 0xbc, + [PWRAP_SIG_ADR] =3D 0xc0, + [PWRAP_SIG_MODE] =3D 0xc4, + [PWRAP_SIG_VALUE] =3D 0xc8, + [PWRAP_SIG_ERRVAL] =3D 0xcc, + [PWRAP_CRC_EN] =3D 0xd0, + [PWRAP_EVENT_STA] =3D 0xd4, + [PWRAP_EVENT_STACLR] =3D 0xd8, + [PWRAP_TIMER_EN] =3D 0xdc, + [PWRAP_TIMER_STA] =3D 0xe0, + [PWRAP_WDT_UNIT] =3D 0xe4, + [PWRAP_WDT_SRC_EN] =3D 0xe8, + [PWRAP_WDT_FLG] =3D 0xec, + [PWRAP_DEBUG_INT_SEL] =3D 0xf0, + [PWRAP_DVFS_ADR0] =3D 0xf4, + [PWRAP_DVFS_WDATA0] =3D 0xf8, + [PWRAP_DVFS_ADR1] =3D 0xfc, + [PWRAP_DVFS_WDATA1] =3D 0x100, + [PWRAP_DVFS_ADR2] =3D 0x104, + [PWRAP_DVFS_WDATA2] =3D 0x108, + [PWRAP_DVFS_ADR3] =3D 0x10c, + [PWRAP_DVFS_WDATA3] =3D 0x110, + [PWRAP_DVFS_ADR4] =3D 0x114, + [PWRAP_DVFS_WDATA4] =3D 0x118, + [PWRAP_DVFS_ADR5] =3D 0x11c, + [PWRAP_DVFS_WDATA5] =3D 0x120, + [PWRAP_DVFS_ADR6] =3D 0x124, + [PWRAP_DVFS_WDATA6] =3D 0x128, + [PWRAP_DVFS_ADR7] =3D 0x12c, + [PWRAP_DVFS_WDATA7] =3D 0x130, + [PWRAP_CIPHER_KEY_SEL] =3D 0x134, + [PWRAP_CIPHER_IV_SEL] =3D 0x138, + [PWRAP_CIPHER_LOAD] =3D 0x13c, + [PWRAP_CIPHER_START] =3D 0x140, + [PWRAP_CIPHER_RDY] =3D 0x144, + [PWRAP_CIPHER_MODE] =3D 0x148, + [PWRAP_CIPHER_SWRST] =3D 0x14c, + [PWRAP_CIPHER_IV0] =3D 0x150, + [PWRAP_CIPHER_IV1] =3D 0x154, + [PWRAP_CIPHER_IV2] =3D 0x158, + [PWRAP_DCM_EN] =3D 0x15c, + [PWRAP_DCM_DBC_PRD] =3D 0x160, +}; + static const int mt6765_regs[] =3D { [PWRAP_MUX_SEL] =3D 0x0, [PWRAP_WRAP_EN] =3D 0x4, @@ -1301,6 +1450,7 @@ static const int mt8186_regs[] =3D { }; =20 enum pmic_type { + PMIC_MT6320, PMIC_MT6323, PMIC_MT6331, PMIC_MT6332, @@ -1314,6 +1464,7 @@ enum pmic_type { =20 enum pwrap_type { PWRAP_MT2701, + PWRAP_MT6589, PWRAP_MT6765, PWRAP_MT6779, PWRAP_MT6795, @@ -1750,6 +1901,7 @@ static int pwrap_common_init_reg_clock(struct pmic_wr= apper *wrp) case PWRAP_MT8173: pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2); break; + case PWRAP_MT6589: case PWRAP_MT8135: pwrap_writel(wrp, 0x4, PWRAP_CSHEXT); pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0); @@ -1834,6 +1986,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL); =20 switch (wrp->master->type) { + case PWRAP_MT6589: case PWRAP_MT8135: pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD); pwrap_writel(wrp, 1, PWRAP_CIPHER_START); @@ -1866,6 +2019,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp) pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs); =20 switch (wrp->slave->type) { + case PMIC_MT6320: case PMIC_MT6397: pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD], 0x1); @@ -1960,13 +2114,13 @@ static int pwrap_mt8135_init_soc_specific(struct pm= ic_wrapper *wrp) /* enable pwrap events and pwrap bridge in AP side */ pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN); pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN); - writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT); - writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN); - writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN); - writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN); + writel(0x7f, wrp->bridge_base + PWRAP_BRIDGE_IORD_ARB_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS3_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WACS4_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_WDT_UNIT); + writel(0xffff, wrp->bridge_base + PWRAP_BRIDGE_WDT_SRC_EN); + writel(0x1, wrp->bridge_base + PWRAP_BRIDGE_TIMER_EN); + writel(0x7ff, wrp->bridge_base + PWRAP_BRIDGE_INT_EN); =20 /* enable PMIC event out and sources */ if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN], @@ -2110,7 +2264,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) return ret; } =20 - if (wrp->master->type =3D=3D PWRAP_MT8135) + if (wrp->master->type =3D=3D PWRAP_MT8135 || + wrp->master->type =3D=3D PWRAP_MT6589) pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN); =20 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN); @@ -2131,8 +2286,8 @@ static int pwrap_init(struct pmic_wrapper *wrp) pwrap_writel(wrp, 1, PWRAP_INIT_DONE1); =20 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) { - writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3); - writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4); + writel(1, wrp->bridge_base + PWRAP_BRIDGE_INIT_DONE3); + writel(1, wrp->bridge_base + PWRAP_BRIDGE_INIT_DONE4); } =20 return 0; @@ -2186,6 +2341,14 @@ static const struct pwrap_slv_regops pwrap_regops32 = =3D { .regmap =3D &pwrap_regmap_config32, }; =20 +static const struct pwrap_slv_type pmic_mt6320 =3D { + .dew_regs =3D mt6320_regs, + .type =3D PMIC_MT6320, + .regops =3D &pwrap_regops16, + .caps =3D PWRAP_SLV_CAP_SPI | PWRAP_DEW_DIO_EN | + PWRAP_SLV_CAP_SECURITY, +}; + static const struct pwrap_slv_type pmic_mt6323 =3D { .dew_regs =3D mt6323_regs, .type =3D PMIC_MT6323, @@ -2248,6 +2411,7 @@ static const struct pwrap_slv_type pmic_mt6397 =3D { }; =20 static const struct of_device_id of_slave_match_tbl[] =3D { + { .compatible =3D "mediatek,mt6320", .data =3D &pmic_mt6320 }, { .compatible =3D "mediatek,mt6323", .data =3D &pmic_mt6323 }, { .compatible =3D "mediatek,mt6331", .data =3D &pmic_mt6331 }, { .compatible =3D "mediatek,mt6351", .data =3D &pmic_mt6351 }, @@ -2277,6 +2441,19 @@ static const struct pmic_wrapper_type pwrap_mt2701 = =3D { .init_soc_specific =3D pwrap_mt2701_init_soc_specific, }; =20 +static const struct pmic_wrapper_type pwrap_mt6589 =3D { + .regs =3D mt6589_regs, + .type =3D PWRAP_MT6589, + .arb_en_all =3D 0x1ff, + .int_en_all =3D 0x7ffffffd, + .int1_en_all =3D 0, + .spi_w =3D PWRAP_MAN_CMD_SPI_WRITE, + .wdt_src =3D PWRAP_WDT_SRC_MASK_ALL, + .caps =3D PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM, + .init_reg_clock =3D pwrap_common_init_reg_clock, + .init_soc_specific =3D pwrap_mt8135_init_soc_specific, +}; + static const struct pmic_wrapper_type pwrap_mt6765 =3D { .regs =3D mt6765_regs, .type =3D PWRAP_MT6765, @@ -2446,6 +2623,7 @@ static const struct pmic_wrapper_type pwrap_mt8186 = =3D { =20 static const struct of_device_id of_pwrap_match_tbl[] =3D { { .compatible =3D "mediatek,mt2701-pwrap", .data =3D &pwrap_mt2701 }, + { .compatible =3D "mediatek,mt6589-pwrap", .data =3D &pwrap_mt6589 }, { .compatible =3D "mediatek,mt6765-pwrap", .data =3D &pwrap_mt6765 }, { .compatible =3D "mediatek,mt6779-pwrap", .data =3D &pwrap_mt6779 }, { .compatible =3D "mediatek,mt6795-pwrap", .data =3D &pwrap_mt6795 }, --=20 2.54.0