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Thu, 16 Jul 2026 04:40:10 -0700 (PDT) From: David Oberhollenzer To: devicetree@vger.kernel.org, linux-omap@vger.kernel.org, linux-kernel@vger.kernel.org, conor+dt@kernel.org, krzk+dt@kernel.org, robh@kernel.org, tony@atomide.com, rogerq@kernel.org, khilman@baylibre.com, andreas@kemnade.info, aaro.koskinen@iki.fi Cc: Julian.FRIEDRICH@frequentis.com, upstream+omap@sigma-star.at, David Oberhollenzer Subject: [PATCH] ARM: dts: ti/omap: dra7: fix PCIe PHY clock divider definition Date: Thu, 16 Jul 2026 13:39:47 +0200 Message-ID: <20260716113947.92513-1-david.oberhollenzer@sigma-star.at> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit d0bdd8bb7f35 ("ARM: dts: ti/omap: dra7: fix redundant clock divider definition") removes the clock divider definition from optfclk_pciephy_div, reasoning that the table is redundant, as it contains the values 1 and 2, while also setting ti,max-div to 2 while ti,min-div is implicitly initialized to 1. What that commit missed was the fact that the values in the table are in reverse order, i.e. first 2, then 1. As is clearly described in the documentation, the ordering is signifficant, the actual values for the register setting are derived from the index. If no table is specified, the driver assumes that the register value is divider - 1 (see also `_get_val` in `drivers/clk/ti/divider.c`). What is in fact redundant is the value of ti,max-div that is derived from the table if none is specified. To satisfy device tree semantic linters, it is removed instead. Fixes: d0bdd8bb7f35 ("fix redundant clock divider definition") Signed-off-by: David Oberhollenzer --- arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi b/arch/arm/boot/d= ts/ti/omap/dra7xx-clocks.dtsi index 0de16ee262cf..615a8fb47776 100644 --- a/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi @@ -1376,8 +1376,8 @@ optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00= 821c { clocks =3D <&apll_pcie_ck>; #clock-cells =3D <0>; reg =3D <0x021c>; + ti,dividers =3D <2>, <1>; ti,bit-shift =3D <8>; - ti,max-div =3D <2>; }; =20 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo { --=20 2.55.0