From nobody Mon Jul 27 20:02:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01932442FDE; Thu, 16 Jul 2026 17:33:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784223237; cv=none; b=biX2VzPegJI0IBEKqvaZGhAx7AZgquhbKXMhNDhwLcs4bRwI/lsLa/3O0SRxgm9MS6pm3MpylUlSS7YULMQeE+EwRFUefwl44XnBXP+wctRVTuoPwn3AmRZF8B9//ykzPFdb5AWD16ATf982jH4AMzs6omqhXykRxC5widABLTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784223237; c=relaxed/simple; bh=q2lLkxNaadrgXTsv8cEEY723l15J0hmf8UnRHnzBKSg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AqZ5fvRFv/LXkhdFUh++riJX6hhPx1Y5a9LqxiPjhHeDIjYFt+mAVTQ5dMlvDljvq5hdGgA8ugVikuO/HXzl3H5QXgXSwCe7OUkq3NKwcsnk+ugTeb6/K4Ut4DVgLXo6FZR/ymfhLl0GiPtdEJWifPbR5M3jvTYozQWGihLXd+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BHhikT5y; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BHhikT5y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 327A21F00A3D; Thu, 16 Jul 2026 17:33:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784223235; bh=1Ceq8mFJ/Vm5ez9i9TjFa0c2lAx5jjZdX4+jrUDU9Vo=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=BHhikT5ypZ72X/FL3kXDNv0UT9uIS7xkT9qnvKquh4z2ARz7PSKGUVZO4qpgRFe4m ptL/YfzKrDd1RhAaJFC8/Tld+egPfunwfi7hJRfLjvYGDWLE7Z2ns+2jHI+iiDJHm9 Wvyajsf9zE+7TOI1HDbi/+oCNeHciy5X+tFaZokz930hkWvfe0r5QQ3r/HI8DV5Rbr zxn7i9qm5aOKXItUBWvL7GDLAN+xJffeVeo23bWP4H4l+gnrc7vI9mzYLTaQ6pLYuQ 1zrLEEcIjvvrLWxNCRihIwdSHEL0cN1A67fSMiOQM0YBYiSEKvLOkIcfgI+9j03Lf8 ytZ0sfsZFRp5A== From: Konrad Dybcio Date: Thu, 16 Jul 2026 19:33:42 +0200 Subject: [PATCH 1/2] arm64: dts: qcom: smb2370: Disable SMB2370_2 by default Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260716-topic-smb2370_port2-v1-1-83d02b2ba4b0@oss.qualcomm.com> References: <20260716-topic-smb2370_port2-v1-0-83d02b2ba4b0@oss.qualcomm.com> In-Reply-To: <20260716-topic-smb2370_port2-v1-0-83d02b2ba4b0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784223229; l=815; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=aYmIoaIAFX1Z+JiTV83VrqjeioU8i3Dqis0+WcJiBlc=; b=ZeZIZgKz8Zmur/DyiXxXHaWN/1h85igZeyH9L3GfgO868/KsSm6XsGziCuWj2Mpnr7XgJ58b2 6C+2UCn1rBLBJgr1s8G2ZyabAyBO9RbN4txfVkMveM0zeF6nFSFSf51 X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio It's absent on laptops that only have 2 type-C ports (the majority so far, including the CRD). Keep it disabled by default, following established practice from the previous generation. Signed-off-by: Konrad Dybcio Reviewed-by: Gopikrishna Garmidi --- arch/arm64/boot/dts/qcom/smb2370.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/smb2370.dtsi b/arch/arm64/boot/dts/qc= om/smb2370.dtsi index 80f3fdae5705..1e02578e4ee3 100644 --- a/arch/arm64/boot/dts/qcom/smb2370.dtsi +++ b/arch/arm64/boot/dts/qcom/smb2370.dtsi @@ -36,6 +36,8 @@ smb2370_l_e2: pmic@b { #address-cells =3D <1>; #size-cells =3D <0>; =20 + status =3D "disabled"; + smb2370_l_e2_eusb2_repeater: phy@fd00 { compatible =3D "qcom,smb2370-eusb2-repeater"; reg =3D <0xfd00>; --=20 2.55.0 From nobody Mon Jul 27 20:02:54 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 41134443AAE; Thu, 16 Jul 2026 17:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784223240; cv=none; b=P/2wspPytj0z8DfqgJmPa23BlwMzL7NWLSuyFtARxbdxH0zBGnC9pIwmeJvkyDwh/meJGAYqLREduRtCherlesUe6ULxemFV3tJArzADNMn6V91p4pimQe6SkzY7rCZpm2wrxVw+NuelBAeNiRo5UM/UtWQ/28XPcQGQKQp1ABM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784223240; c=relaxed/simple; bh=U3f2i+S1l7IicozaxVBk8mvLIf8XqNOAaChMA7rsGaU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=cRXO2HYZb6aFCYH65XUV/9p5/dW50yBnDFv7kHXyrQnlNYDHMVRrI2DTYLUVhsuVkA9nAmkinY4WzZYxmXXRkb2YeladQ7uvo9VYLekIW8ZqhU3v1+IM5th2Jkn+AtdrJfqpgumbPRGtNm/6erjsMRsRxGAoXZe8BMexq8UXry4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=asBZlIq3; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="asBZlIq3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 293A21F000E9; Thu, 16 Jul 2026 17:33:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784223238; bh=2h/eflKxXmNY1+ClhaFTWs5e/Z5XUAroC1vzlwrkPFA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=asBZlIq3OWSgQd6kmk3CY3rXlN93kHAQ4Te2bhWwSfG0Np267Tsvnrua4qswWbMK1 9XMJB054fUmeYy/Cfc4reTYMnSoY/4m84iElvN6bCn3bHEwY72FI5LUtlqrt4Q3qDf 8C2O0PwFX0mtEObGcn6C/BFIocg/AyxzX1RP9HPvdBboncQb+jci0XkZ79O7OT8vxg UOAXI5Kcv4T81GFpSjaZLjs6tz0RCxYy436ZFDKOmoq6ZuCWSrT98+k6Ov0dIwmzpn RQPszEzS9rxGA9LaORKadBX2c0OE+eNk2O2S80uyEqjkRHaqQ8vm6uNVBwnQpQq6bd u2bJ4htbSQyoQ== From: Konrad Dybcio Date: Thu, 16 Jul 2026 19:33:43 +0200 Subject: [PATCH 2/2] arm64: dts: qcom: glymur: Add PCIe port compatibles and ports Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260716-topic-smb2370_port2-v1-2-83d02b2ba4b0@oss.qualcomm.com> References: <20260716-topic-smb2370_port2-v1-0-83d02b2ba4b0@oss.qualcomm.com> In-Reply-To: <20260716-topic-smb2370_port2-v1-0-83d02b2ba4b0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784223229; l=2171; i=konrad.dybcio@oss.qualcomm.com; s=20230215; h=from:subject:message-id; bh=305DCkMnj6IJ3KfBtHD3BIkdK3eM0+n7UFRwuDNYKoA=; b=VSKiFCvboUEYbWXuSLqNUTSxHzvCFRMCOv8oJSSAEmCDxyGg7MxIUq6j6Ge0yZML/18FVI0nn 4RDHZrPG/1PDp5ShVkKTm75ebrIV2AzA6Cj9o2SbwEbaaahZtt3eDxV X-Developer-Key: i=konrad.dybcio@oss.qualcomm.com; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= From: Konrad Dybcio Centrally define the endpoints to let device DTs that describe PCIe devices and/or M.2 connectors refer to them without error-prone duplication. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/glymur.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index 55d91c696a3a..8d7354affd48 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2946,6 +2946,7 @@ opp-32000000-4 { =20 pcie4_port0: pcie@0 { device_type =3D "pci"; + compatible =3D "pciclass,0604"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 @@ -2954,6 +2955,11 @@ pcie4_port0: pcie@0 { #address-cells =3D <3>; #size-cells =3D <2>; ranges; + + port { + pcie4_port0_ep: endpoint { + }; + }; }; }; =20 @@ -3212,6 +3218,7 @@ opp-128000000-5 { =20 pcie5_port0: pcie@0 { device_type =3D "pci"; + compatible =3D "pciclass,0604"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 @@ -3220,6 +3227,11 @@ pcie5_port0: pcie@0 { #address-cells =3D <3>; #size-cells =3D <2>; ranges; + + port { + pcie5_port0_ep: endpoint { + }; + }; }; }; =20 @@ -3422,6 +3434,7 @@ opp-32000000-4 { =20 pcie6_port0: pcie@0 { device_type =3D "pci"; + compatible =3D "pciclass,0604"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 @@ -3430,6 +3443,11 @@ pcie6_port0: pcie@0 { #address-cells =3D <3>; #size-cells =3D <2>; ranges; + + port { + pcie6_port0_ep: endpoint { + }; + }; }; }; =20 @@ -3688,6 +3706,7 @@ opp-128000000-5 { =20 pcie3b_port0: pcie@0 { device_type =3D "pci"; + compatible =3D "pciclass,0604"; reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 @@ -3696,6 +3715,11 @@ pcie3b_port0: pcie@0 { #address-cells =3D <3>; #size-cells =3D <2>; ranges; + + port { + pcie3b_port0_ep: endpoint { + }; + }; }; }; =20 --=20 2.55.0