From nobody Mon Jul 27 18:59:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B42C3433BCB; Thu, 16 Jul 2026 17:07:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784221660; cv=none; b=fbr9E2lXYuHT2GF4TkXANJvcp1AF4YTvNifdVyl+hBkuUsLBm4ceutBLyoeulhrssak//iYK7oCL/sWTg6tv7/e7fxc76o1XyfMAgNmIyryhCj370Vu2OeJMy6p6Wwvn38GioSUKSl4j7ZsoryO7Jg53dWgxm9oRVOFzHi/NIJs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784221660; c=relaxed/simple; bh=gW7yskx0hJe4wqbjC3Uh9uR5y58UvdjvlKeXqi7lhsE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QkgcBdTQF8J1Bl2xESjneeZyB/9+7rL6TcMc/4LMhdjOIH8iIa4PM9oO2BJv4NrbPh7uiI6sfJQGVQJnXr8/U8noSQw5DqZFmRwnA2pbFqXzWTFmBvmlQ+Zz3scmPCkMdphpXi+mz9eAl/As0JZ412cY0+tWeoxjwbD/9jAqq3k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ikMp6gCi; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ikMp6gCi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A99731F00A3A; Thu, 16 Jul 2026 17:07:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784221654; bh=d8keb7Vf5mcDOWQ8qaY4y+UDfw6ta0RP32gTRI58mxc=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ikMp6gCia4sI8zJ5UktScFnaCBko744+wuW1338qA4GsddBGYwU3s+ViYAODyvPqv vKmeyGGfhr3KcdaxeS+q1siNKOdTUUvZ0SwFaQy4aaUkIUSVeMZlZZ8UwObJ0WIGkK q3eRK3914mQyqNjJ8Y+o8RIWF+pya9aRjmBGrS8NBaGK7/oIK/S4Y3d2YSCYgadAeW JVIEBiyube3Mt0UPtbqBMuXldIg0zfIkQpe78HkIZxy4FgbH1rjzmZYpDMJm9iFEth vFqUyLzCDknDqta4GI3fX2qRCuQbUccrQ8KJgpeVhUPVOOPaRWIHCU2shTaTGXJgrN CQWlSMUPy2O3w== From: Thierry Reding Date: Thu, 16 Jul 2026 19:07:12 +0200 Subject: [PATCH v8 1/6] dt-bindings: pci: tegra264: Strictly distinguish C0 from C1-C5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260716-tegra264-pcie-v8-1-23e51589229b@nvidia.com> References: <20260716-tegra264-pcie-v8-0-23e51589229b@nvidia.com> In-Reply-To: <20260716-tegra264-pcie-v8-0-23e51589229b@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5710; i=treding@nvidia.com; h=from:subject:message-id; bh=gA/SKuXPQwDidcW7rDgkqxu6NGKwUPEXWt8YBaFws+g=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqWQ/Q0rpOfRZUKOhMpUqiigHzGrTS/ciHfOMMz xnRfTN2ST6JAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCalkP0AAKCRDdI6zXfz6z oaP1EACRL0w6KEF/FRhEl9JLftSPZaQROJVJLGsiN2ODs8cQxUiwVHZ85J0/8Q9mBySoxT6YjN6 52P9OoRoQdM+SJrpLU4qHUVRxbCQFGCzzFxSxcJVAUzsab3RY1l4A5MhJzh7WLjadX5evCakEvu RJGXD5HO0Za7eiFJuKHptVpvefOqq5E4nODDdM92oqFmPgtnOydMREqM4iqfddIPD1f8gwsNJq6 38kGxVvYzh8Wit7ri563UsRoKWjVaQelIXKx6sTVat0OsepzsHG5aEXugVRD5hjlOC5dXZo/Tph UGdfvMhvoUt4XmlyANvCxx3cMGpMGuFu4PrV7oB/QzIXmm5kC5G+9folMzzy8PauluOqn0Ktw99 G4d0DgsQdjhB/RYk3k9b7f5WF2VYwLE6vAlDtQ2Xjzqe2VFr7U+kdvU1jVuV2Ert75SgbfB84g2 Xjmu6IMT/Tj/wRZLflrmq6esdRJbQCYYObX6ac8kuaOAko55C2pcxm0lC6il16zRiYub5MFLlZx F8WL6xp3Flgx2sNObzXK9zxEqVx1BOma2oQZKw4KemP2UDRaAxdJ/4N20b9VMGCgqMcw0Jwm7+/ LE0p448Tt7L3CQYfF/znAYYFZvLYA8E3Ssz5bFhn2eHnutGpZLdycB7WC9Vdy0We+XgI45U4suJ 6uFSzjL+lV8r6aQ== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Instead of using the ECAM registers as the first entry, strictly make a distinction between C0 and C1-C5. This is needed because otherwise the unit address doesn't match the first "reg" entry. We also cannot change the ordering of these nodes to follow the ECAM addresses because that would put them outside of their "control bus" hierarchy since the ECAM address space is a global one outside of any of the control busses. Reviewed-by: Rob Herring (Arm) Signed-off-by: Thierry Reding --- Changes in v7: - undo changes suggested by Sashiko, should've trust the dedicated tool rather than the AI Changes in v6: - add maxItems as suggested by Sashiko Changes in v5: - rebase on top of v7.1-rc1, make it into a fix Changes in v4: - ECAM is outside of the controller's region, so it cannot be the first reg entry, otherwise we get warnings because it doesn't match the unit-address, so revert back to oneOf construct Changes in v2: - move ECAM region first and unify C0 vs. C1-C5 - move unevaluatedProperties to right before the examples - add description to clarify the two types of controllers - add examples for C0 and C1-C5 --- .../bindings/pci/nvidia,tegra264-pcie.yaml | 75 ++++++++++++++----= ---- 1 file changed, 50 insertions(+), 25 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml index dc4f8725c9f5..acb677d477fb 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -10,32 +10,23 @@ maintainers: - Thierry Reding - Jon Hunter =20 +description: | + Of the six PCIe controllers found on Tegra264, one (C0) is used for the + internal GPU and the other five (C1-C5) are routed to connectors such as + PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1 + through C5, but not for C0. + properties: compatible: const: nvidia,tegra264-pcie =20 reg: - description: | - Of the six PCIe controllers found on Tegra264, one (C0) is used for = the - internal GPU and the other five (C1-C5) are routed to connectors suc= h as - PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for = C1 - through C5, but not for C0. minItems: 4 - items: - - description: ECAM-compatible configuration space - - description: application layer registers - - description: transaction layer registers - - description: privileged transaction layer registers - - description: data link/physical layer registers (not available on = C0) + maxItems: 5 =20 reg-names: minItems: 4 - items: - - const: ecam - - const: xal - - const: xtl - - const: xtl-pri - - const: xpl + maxItems: 5 =20 interrupts: minItems: 1 @@ -70,6 +61,40 @@ required: =20 allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# + - oneOf: + - description: C0 controller (no UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: ecam + + - description: C1-C5 controllers (with UPHY) + properties: + reg: + items: + - description: application layer registers + - description: transaction layer registers + - description: privileged transaction layer registers + - description: data link/physical layer registers + - description: ECAM compatible configuration space + + reg-names: + items: + - const: xal + - const: xtl + - const: xtl-pri + - const: xpl + - const: ecam =20 unevaluatedProperties: false =20 @@ -81,11 +106,11 @@ examples: =20 pci@c000000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg =3D <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -118,12 +143,12 @@ examples: =20 pci@8400000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg =3D <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Switch to using the PCIe root port bindings in preparation for using the standard WAKE# handling. Signed-off-by: Thierry Reding Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/nvidia,tegra264-pcie.yaml | 40 +++++++++++++++++-= ---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yam= l b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml index acb677d477fb..f0114defc04e 100644 --- a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml @@ -52,12 +52,11 @@ properties: - description: PCIe controller ID maximum: 5 =20 -required: - - interrupt-map - - interrupt-map-mask - - iommu-map - - msi-map - - nvidia,bpmp +patternProperties: + '^pcie@': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + unevaluatedProperties: false =20 allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# @@ -96,6 +95,13 @@ allOf: - const: xpl - const: ecam =20 +required: + - interrupt-map + - interrupt-map-mask + - iommu-map + - msi-map + - nvidia,bpmp + unevaluatedProperties: false =20 examples: @@ -130,9 +136,18 @@ examples: ranges =3D <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x0020= 0000>, <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x080000= 00>, <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc00000= 00>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260716-tegra264-pcie-v8-3-23e51589229b@nvidia.com> References: <20260716-tegra264-pcie-v8-0-23e51589229b@nvidia.com> In-Reply-To: <20260716-tegra264-pcie-v8-0-23e51589229b@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7585; i=treding@nvidia.com; h=from:subject:message-id; bh=JmbVJZG0ek7JwrjZ8mJSK4lVcfAx1G+/ygj6G4RV5Z8=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqWQ/QdzKLgojz1NTzlGmvj6Q9YfKXDz1d26gLm YNWF8wYR0yJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCalkP0AAKCRDdI6zXfz6z oVlNEACFvQe3oWt9wQOxG85TSLBT33yvOILfISWCqmLZVNumHpRZ0pbAAdC/nYo3wi3v43eFk5a kwEUl37p/aCuPdfP313mQCiZ4lgaoHYqufZHahNO5i8oGxgOrIA4nbCGWwKP1NcJ5h8bZwBrh/o dRfxs85WkIEQ8lbynGUH6DSXXixme4tjJ0LmFW0Lxsvoafg3VVW6bmVGtbCaXoEE61NCX6AJJuR QQMKqqe/YfHR42ESy7V6LFvV8dlwpNga0mdpQI4LHFqvTeGX8rJTrhzQWYTvaIUBlPyI4JBKI6D 99v8iS8K73v3AhX/P2Uz4jHZwj19y/CczCs57X6dji4TH7Fh+OooUaxn0DQ+mWugLeg58iAosXF LBTLoXEymahEZvB8OfoFBRJkvDAsboaPpSi5/jstbVTZVPAWC55ibrNU0pblLsFSmQrM9H6fgYE wilQrSMNwD5IaEAQ+A1ZzgflxiV1c44x7oxoNCpozJJ6q/Lt4ts4uT7RWk0Ioq1GhzyQTpQwVIq O1SsYS8lPiWlnPpAS9/5qPYBx3Q7tEB+Qllf4kA2AakfY5DJLITwYDmOJn8cgYgLQbtTDzhfTeo mOeA9id/MlmCYI+psyHsn/SGWCGOptANCGXwVI7HicOweve0hwdOKZOAUsjzttH4UKLP/kFUBKL /1/o1R+SLRqDusA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Instead of defining the wait values for each driver, use common values defined in the core pci.h header file. Note that while most drivers use the usleep_range(), it looks like these were mostly cargo culted and msleep() is a better choice given the fixed delay that the specification calls for. Convert all drivers to msleep() and use the existing definition. Reviewed-by: Aksh Garg Signed-off-by: Thierry Reding --- Changes in v8: - add Reviewed-by from Aksh Garg Changes in v7: - rebase on top of next-20260615 (resolve pci-aardvark.c conflict) Changes in v6: - convert all drivers to use msleep() (Lukas Wunner) Changes in v2: - fix build for Cadence --- drivers/pci/controller/cadence/pcie-cadence-host-common.c | 6 ++++-- drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 ----- drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++-- drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 ----- drivers/pci/controller/pci-aardvark.c | 7 ++----- drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++------- drivers/pci/controller/plda/pcie-starfive.c | 9 ++------- 7 files changed, 12 insertions(+), 33 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c index 18e4b6c760b5..0ef4396151b4 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -16,6 +16,8 @@ #include "pcie-cadence-host-common.h" #include "../pci-host-common.h" =20 +#include "../../pci.h" + #define LINK_RETRAIN_TIMEOUT HZ =20 u64 bar_max_size[] =3D { @@ -54,12 +56,12 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie, int retries; =20 /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (pcie_link_up(pcie)) { dev_info(dev, "Link up\n"); return 0; } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h index 857b2140c5d2..15dc4fcaf45d 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -10,11 +10,6 @@ =20 #include =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - /* Local Management Registers */ #define CDNS_PCIE_LM_BASE 0x00100000 =20 diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/= controller/mobiveil/pcie-mobiveil.c index 62ecbaeb0a60..e8346851c49b 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c @@ -218,11 +218,11 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (mobiveil_pcie_link_up(pcie)) return 0; =20 - usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 dev_err(&pcie->pdev->dev, "link never came up\n"); diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/= controller/mobiveil/pcie-mobiveil.h index 7246de6a7176..11010a99e27c 100644 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h @@ -122,11 +122,6 @@ #define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024) #define MAX_PIO_WINDOWS 8 =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_MIN 90000 -#define LINK_WAIT_MAX 100000 - #define PAGED_ADDR_BNDRY 0xc00 #define OFFSET_TO_PAGE_ADDR(off) \ ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY) diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller= /pci-aardvark.c index fd9c7d53e8a7..272c5c8fc1e5 100644 --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -256,9 +256,6 @@ enum { #define PIO_RETRY_CNT 750000 /* 1.5 s */ #define PIO_RETRY_DELAY 2 /* 2 us*/ =20 -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 #define RETRAIN_WAIT_MAX_RETRIES 10 #define RETRAIN_WAIT_USLEEP_US 2000 =20 @@ -350,13 +347,13 @@ static int advk_pcie_wait_for_link(struct advk_pcie *= pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (advk_pcie_link_up(pcie)) { pci_host_common_link_train_delay(pcie->link_gen); return 0; } =20 - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 return -ETIMEDOUT; diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/control= ler/pcie-xilinx-nwl.c index 7db2c96c6cec..0dee19fa24ca 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -140,11 +140,6 @@ #define PCIE_PHY_LINKUP_BIT BIT(0) #define PHY_RDY_LINKUP_BIT BIT(1) =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct nwl_msi { /* MSI information */ DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR); struct irq_domain *dev_domain; @@ -203,10 +198,10 @@ static int nwl_wait_for_link(struct nwl_pcie *pcie) int retries; =20 /* check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + for (retries =3D 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) { if (nwl_phy_link_up(pcie)) return 0; - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + msleep(PCIE_LINK_WAIT_SLEEP_MS); } =20 dev_err(dev, "PHY link never came up\n"); diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/cont= roller/plda/pcie-starfive.c index 298036c3e7f9..2835c7af965e 100644 --- a/drivers/pci/controller/plda/pcie-starfive.c +++ b/drivers/pci/controller/plda/pcie-starfive.c @@ -45,11 +45,6 @@ #define STG_SYSCON_LNKSTA_OFFSET 0x170 #define DATA_LINK_ACTIVE BIT(5) =20 -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - struct starfive_jh7110_pcie { struct plda_pcie_rp plda; struct reset_control *resets; @@ -217,12 +212,12 @@ static int starfive_pcie_host_wait_for_link(struct st= arfive_jh7110_pcie *pcie) int retries; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding Add a driver for the PCIe controller found on NVIDIA Tegra264 SoCs. The driver is very small, with its main purpose being to set up the address translation registers and then creating a standard PCI host using ECAM. Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- Changes in v8: - remove controller deinitialization, firmware does this already - separately track hotplug support and link up state for clarity - select pinctrl sleep state on suspend for symmetry with resume - fail probe if the link is down and not hotplug-capable - remove WAKE# IRQ support - add err_ prefix to gotos Changes in v7: - select PCI_ECAM to satisfy the build dependency (Jonathan Hunter) - remove pre-silicon support patch to avoid extra build dependency Changes in v6: - remove unneeded pm_runtime_disable() call (Sashiko) - do not use noirq suspend/resume callbacks (Sashiko) - wrap PM ops in pm_ptr() macro (Sashiko) - use standard wait times with msleep() (Lukas Wunner) - properly check errors for wake IRQs - fix build failures /o\ Changes in v5: - make PCIE_TEGRA264 symbol tristate - drop dependency on PCI_MSI - reorganize tegra264_pcie struct - use standard wake-gpios property - rename tegra264_pcie_bpmp_set_rp_state() to tegra264_pcie_power_off() - use dev_err() instead of dev_info() for some error messages - add clarifying comment as to why bandwidth requests aren't fatal - address some compiler warnings on 32-bit physical address platforms - drop needless comments - explicitly deinitialize controller on suspend - use devm_pm_runtime_active_enabled() - rename "free" label to "free_ecam" - use dev_err_probe() in more places - reselect default pin state during resume, not probe - return early on absence of wake GPIO - simplify BW value calculation Changes in v2: - specify generations applicable for PCI_TEGRA driver to avoid confusion - drop SPDX-FileCopyrightText tag - rename link_state to link_up to clarify meaning - replace memset() by an empty initializer - sanity-check only enable BAR regions - bring PCI link out of reset in case firmware didn't - use common wait times instead of defining our own - use core helpers to parse and print PCI link speed - fix multi-line comment - use dev_err_probe() more ubiquitously - fix probe sequence and error cleanup - use DEFINE_NOIRQ_DEV_PM_OPS() to avoid warnings for !PM_SUSPEND - reuse more standard registers and remove unused register definitions - use %pe and ERR_PTR() to print symbolic errors - add signed-off-by from Manikanta as the original author - add myself as author after significantly modifying the driver --- drivers/pci/controller/Kconfig | 10 +- drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-tegra264.c | 485 +++++++++++++++++++++++++++++= ++++ 3 files changed, 495 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 2247709ef6d6..3045c8aecc7e 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -255,7 +255,15 @@ config PCI_TEGRA select IRQ_MSI_LIB help Say Y here if you want support for the PCIe host controller found - on NVIDIA Tegra SoCs. + on NVIDIA Tegra SoCs (Tegra20 through Tegra186). + +config PCIE_TEGRA264 + tristate "NVIDIA Tegra264 PCIe controller" + depends on ARCH_TEGRA || COMPILE_TEST + select PCI_ECAM + help + Say Y here if you want support for the PCIe host controller found + on NVIDIA Tegra264 SoCs. =20 config PCIE_RCAR_HOST bool "Renesas R-Car PCIe controller (host mode)" diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makef= ile index ac8db283f0fe..d478743b5142 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_HYPERV_INTERFACE) +=3D pci-hyperv-intf.o obj-$(CONFIG_PCI_MVEBU) +=3D pci-mvebu.o obj-$(CONFIG_PCI_AARDVARK) +=3D pci-aardvark.o obj-$(CONFIG_PCI_TEGRA) +=3D pci-tegra.o +obj-$(CONFIG_PCIE_TEGRA264) +=3D pcie-tegra264.o obj-$(CONFIG_PCI_RCAR_GEN2) +=3D pci-rcar-gen2.o obj-$(CONFIG_PCIE_RCAR_HOST) +=3D pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCIE_RCAR_EP) +=3D pcie-rcar.o pcie-rcar-ep.o diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controlle= r/pcie-tegra264.c new file mode 100644 index 000000000000..7071f4b3b97b --- /dev/null +++ b/drivers/pci/controller/pcie-tegra264.c @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PCIe host controller driver for Tegra264 SoC + * + * Copyright (c) 2022-2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "../pci.h" + +/* XAL registers */ +#define XAL_RC_ECAM_BASE_HI 0x00 +#define XAL_RC_ECAM_BASE_LO 0x04 +#define XAL_RC_ECAM_BUSMASK 0x08 +#define XAL_RC_IO_BASE_HI 0x0c +#define XAL_RC_IO_BASE_LO 0x10 +#define XAL_RC_IO_LIMIT_HI 0x14 +#define XAL_RC_IO_LIMIT_LO 0x18 +#define XAL_RC_MEM_32BIT_BASE_HI 0x1c +#define XAL_RC_MEM_32BIT_BASE_LO 0x20 +#define XAL_RC_MEM_32BIT_LIMIT_HI 0x24 +#define XAL_RC_MEM_32BIT_LIMIT_LO 0x28 +#define XAL_RC_MEM_64BIT_BASE_HI 0x2c +#define XAL_RC_MEM_64BIT_BASE_LO 0x30 +#define XAL_RC_MEM_64BIT_LIMIT_HI 0x34 +#define XAL_RC_MEM_64BIT_LIMIT_LO 0x38 +#define XAL_RC_BAR_CNTL_STANDARD 0x40 +#define XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN BIT(0) +#define XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN BIT(1) +#define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN BIT(2) + +/* XTL registers */ +#define XTL_RC_PCIE_CFG_LINK_STATUS 0x5a + +#define XTL_RC_MGMT_PERST_CONTROL 0x218 +#define XTL_RC_MGMT_PERST_CONTROL_PERST_O_N BIT(0) + +#define XTL_RC_MGMT_CLOCK_CONTROL 0x47c +#define XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_PRSNT BIT= (9) + +struct tegra264_pcie { + struct device *dev; + + /* I/O memory */ + void __iomem *xal; + void __iomem *xtl; + void __iomem *ecam; + + /* bridge configuration */ + struct pci_config_window *cfg; + struct pci_host_bridge *bridge; + + /* BPMP and bandwidth management */ + struct icc_path *icc_path; + struct tegra_bpmp *bpmp; + u32 ctl_id; + + bool supports_hotplug; + bool link_up; +}; + +static void tegra264_pcie_power_off(struct tegra264_pcie *pcie) +{ + struct tegra_bpmp_message msg =3D {}; + struct mrq_pcie_request req =3D {}; + int err; + + req.cmd =3D CMD_PCIE_RP_CONTROLLER_OFF; + req.rp_ctrlr_off.rp_controller =3D pcie->ctl_id; + + msg.mrq =3D MRQ_PCIE; + msg.tx.data =3D &req; + msg.tx.size =3D sizeof(req); + + err =3D tegra_bpmp_transfer(pcie->bpmp, &msg); + if (err) + dev_err(pcie->dev, "failed to turn off PCIe #%u: %pe\n", + pcie->ctl_id, ERR_PTR(err)); + + if (msg.rx.ret) + dev_err(pcie->dev, "failed to turn off PCIe #%u: %d\n", + pcie->ctl_id, msg.rx.ret); +} + +static void tegra264_pcie_icc_set(struct tegra264_pcie *pcie) +{ + u32 value, speed, width; + int err; + + value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + speed =3D FIELD_GET(PCI_EXP_LNKSTA_CLS, value); + width =3D FIELD_GET(PCI_EXP_LNKSTA_NLW, value); + + value =3D Mbps_to_icc(width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])); + + /* + * We don't want to error out here because a boot-critical device + * could be connected to this root port. Failure to set the bandwidth + * request may have an adverse impact on performance, but it is not + * generally fatal, so we opt to continue regardless so that users + * get a chance to fix things. + */ + err =3D icc_set_bw(pcie->icc_path, value, value); + if (err < 0) + dev_err(pcie->dev, + "failed to request bandwidth (%u MBps): %pe\n", + value, ERR_PTR(err)); +} + +/* + * The various memory regions used by the controller (I/O, memory, ECAM) a= re + * set up during early boot and have hardware-level protections in place. = If + * the DT ranges don't match what's been setup, the controller won't be ab= le + * to write the address endpoints properly, so make sure to validate that = DT + * and firmware programming agree on these ranges. + */ +static bool tegra264_pcie_check_ranges(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + struct device_node *np =3D pcie->dev->of_node; + struct of_pci_range_parser parser; + phys_addr_t phys, limit, hi, lo; + struct of_pci_range range; + struct resource *res; + bool status =3D true; + u32 value; + int err; + + err =3D of_pci_range_parser_init(&parser, np); + if (err < 0) + return false; + + for_each_of_pci_range(&parser, &range) { + unsigned int addr_hi, addr_lo, limit_hi, limit_lo, enable; + unsigned long type =3D range.flags & IORESOURCE_TYPE_BITS; + phys_addr_t start, end, mask; + const char *region =3D NULL; + + end =3D range.cpu_addr + range.size - 1; + start =3D range.cpu_addr; + + switch (type) { + case IORESOURCE_IO: + addr_hi =3D XAL_RC_IO_BASE_HI; + addr_lo =3D XAL_RC_IO_BASE_LO; + limit_hi =3D XAL_RC_IO_LIMIT_HI; + limit_lo =3D XAL_RC_IO_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_IOBAR_EN; + mask =3D SZ_64K - 1; + region =3D "I/O"; + break; + + case IORESOURCE_MEM: + if (range.flags & IORESOURCE_PREFETCH) { + addr_hi =3D XAL_RC_MEM_64BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_64BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_64BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_64BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN; + region =3D "prefetchable memory"; + } else { + addr_hi =3D XAL_RC_MEM_32BIT_BASE_HI; + addr_lo =3D XAL_RC_MEM_32BIT_BASE_LO; + limit_hi =3D XAL_RC_MEM_32BIT_LIMIT_HI; + limit_lo =3D XAL_RC_MEM_32BIT_LIMIT_LO; + enable =3D XAL_RC_BAR_CNTL_STANDARD_32B_BAR_EN; + region =3D "memory"; + } + + mask =3D SZ_1M - 1; + break; + } + + /* not interested in anything that's not I/O or memory */ + if (!region) + continue; + + /* don't check regions that haven't been enabled */ + value =3D readl(pcie->xal + XAL_RC_BAR_CNTL_STANDARD); + if ((value & enable) =3D=3D 0) + continue; + + hi =3D readl(pcie->xal + addr_hi); + lo =3D readl(pcie->xal + addr_lo); + phys =3D ((hi << 16) << 16) | lo; + + hi =3D readl(pcie->xal + limit_hi); + lo =3D readl(pcie->xal + limit_lo); + limit =3D ((hi << 16) << 16) | lo | mask; + + if (phys !=3D start || limit !=3D end) { + dev_err(pcie->dev, + "%s region mismatch: %pap-%pap -> %pap-%pap\n", + region, &phys, &limit, &start, &end); + status =3D false; + } + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return false; + + hi =3D readl(pcie->xal + XAL_RC_ECAM_BASE_HI); + lo =3D readl(pcie->xal + XAL_RC_ECAM_BASE_LO); + phys =3D ((hi << 16) << 16) | lo; + + value =3D readl(pcie->xal + XAL_RC_ECAM_BUSMASK); + limit =3D phys + ((value + 1) << 20) - 1; + + if (phys !=3D res->start || limit !=3D res->end) { + dev_err(pcie->dev, + "ECAM region mismatch: %pap-%pap -> %pap-%pap\n", + &phys, &limit, &res->start, &res->end); + status =3D false; + } + + return status; +} + +static bool tegra264_pcie_supports_hotplug(struct tegra264_pcie *pcie) +{ + u32 value =3D readl(pcie->xtl + XTL_RC_MGMT_CLOCK_CONTROL); + + return (value & XTL_RC_MGMT_CLOCK_CONTROL_PEX_CLKREQ_I_N_PIN_USE_CONV_TO_= PRSNT) !=3D 0; +} + +static bool tegra264_pcie_link_up(struct tegra264_pcie *pcie, + enum pci_bus_speed *speed) +{ + u16 value =3D readw(pcie->ecam + XTL_RC_PCIE_CFG_LINK_STATUS); + + if (value & PCI_EXP_LNKSTA_DLLLA) { + if (speed) + *speed =3D pcie_link_speed[FIELD_GET(PCI_EXP_LNKSTA_CLS, + value)]; + + return true; + } + + return false; +} + +static void tegra264_pcie_init(struct tegra264_pcie *pcie) +{ + enum pci_bus_speed speed; + unsigned int i; + u32 value; + + /* bring the endpoint out of reset */ + value =3D readl(pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + value |=3D XTL_RC_MGMT_PERST_CONTROL_PERST_O_N; + writel(value, pcie->xtl + XTL_RC_MGMT_PERST_CONTROL); + + for (i =3D 0; i < PCIE_LINK_WAIT_MAX_RETRIES; i++) { + if (tegra264_pcie_link_up(pcie, NULL)) + break; + + msleep(PCIE_LINK_WAIT_SLEEP_MS); + } + + pcie->supports_hotplug =3D tegra264_pcie_supports_hotplug(pcie); + pcie->link_up =3D tegra264_pcie_link_up(pcie, &speed); + + if (pcie->link_up) { + msleep(PCIE_RESET_CONFIG_WAIT_MS); + dev_info(pcie->dev, "PCIe #%u link is up (speed: %s)\n", + pcie->ctl_id, pci_speed_string(speed)); + tegra264_pcie_icc_set(pcie); + } else { + dev_info(pcie->dev, "PCIe #%u link is down\n", pcie->ctl_id); + + /* + * Make sure to reset the bandwidth requirements if the link + * is down but hotplug-capable. + */ + if (pcie->supports_hotplug) + tegra264_pcie_icc_set(pcie); + } +} + +static int tegra264_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct tegra264_pcie *pcie; + struct resource_entry *bus; + struct resource *res; + int err; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(struct tegra264_pcie)); + if (!bridge) + return dev_err_probe(dev, -ENOMEM, + "failed to allocate host bridge\n"); + + pcie =3D pci_host_bridge_priv(bridge); + platform_set_drvdata(pdev, pcie); + pcie->bridge =3D bridge; + pcie->dev =3D dev; + + pcie->xal =3D devm_platform_ioremap_resource_byname(pdev, "xal"); + if (IS_ERR(pcie->xal)) + return dev_err_probe(dev, PTR_ERR(pcie->xal), + "failed to map XAL memory\n"); + + pcie->xtl =3D devm_platform_ioremap_resource_byname(pdev, "xtl-pri"); + if (IS_ERR(pcie->xtl)) + return dev_err_probe(dev, PTR_ERR(pcie->xtl), + "failed to map XTL-PRI memory\n"); + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return dev_err_probe(dev, -ENODEV, + "failed to get bus resources\n"); + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "ecam"); + if (!res) + return dev_err_probe(dev, -ENXIO, + "failed to get ECAM resource\n"); + + pcie->icc_path =3D devm_of_icc_get(dev, "write"); + if (IS_ERR(pcie->icc_path)) + return dev_err_probe(dev, PTR_ERR(pcie->icc_path), + "failed to get ICC\n"); + + pcie->bpmp =3D tegra_bpmp_get_with_id(dev, &pcie->ctl_id); + if (IS_ERR(pcie->bpmp)) + return dev_err_probe(dev, PTR_ERR(pcie->bpmp), + "failed to get BPMP\n"); + + err =3D devm_pm_runtime_set_active_enabled(dev); + if (err < 0) { + dev_err_probe(dev, err, "failed to enable runtime PM\n"); + goto err_put_bpmp; + } + + err =3D pm_runtime_get_sync(dev); + if (err < 0) { + dev_err_probe(dev, err, "failed to power on device\n"); + goto err_put_bpmp; + } + + /* sanity check that programmed ranges match what's in DT */ + if (!tegra264_pcie_check_ranges(pdev)) { + err =3D -EINVAL; + goto err_put_pm; + } + + pcie->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) { + err =3D dev_err_probe(dev, PTR_ERR(pcie->cfg), + "failed to create ECAM\n"); + goto err_put_pm; + } + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + bridge->sysdata =3D pcie->cfg; + pcie->ecam =3D pcie->cfg->win; + + tegra264_pcie_init(pcie); + + /* + * Fail if the link isn't up and doesn't support hotplug, no device + * will ever be able to be added on this bus. + */ + if (!pcie->link_up && !pcie->supports_hotplug) { + err =3D dev_err_probe(pcie->dev, -ENODEV, + "PCIe #%u link is down and not hotplug-capable, turning off\n", + pcie->ctl_id); + tegra264_pcie_power_off(pcie); + goto err_free_ecam; + } + + err =3D pci_host_probe(bridge); + if (err < 0) { + dev_err_probe(dev, err, "failed to register host\n"); + goto err_free_ecam; + } + + return 0; + +err_free_ecam: + pci_ecam_free(pcie->cfg); +err_put_pm: + pm_runtime_put_sync(dev); +err_put_bpmp: + tegra_bpmp_put(pcie->bpmp); + + return err; +} + +static void tegra264_pcie_remove(struct platform_device *pdev) +{ + struct tegra264_pcie *pcie =3D platform_get_drvdata(pdev); + + /* + * If we undo tegra264_pcie_init() then link goes down and need + * controller reset to bring up the link again. Remove intention is + * to clean up the root bridge and re-enumerate during bind. + */ + pci_lock_rescan_remove(); + pci_stop_root_bus(pcie->bridge->bus); + pci_remove_root_bus(pcie->bridge->bus); + pci_unlock_rescan_remove(); + + pm_runtime_put_sync(&pdev->dev); + tegra_bpmp_put(pcie->bpmp); + pci_ecam_free(pcie->cfg); +} + +static int tegra264_pcie_suspend(struct device *dev) +{ + /* + * No need to do anything device-specific here, BPMP handles the + * details of taking the link into L2. + */ + + return pinctrl_pm_select_sleep_state(dev); +} + +static int tegra264_pcie_resume(struct device *dev) +{ + struct tegra264_pcie *pcie =3D dev_get_drvdata(dev); + int err; + + err =3D pinctrl_pm_select_default_state(dev); + if (err < 0) { + dev_err(dev, "failed to configure sideband pins: %pe\n", + ERR_PTR(err)); + return err; + } + + tegra264_pcie_init(pcie); + + return 0; +} + +static DEFINE_SIMPLE_DEV_PM_OPS(tegra264_pcie_pm_ops, + tegra264_pcie_suspend, + tegra264_pcie_resume); + +static const struct of_device_id tegra264_pcie_of_match[] =3D { + { + .compatible =3D "nvidia,tegra264-pcie", + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, tegra264_pcie_of_match); + +static struct platform_driver tegra264_pcie_driver =3D { + .probe =3D tegra264_pcie_probe, + .remove =3D tegra264_pcie_remove, + .driver =3D { + .name =3D "tegra264-pcie", + .pm =3D pm_ptr(&tegra264_pcie_pm_ops), + .of_match_table =3D tegra264_pcie_of_match, + }, +}; +module_platform_driver(tegra264_pcie_driver); + +MODULE_AUTHOR("Manikanta Maddireddy "); +MODULE_AUTHOR("Thierry Reding "); +MODULE_DESCRIPTION("NVIDIA Tegra264 PCIe host controller driver"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Mon Jul 27 18:59:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDA00437861; Thu, 16 Jul 2026 17:07:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; 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a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The ECAM region cannot be the first entry in the "reg" property, because in that case the unit-address wouldn't match the first entry. The order of the nodes can also not be changed to match the ECAM entry because the ECAM region is global and outside of any of the control busses. Acked-by: Manivannan Sadhasivam Signed-off-by: Thierry Reding --- Changes in v8: - add Acked-by from Manivannan Changes in v5: - rebase onto v7.1-rc1 Changes in v4: - revert ECAM "reg" entry order Changes in v2: - order ECAM "reg" entry before others --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 48 ++++++++++++++++------------= ---- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 133d1156ee81..5008bf05d268 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3513,11 +3513,11 @@ cmdqv4: cmdqv@b200000 { =20 pci@c000000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xd0 0xb0000000 0x0 0x10000000>, - <0x00 0x0c000000 0x0 0x00004000>, + reg =3D <0x00 0x0c000000 0x0 0x00004000>, <0x00 0x0c004000 0x0 0x00001000>, - <0x00 0x0c005000 0x0 0x00001000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri"; + <0x00 0x0c005000 0x0 0x00001000>, + <0xd0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3893,12 +3893,12 @@ gpio_uphy: gpio@8300000 { =20 pci@8400000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xa8 0xb0000000 0x0 0x10000000>, - <0x00 0x08400000 0x0 0x00004000>, + reg =3D <0x00 0x08400000 0x0 0x00004000>, <0x00 0x08404000 0x0 0x00001000>, <0x00 0x08405000 0x0 0x00001000>, - <0x00 0x08410000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08410000 0x0 0x00010000>, + <0xa8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3925,12 +3925,12 @@ pci@8400000 { =20 pci@8420000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xb0 0xb0000000 0x0 0x10000000>, - <0x00 0x08420000 0x0 0x00004000>, + reg =3D <0x00 0x08420000 0x0 0x00004000>, <0x00 0x08424000 0x0 0x00001000>, <0x00 0x08425000 0x0 0x00001000>, - <0x00 0x08430000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08430000 0x0 0x00010000>, + <0xb0 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3957,12 +3957,12 @@ pci@8420000 { =20 pci@8440000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xb8 0xb0000000 0x0 0x10000000>, - <0x00 0x08440000 0x0 0x00004000>, + reg =3D <0x00 0x08440000 0x0 0x00004000>, <0x00 0x08444000 0x0 0x00001000>, <0x00 0x08445000 0x0 0x00001000>, - <0x00 0x08450000 0x0 0x00010000>; - reg-names =3D "ecam", "xal", "xtl", "xtl-pri", "xpl"; + <0x00 0x08450000 0x0 0x00010000>, + <0xb8 0xb0000000 0x0 0x10000000>; + reg-names =3D "xal", "xtl", "xtl-pri", "xpl", "ecam"; #address-cells =3D <3>; #size-cells =3D <2>; device_type =3D "pci"; @@ -3989,12 +3989,12 @@ pci@8440000 { =20 pci@8460000 { compatible =3D "nvidia,tegra264-pcie"; - reg =3D <0xc0 0xb0000000 0x0 0x10000000>, - <0x00 0x08460000 0x0 0x00004000>, + reg =3D <0x00 0x08460000 0x0 0x00004000>, <0x00 0x08464000 0x0 0x00001000>, <0x00 0x08465000 0x0 0x00001000>, - <0x00 0x08470000 0x0 0x00010000>; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260716-tegra264-pcie-v8-6-23e51589229b@nvidia.com> References: <20260716-tegra264-pcie-v8-0-23e51589229b@nvidia.com> In-Reply-To: <20260716-tegra264-pcie-v8-0-23e51589229b@nvidia.com> To: Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Karthikeyan Mitran , Hou Zhiqiang , Thomas Petazzoni , =?utf-8?q?Pali_Roh=C3=A1r?= , Michal Simek , Kevin Xie , Thierry Reding , Aksh Garg Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thierry Reding X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4510; i=treding@nvidia.com; h=from:subject:message-id; bh=rmyUx6u3OZmVAXG46//PWujiPHCV2TJ7sHTZv11zOUc=; b=owEBbQKS/ZANAwAKAd0jrNd/PrOhAcsmYgBqWQ/RKZi+YZ6sfUHnc60Jc4EKA0uqTHbFQrDG7 7eQ94rw0keJAjMEAAEKAB0WIQSI6sMIAUnM98CNyJ/dI6zXfz6zoQUCalkP0QAKCRDdI6zXfz6z oZCDEACDc9shAu8gXwsqaWkU9lJOMUH6H2Lwb+cIWkc1ZvYhWwDKOg9M/jNb5SK9ojZt1FyaHna 6V11VIRCWPz10X9u+or4jBNwLX5uFFMGlUXk6tCio4svydHKKgvSFMm9ZTXu3NM1Tz+39OhCwFK uEJmoTrmkbfc8aiRKuFiynAXcv4LKatibUctE1jtEhQ9+v54NDxzZJ5WqJ60131SgIlagkXDEHo ppXSk98T2j6eOGSYe06YIvN50XAj00qKP4eNZrpb9J1nlD6lM5bggoz64t5HZnCNGcGi47ByCbB r4+vCQnw1o4APbPYsTOdoQjbZ/axGkFEwUuXThfn+mfLoouNhv2y+TMexD44wS6xhLaAXhraDxJ pQoN2tHiCq5W/OnHYrcBNidKPH/kqttuKUtICNwza4ygF4dWjASc/GLF71LVM1a92dMY6OJUHdC J79i/j4OCknRijCrBjMaEEGTVkj50aESiuE/X6Nd1oSCfG0f6PKlI6GnN4pFoalATajSMU1eGGw DvuRPVIkVWbh63TacYErC8XQ1Ljob2zaintxj7ZsdWasmQnWbjH/fOgJBoAZYoVYhcDn/SNiPEh Xinwb968teUFHSCkXyMS0E2rrx1q9iQ8FBJxR4fcjVh37BxCBsQbrjuEPjbC9IdCZO8KtPHnw7I iZIBcXNU2XO+LUA== X-Developer-Key: i=treding@nvidia.com; a=openpgp; fpr=88EAC3080149CCF7C08DC89FDD23ACD77F3EB3A1 From: Thierry Reding The bindings have been updated to use the PCIe root port bindings, so the nodes for the root ports must be added. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 66 ++++++++++++++++++++++++++++= +--- 1 file changed, 60 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts= /nvidia/tegra264.dtsi index 5008bf05d268..1a1a741bfc79 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3537,10 +3537,19 @@ pci@c000000 { ranges =3D <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-= prefetchable memory (128 MiB) */ <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x0 0xff>; =20 nvidia,bpmp =3D <&bpmp 0>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 gpio_main: gpio@c300000 { @@ -3917,10 +3926,19 @@ pci@8400000 { ranges =3D <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 1>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8420000 { @@ -3949,10 +3967,19 @@ pci@8420000 { ranges =3D <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 2>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8440000 { @@ -3981,10 +4008,19 @@ pci@8440000 { ranges =3D <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 3>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8460000 { @@ -4013,10 +4049,19 @@ pci@8460000 { ranges =3D <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 4>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; =20 pci@8480000 { @@ -4045,10 +4090,19 @@ pci@8480000 { ranges =3D <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>= , /* I/O */ <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-= prefetchable memory */ <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* pref= etchable memory */ - bus-range =3D <0x00 0xff>; =20 nvidia,bpmp =3D <&bpmp 5>; status =3D "disabled"; + + pcie@0 { + device_type =3D "pci"; + compatible =3D "pciclass,0604"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; }; }; =20 --=20 2.54.0