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Signed-off-by: Jagadeesh Kona --- .../bindings/clock/qcom,sm8450-videocc.yaml | 2 + include/dt-bindings/clock/qcom,maili-videocc.h | 49 ++++++++++++++++++= ++++ 2 files changed, 51 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.ya= ml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 1e1fec1cd7ce96f103348baf85341e775fac690a..910c6d5672b8657f161058c4ceb= a98637c299b73 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -18,6 +18,7 @@ description: | include/dt-bindings/clock/qcom,glymur-videocc.h include/dt-bindings/clock/qcom,hawi-videocc.h include/dt-bindings/clock/qcom,kaanapali-videocc.h + include/dt-bindings/clock/qcom,maili-videocc.h include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h @@ -29,6 +30,7 @@ properties: - qcom,glymur-videocc - qcom,hawi-videocc - qcom,kaanapali-videocc + - qcom,maili-videocc - qcom,sm8450-videocc - qcom,sm8475-videocc - qcom,sm8550-videocc diff --git a/include/dt-bindings/clock/qcom,maili-videocc.h b/include/dt-bi= ndings/clock/qcom,maili-videocc.h new file mode 100644 index 0000000000000000000000000000000000000000..ae52686639db3231b8705e28667= d3a65192d4de7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,maili-videocc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_MAILI_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_AHB_CLK 0 +#define VIDEO_CC_AHB_CLK_SRC 1 +#define VIDEO_CC_MVS0_CLK 2 +#define VIDEO_CC_MVS0_CLK_SRC 3 +#define VIDEO_CC_MVS0_FREERUN_CLK 4 +#define VIDEO_CC_MVS0_SHIFT_CLK 5 +#define VIDEO_CC_MVS0_VPP0_CLK 6 +#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK 7 +#define VIDEO_CC_MVS0B_CLK 8 +#define VIDEO_CC_MVS0B_CLK_SRC 9 +#define VIDEO_CC_MVS0B_FREERUN_CLK 10 +#define VIDEO_CC_MVS0C_CLK 11 +#define VIDEO_CC_MVS0C_CLK_SRC 12 +#define VIDEO_CC_MVS0C_DEBUG_CLK 13 +#define VIDEO_CC_MVS0C_FREERUN_CLK 14 +#define VIDEO_CC_MVS0C_SHIFT_CLK 15 +#define VIDEO_CC_PLL0 16 +#define VIDEO_CC_PLL1 17 +#define VIDEO_CC_PLL2 18 +#define VIDEO_CC_SLEEP_CLK 19 +#define VIDEO_CC_XO_CLK 20 +#define VIDEO_CC_XO_CLK_SRC 21 + +/* VIDEO_CC power domains */ +#define VIDEO_CC_MVS0_GDSC 0 +#define VIDEO_CC_MVS0_VPP0_GDSC 1 +#define VIDEO_CC_MVS0C_GDSC 2 + +/* VIDEO_CC resets */ +#define VIDEO_CC_INTERFACE_BCR 0 +#define VIDEO_CC_MVS0_BCR 1 +#define VIDEO_CC_MVS0_CLK_ARES 2 +#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 3 +#define VIDEO_CC_MVS0_VPP0_BCR 4 +#define VIDEO_CC_MVS0C_BCR 5 +#define VIDEO_CC_MVS0C_CLK_ARES 6 +#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 7 +#define VIDEO_CC_XO_CLK_ARES 8 + +#endif --=20 2.34.1 From nobody Sat Jul 25 16:20:10 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CF4F19D89E for ; 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Wed, 15 Jul 2026 21:08:17 -0700 (PDT) Received: from hu-jkona-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3140e6a4779sm7623907eec.17.2026.07.15.21.08.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 21:08:17 -0700 (PDT) From: Jagadeesh Kona Date: Thu, 16 Jul 2026 09:38:00 +0530 Subject: [PATCH v2 2/2] clk: qcom: Add support for videocc driver on Qualcomm Maili SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260716-maili_videocc-v2-2-7ed5ab140770@oss.qualcomm.com> References: <20260716-maili_videocc-v2-0-7ed5ab140770@oss.qualcomm.com> In-Reply-To: <20260716-maili_videocc-v2-0-7ed5ab140770@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Jagadeesh Kona Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jagadeesh Kona , Konrad Dybcio X-Mailer: b4 0.14.2 X-Proofpoint-GUID: c-aSHUQiI_4byn7tb016aQYPg7fdw4fE X-Authority-Analysis: v=2.4 cv=KOlqylFo c=1 sm=1 tr=0 ts=6a585933 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=F0qgNhY56VeKpUo0egcA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE2MDAzOCBTYWx0ZWRfX8Gf7hcUJBuIJ WVn7c8/dRB79bmdp1Xzkh6gut3+8NRGVRRO/FpaljbbjFtbY4B+l+uBYoPs7Tg7dMRTGuej+dSO 3/koiM2VEE7URttormJplk8v6xFVDPB6CNDvBVDh0t812qSzAHSsWqtmUUyOL1+nLn8gg0+PnxJ ZzW1sfJPSfa/8R0k61Dj/2IVGTyfljcEFJE52PzF9/Vn2AmHP3pq02HcXJIDo6Fx0TVDJF0YAWg P2t9QSR5UKmoEvmzZM1iLy5ZVbDuBCegHBR5eNZrIPv55QSYjrbbvNDVapMmAYF/02EqvgZhKqH SNlI5fJahUO9pi4qd0jfM+v5UJ7ZvwJ0lkDVxEaYHlKCjm4yNAmorBM2+h8DadGH8R8Bd5UDLv8 fYiY+nK25IM1Tgp/xBqOZFhtKfAfJ6pN58OFFcDjHESWpdWLNqjtYf7+quzn8Jtwl6xjBGqL3jr nti+YKwtwYeFzkA2EKw== X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE2MDAzOCBTYWx0ZWRfX/EsIU8aWHSt0 UW1oYHLZ/WbFxTDqCV+EnT2vpV8UTME4XPPBzXo+AUQhKXciIiOG5zfuGzaxNQ2r/GUA/oe4Vlg OILKWaNQ6P65YO+jHje5HrFxlDcxW/Y= X-Proofpoint-ORIG-GUID: c-aSHUQiI_4byn7tb016aQYPg7fdw4fE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-16_02,2026-07-15_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607160038 Add support for Qualcomm Maili video clock controller driver for video clients to be able to request for videocc clocks. Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Reviewed-by: Taniya Das --- drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/videocc-maili.c | 660 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 671 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 63f271aff1771bea0885fb753dd28d02fd7d4ab6..690f0b6fe227ca449274d3606f7= ca6a9da23a5ab 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -181,6 +181,16 @@ config CLK_KAANAPALI_VIDEOCC Say Y if you want to support video devices and functionality such as video encode/decode. =20 +config CLK_MAILI_VIDEOCC + tristate "Maili Video Clock Controller" + depends on ARM64 || COMPILE_TEST + select CLK_HAWI_GCC + default m if ARCH_QCOM + help + Support for the video clock controller on Maili devices. + Say Y if you want to support video devices and functionality such as + video encode/decode. + config CLK_NORD_GCC tristate "Nord Global Clock Controller" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index db7689ee5dc63bc8b7d12b8222188bc1e1ff78ba..bb5e3dc7073340f895d3e1108f2= 43c8d66b84b4f 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_CLK_KAANAPALI_GCC) +=3D gcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_GPUCC) +=3D gpucc-kaanapali.o gxclkctl-kaanapal= i.o obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) +=3D tcsrcc-kaanapali.o obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) +=3D videocc-kaanapali.o +obj-$(CONFIG_CLK_MAILI_VIDEOCC) +=3D videocc-maili.o obj-$(CONFIG_CLK_NORD_GCC) +=3D gcc-nord.o negcc-nord.o nwgcc-nord.o segcc= -nord.o obj-$(CONFIG_CLK_NORD_TCSRCC) +=3D tcsrcc-nord.o obj-$(CONFIG_CLK_SHIKRA_GCC) +=3D gcc-shikra.o diff --git a/drivers/clk/qcom/videocc-maili.c b/drivers/clk/qcom/videocc-ma= ili.c new file mode 100644 index 0000000000000000000000000000000000000000..640c1802f4ace38d3568df70043= dc20fa8ce6a7b --- /dev/null +++ b/drivers/clk/qcom/videocc-maili.c @@ -0,0 +1,660 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "common.h" +#include "gdsc.h" +#include "reset.h" + +#define ACCU_CFG_MASK GENMASK(25, 21) + +enum { + DT_BI_TCXO, + DT_AHB_CLK, +}; + +enum { + P_BI_TCXO, + P_VIDEO_CC_PLL0_OUT_MAIN, + P_VIDEO_CC_PLL1_OUT_MAIN, + P_VIDEO_CC_PLL2_OUT_MAIN, +}; + +static const struct pll_vco taycan_eha_t_vco[] =3D { + { 249600000, 2500000000, 0 }, +}; + +/* 360.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll0_config =3D { + .l =3D 0x12, + .cal_l =3D 0x42, + .alpha =3D 0xc000, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a806160, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll0 =3D { + .offset =3D 0x0, + .config =3D &video_cc_pll0_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll0", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll1_config =3D { + .l =3D 0x19, + .cal_l =3D 0x42, + .alpha =3D 0x0, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a806160, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll1 =3D { + .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll1", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +/* 480.0 MHz Configuration */ +static const struct alpha_pll_config video_cc_pll2_config =3D { + .l =3D 0x19, + .cal_l =3D 0x42, + .alpha =3D 0x0, + .config_ctl_val =3D 0xa5c400e7, + .config_ctl_hi_val =3D 0x0a806160, + .config_ctl_hi1_val =3D 0xf51dea20, + .user_ctl_val =3D 0x00000000, + .user_ctl_hi_val =3D 0x00000002, +}; + +static struct clk_alpha_pll video_cc_pll2 =3D { + .offset =3D 0x2000, + .config =3D &video_cc_pll2_config, + .vco_table =3D taycan_eha_t_vco, + .num_vco =3D ARRAY_SIZE(taycan_eha_t_vco), + .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EHA_T], + .clkr =3D { + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_pll2", + .parent_data =3D &(const struct clk_parent_data) { + .index =3D DT_BI_TCXO, + }, + .num_parents =3D 1, + .ops =3D &clk_alpha_pll_taycan_eha_t_ops, + }, + }, +}; + +static const struct parent_map video_cc_parent_map_0[] =3D { + { P_BI_TCXO, 0 }, +}; + +static const struct clk_parent_data video_cc_parent_data_0[] =3D { + { .index =3D DT_BI_TCXO }, +}; + +static const struct parent_map video_cc_parent_map_1[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL1_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_1[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll1.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_2[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL2_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_2[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll2.clkr.hw }, +}; + +static const struct parent_map video_cc_parent_map_3[] =3D { + { P_BI_TCXO, 0 }, + { P_VIDEO_CC_PLL0_OUT_MAIN, 1 }, +}; + +static const struct clk_parent_data video_cc_parent_data_3[] =3D { + { .index =3D DT_BI_TCXO }, + { .hw =3D &video_cc_pll0.clkr.hw }, +}; + +static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] =3D { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_ahb_clk_src =3D { + .cmd_rcgr =3D 0x8060, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_ahb_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(600000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(800000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + F(1000000000, P_VIDEO_CC_PLL1_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0_clk_src =3D { + .cmd_rcgr =3D 0x8030, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_1, + .freq_tbl =3D ftbl_video_cc_mvs0_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk_src", + .parent_data =3D video_cc_parent_data_1, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_1), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0b_clk_src[] =3D { + F(240000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(338000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(420000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(444000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(533000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(630000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + F(800000000, P_VIDEO_CC_PLL2_OUT_MAIN, 2, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0b_clk_src =3D { + .cmd_rcgr =3D 0x8018, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_2, + .freq_tbl =3D ftbl_video_cc_mvs0b_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_clk_src", + .parent_data =3D video_cc_parent_data_2, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_2), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static const struct freq_tbl ftbl_video_cc_mvs0c_clk_src[] =3D { + F(360000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(507000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(630000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(666000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(800000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1104000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0), + { } +}; + +static struct clk_rcg2 video_cc_mvs0c_clk_src =3D { + .cmd_rcgr =3D 0x8048, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_3, + .freq_tbl =3D ftbl_video_cc_mvs0c_clk_src, + .hw_clk_ctrl =3D true, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk_src", + .parent_data =3D video_cc_parent_data_3, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_3), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_shared_ops, + }, +}; + +static struct clk_rcg2 video_cc_xo_clk_src =3D { + .cmd_rcgr =3D 0x8194, + .mnd_width =3D 0, + .hid_width =3D 5, + .parent_map =3D video_cc_parent_map_0, + .freq_tbl =3D ftbl_video_cc_ahb_clk_src, + .clkr.hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_xo_clk_src", + .parent_data =3D video_cc_parent_data_0, + .num_parents =3D ARRAY_SIZE(video_cc_parent_data_0), + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_rcg2_ops, + }, +}; + +static struct clk_branch video_cc_mvs0_clk =3D { + .halt_reg =3D 0x80d0, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80d0, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80d0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_mem_branch video_cc_mvs0_freerun_clk =3D { + .mem_enable_reg =3D 0x80e4, + .mem_ack_reg =3D 0x80e4, + .mem_enable_mask =3D BIT(3), + .mem_enable_ack_mask =3D 0xc00, + .mem_enable_invert =3D true, + .branch =3D { + .halt_reg =3D 0x80e0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80e0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_mem_ops, + }, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_shift_clk =3D { + .halt_reg =3D 0x81b4, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81b4, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81b4, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp0_clk =3D { + .halt_reg =3D 0x8134, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8134, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8134, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp0_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0_vpp0_freerun_clk =3D { + .halt_reg =3D 0x8144, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8144, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0_vpp0_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0b_clk =3D { + .halt_reg =3D 0x80bc, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x80bc, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x80bc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0b_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0b_freerun_clk =3D { + .halt_reg =3D 0x80cc, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x80cc, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0b_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0b_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_clk =3D { + .halt_reg =3D 0x8164, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x8164, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x8164, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_debug_clk =3D { + .halt_reg =3D 0x81c0, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x81c0, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_debug_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_freerun_clk =3D { + .halt_reg =3D 0x8174, + .halt_check =3D BRANCH_HALT, + .clkr =3D { + .enable_reg =3D 0x8174, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_freerun_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_mvs0c_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch video_cc_mvs0c_shift_clk =3D { + .halt_reg =3D 0x81b8, + .halt_check =3D BRANCH_HALT_VOTED, + .hwcg_reg =3D 0x81b8, + .hwcg_bit =3D 1, + .clkr =3D { + .enable_reg =3D 0x81b8, + .enable_mask =3D BIT(0), + .hw.init =3D &(const struct clk_init_data) { + .name =3D "video_cc_mvs0c_shift_clk", + .parent_hws =3D (const struct clk_hw*[]) { + &video_cc_xo_clk_src.clkr.hw, + }, + .num_parents =3D 1, + .flags =3D CLK_SET_RATE_PARENT, + .ops =3D &clk_branch2_ops, + }, + }, +}; + +static struct gdsc video_cc_mvs0c_gdsc =3D { + .gdscr =3D 0x814c, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0c_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_gdsc =3D { + .gdscr =3D 0x80a8, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0x6, + .pd =3D { + .name =3D "video_cc_mvs0_gdsc", + }, + .parent =3D &video_cc_mvs0c_gdsc.pd, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct gdsc video_cc_mvs0_vpp0_gdsc =3D { + .gdscr =3D 0x8120, + .en_rest_wait_val =3D 0x2, + .en_few_wait_val =3D 0x2, + .clk_dis_wait_val =3D 0xf, + .pd =3D { + .name =3D "video_cc_mvs0_vpp0_gdsc", + }, + .pwrsts =3D PWRSTS_OFF_ON, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, +}; + +static struct clk_regmap *video_cc_maili_clocks[] =3D { + [VIDEO_CC_AHB_CLK_SRC] =3D &video_cc_ahb_clk_src.clkr, + [VIDEO_CC_MVS0_CLK] =3D &video_cc_mvs0_clk.clkr, + [VIDEO_CC_MVS0_CLK_SRC] =3D &video_cc_mvs0_clk_src.clkr, + [VIDEO_CC_MVS0_FREERUN_CLK] =3D &video_cc_mvs0_freerun_clk.branch.clkr, + [VIDEO_CC_MVS0_SHIFT_CLK] =3D &video_cc_mvs0_shift_clk.clkr, + [VIDEO_CC_MVS0_VPP0_CLK] =3D &video_cc_mvs0_vpp0_clk.clkr, + [VIDEO_CC_MVS0_VPP0_FREERUN_CLK] =3D &video_cc_mvs0_vpp0_freerun_clk.clkr, + [VIDEO_CC_MVS0B_CLK] =3D &video_cc_mvs0b_clk.clkr, + [VIDEO_CC_MVS0B_CLK_SRC] =3D &video_cc_mvs0b_clk_src.clkr, + [VIDEO_CC_MVS0B_FREERUN_CLK] =3D &video_cc_mvs0b_freerun_clk.clkr, + [VIDEO_CC_MVS0C_CLK] =3D &video_cc_mvs0c_clk.clkr, + [VIDEO_CC_MVS0C_CLK_SRC] =3D &video_cc_mvs0c_clk_src.clkr, + [VIDEO_CC_MVS0C_DEBUG_CLK] =3D &video_cc_mvs0c_debug_clk.clkr, + [VIDEO_CC_MVS0C_FREERUN_CLK] =3D &video_cc_mvs0c_freerun_clk.clkr, + [VIDEO_CC_MVS0C_SHIFT_CLK] =3D &video_cc_mvs0c_shift_clk.clkr, + [VIDEO_CC_PLL0] =3D &video_cc_pll0.clkr, + [VIDEO_CC_PLL1] =3D &video_cc_pll1.clkr, + [VIDEO_CC_PLL2] =3D &video_cc_pll2.clkr, + [VIDEO_CC_XO_CLK_SRC] =3D &video_cc_xo_clk_src.clkr, +}; + +static struct gdsc *video_cc_maili_gdscs[] =3D { + [VIDEO_CC_MVS0_GDSC] =3D &video_cc_mvs0_gdsc, + [VIDEO_CC_MVS0_VPP0_GDSC] =3D &video_cc_mvs0_vpp0_gdsc, + [VIDEO_CC_MVS0C_GDSC] =3D &video_cc_mvs0c_gdsc, +}; + +static const struct qcom_reset_map video_cc_maili_resets[] =3D { + [VIDEO_CC_INTERFACE_BCR] =3D { 0x8178 }, + [VIDEO_CC_MVS0_BCR] =3D { 0x80a4 }, + [VIDEO_CC_MVS0_CLK_ARES] =3D { 0x80d0, 2 }, + [VIDEO_CC_MVS0_FREERUN_CLK_ARES] =3D { 0x80e0, 2 }, + [VIDEO_CC_MVS0_VPP0_BCR] =3D { 0x811c }, + [VIDEO_CC_MVS0C_BCR] =3D { 0x8148 }, + [VIDEO_CC_MVS0C_CLK_ARES] =3D { 0x8164, 2 }, + [VIDEO_CC_MVS0C_FREERUN_CLK_ARES] =3D { 0x8174, 2 }, + [VIDEO_CC_XO_CLK_ARES] =3D { 0x81ac, 2 }, +}; + +static struct clk_alpha_pll *video_cc_maili_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, + &video_cc_pll2, +}; + +static const u32 video_cc_maili_critical_cbcrs[] =3D { + 0x817c, /* VIDEO_CC_AHB_CLK */ + 0x81bc, /* VIDEO_CC_SLEEP_CLK */ + 0x81b0, /* VIDEO_CC_TS_XO_CLK */ + 0x81ac, /* VIDEO_CC_XO_CLK */ +}; + +static const struct regmap_config video_cc_maili_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xa010, + .fast_io =3D true, +}; + +static void clk_maili_regs_configure(struct device *dev, struct regmap *re= gmap) +{ + /* + * Enable clk_on sync for MVS0 and VPP clocks as per the + * hardware recommendation. + */ + regmap_set_bits(regmap, 0x9f24, BIT(0)); + + /* + * Update ACCU configuration for MVS0 CFG3, MVS0 VPP0 CFG3, + * MVS0C CFG3 GDSCRs as per the hardware recommendation. + */ + regmap_set_bits(regmap, 0x80b4, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x812c, ACCU_CFG_MASK); + regmap_set_bits(regmap, 0x8158, ACCU_CFG_MASK); +} + +static const struct qcom_cc_driver_data video_cc_maili_driver_data =3D { + .alpha_plls =3D video_cc_maili_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_maili_plls), + .clk_cbcrs =3D video_cc_maili_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_maili_critical_cbcrs), + .clk_regs_configure =3D clk_maili_regs_configure, +}; + +static const struct qcom_cc_desc video_cc_maili_desc =3D { + .config =3D &video_cc_maili_regmap_config, + .clks =3D video_cc_maili_clocks, + .num_clks =3D ARRAY_SIZE(video_cc_maili_clocks), + .resets =3D video_cc_maili_resets, + .num_resets =3D ARRAY_SIZE(video_cc_maili_resets), + .gdscs =3D video_cc_maili_gdscs, + .num_gdscs =3D ARRAY_SIZE(video_cc_maili_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_maili_driver_data, +}; + +static const struct of_device_id video_cc_maili_match_table[] =3D { + { .compatible =3D "qcom,maili-videocc" }, + { } +}; +MODULE_DEVICE_TABLE(of, video_cc_maili_match_table); + +static int video_cc_maili_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &video_cc_maili_desc); +} + +static struct platform_driver video_cc_maili_driver =3D { + .probe =3D video_cc_maili_probe, + .driver =3D { + .name =3D "videocc-maili", + .of_match_table =3D video_cc_maili_match_table, + }, +}; + +module_platform_driver(video_cc_maili_driver); + +MODULE_DESCRIPTION("QTI VIDEOCC Maili Driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1