From nobody Sat Jul 25 16:51:12 2026 Received: from mail.savoirfairelinux.com (mail.savoirfairelinux.com [208.88.110.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C31247ECDE for ; Wed, 15 Jul 2026 17:04:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=208.88.110.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784135060; cv=none; b=NTYgPjbs0Vi1O7cFNmkM55EMEomHEqOrDl16Mg3bWEe8nEAGuaAQVxIDNRmTM1Plx/rQ11U/s1Fszzf+9Gjg33lsIifdJ8TIIgfbWWV6HPscn0Sam3pEtSn+xEo42sIlwuqtxAzNfJ/joL2LB501M+PFf7e4MiJw3XrpY8Yq/xE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784135060; c=relaxed/simple; bh=nUcSpfywM3gIM41wXV525WBqz0XV130HsMgBTOjejTY=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=KkuNXpBzzqvUcZryZPQ4CoLPu8atuKh6lt4NluZHLfNzvCaSlo3cyK0VG5UEUrM0yBcXtbHyWILkgUazL59EIDO+eSO/13JAxpP3PkF1oXQWFPE0AtQKIgO7IdjEAmibwu9yziW+YnqZwjPoJ+NJkL4tF6fsjO5N/TABB9C3GxU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=savoirfairelinux.com; spf=pass smtp.mailfrom=savoirfairelinux.com; dkim=pass (2048-bit key) header.d=savoirfairelinux.com header.i=@savoirfairelinux.com header.b=hcEo4si5; arc=none smtp.client-ip=208.88.110.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=savoirfairelinux.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=savoirfairelinux.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=savoirfairelinux.com header.i=@savoirfairelinux.com header.b="hcEo4si5" Received: from localhost (localhost [127.0.0.1]) by mail.savoirfairelinux.com (Postfix) with ESMTP id 85BD83D818BB; Wed, 15 Jul 2026 13:04:09 -0400 (EDT) Received: from mail.savoirfairelinux.com ([127.0.0.1]) by localhost (mail.savoirfairelinux.com [127.0.0.1]) (amavis, port 10032) with ESMTP id 8bRpTJ-UL2Ue; Wed, 15 Jul 2026 13:04:08 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mail.savoirfairelinux.com (Postfix) with ESMTP id A8B7E3D818CB; Wed, 15 Jul 2026 13:04:08 -0400 (EDT) DKIM-Filter: OpenDKIM Filter v2.10.3 mail.savoirfairelinux.com A8B7E3D818CB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=savoirfairelinux.com; s=DFC430D2-D198-11EC-948E-34200CB392D2; t=1784135048; bh=phRdmR+70pHyH8tHcjItrzRd3pTCTqtMmmB5IErup7w=; h=From:To:Date:Message-ID:MIME-Version; b=hcEo4si5kIjpNDiQQr9YOJNAPWry9Hrqkuykgfea8cYMm9qeNI5NNIO2A8eYiPK2h zVG15unpuTSeS9aR+wNK90J+SPxlybsdYtNjZ94OPRv2puxoXmdwAghSbSU95t5hwr ENO12WNaAGrEMVDGfqJEOXKu2g4UAX0YiT3MgOprgZCANIeRMMmIROM+M3L1eMuF2C hAoeb1V9QpSHxzQFekf3yOxjhknwUP3eEW0DYn/OBBqPBR8qE7nD4bz7xCXaB9A7eI UccjbUSJotxKyhEHyjlrLXtqF7980q7lFsoT7ohCe2BHt6PP7yzNfB0/Dn0ZBGFVZC MnBhwArTEW8GQ== X-Virus-Scanned: amavis at mail.savoirfairelinux.com Received: from mail.savoirfairelinux.com ([127.0.0.1]) by localhost (mail.savoirfairelinux.com [127.0.0.1]) (amavis, port 10026) with ESMTP id SvJ-eMNLwVYJ; Wed, 15 Jul 2026 13:04:08 -0400 (EDT) Received: from MortyUbuntu.mtl.sfl (unknown [192.168.51.254]) by mail.savoirfairelinux.com (Postfix) with ESMTPSA id 6F4E03D818BB; Wed, 15 Jul 2026 13:04:08 -0400 (EDT) From: Abhishek Ojha To: Mark Brown Cc: Liam Girdwood , Tim Harvey , linux-kernel@vger.kernel.org, Abhishek Ojha Subject: [PATCH] regulator: ltc3676: Fix incorrect IRQSTAT bit offsets Date: Wed, 15 Jul 2026 13:04:08 -0400 Message-ID: <20260715170408.295552-1-Abhishek.ojha@savoirfairelinux.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The LTC3676_IRQSTAT_* bit definitions do not match the IRQSTAT (Interrupt Request Status) register layout documented in Table 15 of the LTC3676/LTC3676-1 datasheet: bit 0 - Pushbutton Status Active bit 1 - Hard Reset Occurred bit 2 - PGOOD Timeout Occurred bit 3 - Undervoltage Warning bit 4 - Undervoltage Standby (Fault) Occurred bit 5 - Overtemperature Warning bit 6 - Overtemperature Standby (Fault) Occurred bit 7 - Reserved The driver instead defines these starting at bit 3, one bit higher than the datasheet specifies, which causes ltc3676_regulator_isr() to check the wrong status bits and misreport (or miss) PGOOD timeout, undervoltage and thermal warning/fault conditions. Fix the bit offsets to match the datasheet. Fixes: 37b918a034fe ("regulator: Add LTC3676 support") Cc: stable@vger.kernel.org Signed-off-by: Abhishek Ojha --- drivers/regulator/ltc3676.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/regulator/ltc3676.c b/drivers/regulator/ltc3676.c index 73d511eb1c1d..768cdce0d4ec 100644 --- a/drivers/regulator/ltc3676.c +++ b/drivers/regulator/ltc3676.c @@ -45,11 +45,11 @@ #define LTC3676_DVBxA_REF_SELECT BIT(5) #define LTC3676_DVBxB_PGOOD_MASK BIT(5) =20 -#define LTC3676_IRQSTAT_PGOOD_TIMEOUT BIT(3) -#define LTC3676_IRQSTAT_UNDERVOLT_WARN BIT(4) -#define LTC3676_IRQSTAT_UNDERVOLT_FAULT BIT(5) -#define LTC3676_IRQSTAT_THERMAL_WARN BIT(6) -#define LTC3676_IRQSTAT_THERMAL_FAULT BIT(7) +#define LTC3676_IRQSTAT_PGOOD_TIMEOUT BIT(2) +#define LTC3676_IRQSTAT_UNDERVOLT_WARN BIT(3) +#define LTC3676_IRQSTAT_UNDERVOLT_FAULT BIT(4) +#define LTC3676_IRQSTAT_THERMAL_WARN BIT(5) +#define LTC3676_IRQSTAT_THERMAL_FAULT BIT(6) =20 enum ltc3676_reg { LTC3676_SW1, --=20 2.43.0