From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E08D5385516; Wed, 15 Jul 2026 14:28:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125739; cv=none; b=c63YeECp+hPlXrGBpb3AmlCNE1VtFmbr0WVn8DY1BxIdu6Yp98ho9yKiWl20QUCpIsHwtB9ByVw/7mVTWt73fW9AjMjIdoWaOc9buZ3kehe7yGZaeEtW1bJC2UVglo9RIWuPDZYmn3pKlGddvv8wb+C89ovFP5iMslJBuYBK3hk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125739; c=relaxed/simple; bh=4Tj9S5AJyJlT1xaoyFWjtSoFJSn54sEDNzeHR7ufHFU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cE6eQ0BoPVhQgH/Gnk5/w26UlHyN6Jdr7wuHOj9OBhvZ/EumSn1C0kODUvz4Z6sJQPjSkosU6NblT+FoxZ2KwkAvznPNB6RIkRMhd9bBzq66yssvowmDMLG++4CxWFzvbDtnnxG3AdZ/bJZi7uv5/jvSkLNA2xujr0gXCnqtGaY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=AGgi9AEH; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="AGgi9AEH" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 101581477; Wed, 15 Jul 2026 07:28:52 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7CF273F7B4; Wed, 15 Jul 2026 07:28:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125736; bh=4Tj9S5AJyJlT1xaoyFWjtSoFJSn54sEDNzeHR7ufHFU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AGgi9AEHA7f2kOodawl5beqTbd168vdiFCm1AADWFdxOQF7CShAqLREa2w1lLmq1h c9GzjLqoMGs4yK2l92M5lGMgbpJFV8qhuPWnw7SdU4SeoyMAGGLvPrjRPCcILxuLuL VG5vwogmXjqLuKkJQF7WyECCwTowcuLz9aw0Tiw0= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Suzuki K Poulose , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 01/37] KVM: arm64: Include kvm_emulate.h in kvm/arm_psci.h Date: Wed, 15 Jul 2026 15:28:03 +0100 Message-ID: <20260715142841.80544-2-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Suzuki K Poulose Fix a potential build error (like below, when asm/kvm_emulate.h gets included after the kvm/arm_psci.h) by including the missing header file in kvm/arm_psci.h: ./include/kvm/arm_psci.h: In function =E2=80=98kvm_psci_version=E2=80=99: ./include/kvm/arm_psci.h:29:13: error: implicit declaration of function =E2=80=98vcpu_has_feature=E2=80=99; did you mean =E2=80=98cpu_have_featu= re=E2=80=99? [-Werror=3Dimplicit-function-declaration] 29 | if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PSCI_0_2)) { | ^~~~~~~~~~~~~~~~ | cpu_have_feature Reviewed-by: Gavin Shan Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price --- include/kvm/arm_psci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kvm/arm_psci.h b/include/kvm/arm_psci.h index cbaec804eb83..38dab7add79b 100644 --- a/include/kvm/arm_psci.h +++ b/include/kvm/arm_psci.h @@ -10,6 +10,8 @@ #include #include =20 +#include + #define KVM_ARM_PSCI_0_1 PSCI_VERSION(0, 1) #define KVM_ARM_PSCI_0_2 PSCI_VERSION(0, 2) #define KVM_ARM_PSCI_1_0 PSCI_VERSION(1, 0) --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC321385D9B; Wed, 15 Jul 2026 14:29:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125743; cv=none; b=AHqr3Jkm80TBOezshlKVfCvpq+6bBLgvU6JfRoZQWVA2IMG5eOvYMxQtEcUBmzMeR2RIHe2AEgFGKS9f6KLarOAkXBFIQgnjRjo1LvxjZNo5lRSyIfpDGXniZk8dw5zlmpXuC7GtX0Kxcwze9qe0O2zudJDAUl2Bbh6LX8f+q2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125743; c=relaxed/simple; bh=1I4ZI4mnm0aIoXu8l8WkH3buhipIX//+u9eyiE9fI5I=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rQt+8N1P132cY/3mbLcbAdpNaRrUic5JVncS83DPhvs6mdRcs07PhkqdZEunKGiM+9ymJq9KjlwFsEFnMYMfNOvPz/5b8uAL1FDywFaCXYDjdX+cy1lj12d7Bc3Q/ZJDUo6hH/u0PbphUgiAsPT98r1Nb2uC/bw4tKJiTBr2mXQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=AwVBy8N1; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="AwVBy8N1" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 18E8C153B; Wed, 15 Jul 2026 07:28:57 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B0F503F7B4; Wed, 15 Jul 2026 07:28:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125741; bh=1I4ZI4mnm0aIoXu8l8WkH3buhipIX//+u9eyiE9fI5I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AwVBy8N1rIdV2rLo5OYmz8A21llJ/W4diYkyS25KkKmHGQuNQ4HjI5IL/AG56VI4d SLD5TXCP17t3DqHjpTGSfmaOcVJ2Efi7FpX2eDlxG7XQSDJMBTv3VGv87RCn7MNWqM ES5Cyz6q2QvmjlESxEEPk3y5k+lNXxlMYFEG/mEk= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 02/37] KVM: arm64: Avoid including linux/kvm_host.h in kvm_pgtable.h Date: Wed, 15 Jul 2026 15:28:04 +0100 Message-ID: <20260715142841.80544-3-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To avoid future include cycles, drop the linux/kvm_host.h include in kvm_pgtable.h and include the lightweight headers required for the types and inline helpers used there. Additionally provide a forward declaration for struct kvm_s2_mmu as it's only used as a pointer in this file. Both pgtable.c and kvm_pkvm.h relied on the indirect inclusion of kvm_host.h, so make that explicit. Signed-off-by: Steven Price --- New patch in v13 --- arch/arm64/include/asm/kvm_pgtable.h | 6 +++++- arch/arm64/include/asm/kvm_pkvm.h | 2 +- arch/arm64/kvm/hyp/pgtable.c | 1 + 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/= kvm_pgtable.h index 41a8687938eb..c2e4b29e605f 100644 --- a/arch/arm64/include/asm/kvm_pgtable.h +++ b/arch/arm64/include/asm/kvm_pgtable.h @@ -8,9 +8,13 @@ #define __ARM64_KVM_PGTABLE_H__ =20 #include -#include +#include +#include +#include #include =20 +struct kvm_s2_mmu; + #define KVM_PGTABLE_FIRST_LEVEL -1 #define KVM_PGTABLE_LAST_LEVEL 3 =20 diff --git a/arch/arm64/include/asm/kvm_pkvm.h b/arch/arm64/include/asm/kvm= _pkvm.h index 74fedd9c5ff0..a0f7a699d690 100644 --- a/arch/arm64/include/asm/kvm_pkvm.h +++ b/arch/arm64/include/asm/kvm_pkvm.h @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include =20 /* Maximum number of VMs that can co-exist under pKVM. */ diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c index 91a7dfad6686..3d608b7e0cf0 100644 --- a/arch/arm64/kvm/hyp/pgtable.c +++ b/arch/arm64/kvm/hyp/pgtable.c @@ -8,6 +8,7 @@ */ =20 #include +#include #include #include =20 --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 91EBD38837C; Wed, 15 Jul 2026 14:29:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125748; cv=none; b=BrJCXzwGly8CSZhtIxm1f2pNdZCQYOoiV7JOL1g1R7ZPseE4/Ac22+N3gOqItCn6CESHbznx3OhMCNhHdv61HlzbkAyduYDqRkxqQlUxVfadF9hdCxuZW5Q9UPRZJR8/DhD8HjN8l+jQZjSPZtRwo6oOe8TzR6LQo30AwmlcKTw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125748; c=relaxed/simple; bh=atB3+AUi+d6UB2ANLJFnJ3D22hkMovBf+VHS20wL0+U=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S2p3W8SZN+T+uvECsVohwKzu+3gi133jkXPUnZuY0ADzwO4pLIN2SdT+AfIlx9TdquIeY308GwGM3wYyefl5j9zxLk4dT8ev/YE6O374snfCPw5VETNkE7UYLJZIm00Ppsrgxfl2YqCb+7EfFI/OP6Ax6jDMBm4TI9gCwxAi5X4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=qKkUOszI; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="qKkUOszI" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DC229153B; Wed, 15 Jul 2026 07:29:02 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A60933F7B4; Wed, 15 Jul 2026 07:29:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125747; bh=atB3+AUi+d6UB2ANLJFnJ3D22hkMovBf+VHS20wL0+U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qKkUOszIIQxlaCE9w9AlUV4y2niUW0T0eJaCd59109QYbgs7Smw44s254HJKFrtsL v+133ew0exD0UcdaNszIuGGnTguZkA/+Nq2Z6j0/Ks4YQjonpY160+Sn8dDcZeNrqc iYZ784cvyMggK59aEpw9PfQ/SBnIYdTWKGETSif0= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 03/37] arm64: mm: Handle Granule Protection Faults (GPFs) Date: Wed, 15 Jul 2026 15:28:05 +0100 Message-ID: <20260715142841.80544-4-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If the host attempts to access granules that have been delegated for use in a realm these accesses will be caught and will trigger a Granule Protection Fault (GPF). A fault during a page walk signals a bug in the kernel and is handled by oopsing the kernel. A non-page walk fault could be caused by user space having access to a page which has been delegated to the kernel and will trigger a SIGBUS to allow debugging why user space is trying to access a delegated page. Reviewed-by: Suzuki K Poulose Reviewed-by: Gavin Shan Signed-off-by: Steven Price --- Changes since v10: * Don't call arm64_notify_die() in do_gpf() but simply return 1. Changes since v2: * Include missing "Granule Protection Fault at level -1" --- arch/arm64/mm/fault.c | 28 ++++++++++++++++++++++------ 1 file changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c index 85e23388f9bb..ea3ae0ca7dba 100644 --- a/arch/arm64/mm/fault.c +++ b/arch/arm64/mm/fault.c @@ -909,6 +909,22 @@ static int do_tag_check_fault(unsigned long far, unsig= ned long esr, return 0; } =20 +static int do_gpf_ptw(unsigned long far, unsigned long esr, struct pt_regs= *regs) +{ + const struct fault_info *inf =3D esr_to_fault_info(esr); + + die_kernel_fault(inf->name, far, esr, regs); + return 0; +} + +static int do_gpf(unsigned long far, unsigned long esr, struct pt_regs *re= gs) +{ + if (!is_el1_instruction_abort(esr) && fixup_exception(regs, esr)) + return 0; + + return 1; +} + static const struct fault_info fault_info[] =3D { { do_bad, SIGKILL, SI_KERNEL, "ttbr address size fault" }, { do_bad, SIGKILL, SI_KERNEL, "level 1 address size fault" }, @@ -945,12 +961,12 @@ static const struct fault_info fault_info[] =3D { { do_bad, SIGKILL, SI_KERNEL, "unknown 32" }, { do_alignment_fault, SIGBUS, BUS_ADRALN, "alignment fault" }, { do_bad, SIGKILL, SI_KERNEL, "unknown 34" }, - { do_bad, SIGKILL, SI_KERNEL, "unknown 35" }, - { do_bad, SIGKILL, SI_KERNEL, "unknown 36" }, - { do_bad, SIGKILL, SI_KERNEL, "unknown 37" }, - { do_bad, SIGKILL, SI_KERNEL, "unknown 38" }, - { do_bad, SIGKILL, SI_KERNEL, "unknown 39" }, - { do_bad, SIGKILL, SI_KERNEL, "unknown 40" }, + { do_gpf_ptw, SIGKILL, SI_KERNEL, "level -1 granule protection fault (tr= anslation table walk)" }, + { do_gpf_ptw, SIGKILL, SI_KERNEL, "level 0 granule protection fault (tra= nslation table walk)" }, + { do_gpf_ptw, SIGKILL, SI_KERNEL, "level 1 granule protection fault (tra= nslation table walk)" }, + { do_gpf_ptw, SIGKILL, SI_KERNEL, "level 2 granule protection fault (tra= nslation table walk)" }, + { do_gpf_ptw, SIGKILL, SI_KERNEL, "level 3 granule protection fault (tra= nslation table walk)" }, + { do_gpf, SIGBUS, SI_KERNEL, "granule protection fault" }, { do_bad, SIGKILL, SI_KERNEL, "level -1 address size fault" }, { do_bad, SIGKILL, SI_KERNEL, "unknown 42" }, { do_translation_fault, SIGSEGV, SEGV_MAPERR, "level -1 translation fault= " }, --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2ABE238944D; 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V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 04/37] KVM: arm64: CCA: Check for RMI support at KVM init Date: Wed, 15 Jul 2026 15:28:06 +0100 Message-ID: <20260715142841.80544-5-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Check if the RMI support is sufficient for using in KVM. Specifically, we currently only support creating realm VMs when KVM is running in VHE mode. Signed-off-by: Steven Price --- Changes since v13: * Most of the init has been moved out of the 'kvm' directory so this is much more basic now. Changes since v12: * Drop check for 4k page size. Changes since v11: * Reword slightly the comments on the realm states. Changes since v10: * kvm_is_realm() no longer has a NULL check. * Rename from "rme" to "rmi" when referring to the RMM interface. * Check for RME (hardware) support before probing for RMI support. Changes since v8: * No need to guard kvm_init_rme() behind 'in_hyp_mode'. Changes since v6: * Improved message for an unsupported RMI ABI version. Changes since v5: * Reword "unsupported" message from "host supports" to "we want" to clarify that 'we' are the 'host'. Changes since v2: * Drop return value from kvm_init_rme(), it was always 0. * Rely on the RMM return value to identify whether the RSI ABI is compatible. --- arch/arm64/include/asm/kvm_host.h | 4 ++++ arch/arm64/include/asm/kvm_rmi.h | 17 +++++++++++++++++ arch/arm64/include/asm/virt.h | 1 + arch/arm64/kvm/Kconfig | 1 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 5 +++++ arch/arm64/kvm/rmi.c | 24 ++++++++++++++++++++++++ 7 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/include/asm/kvm_rmi.h create mode 100644 arch/arm64/kvm/rmi.c diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index bae2c4f92ef5..1a5e15040111 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -27,6 +27,7 @@ #include #include #include +#include #include =20 #define __KVM_HAVE_ARCH_INTC_INITIALIZED @@ -424,6 +425,9 @@ struct kvm_arch { /* Nested virtualization info */ struct dentry *debugfs_nv_dentry; #endif + + bool is_realm; + struct realm realm; }; =20 struct kvm_vcpu_fault_info { diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h new file mode 100644 index 000000000000..57d24b244c95 --- /dev/null +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#ifndef __ASM_KVM_RMI_H +#define __ASM_KVM_RMI_H + +/** + * struct realm - Additional per VM data for a Realm + */ +struct realm { +}; + +void kvm_init_rmi(void); + +#endif /* __ASM_KVM_RMI_H */ diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h index b546703c3ab9..92cec42952f4 100644 --- a/arch/arm64/include/asm/virt.h +++ b/arch/arm64/include/asm/virt.h @@ -87,6 +87,7 @@ void __hyp_reset_vectors(void); bool is_kvm_arm_initialised(void); =20 DECLARE_STATIC_KEY_FALSE(kvm_protected_mode_initialized); +DECLARE_STATIC_KEY_FALSE(kvm_rmi_is_available); =20 static inline bool is_pkvm_initialized(void) { diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index 449154f9a485..189e8ad78b22 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -37,6 +37,7 @@ menuconfig KVM select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS select KVM_GUEST_MEMFD + select ARM_RMM help Support hosting virtualized guest machines. =20 diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 59612d2f277c..ed3cf30eb06e 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -16,7 +16,7 @@ CFLAGS_handle_exit.o +=3D -Wno-override-init kvm-y +=3D arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ inject_fault.o va_layout.o handle_exit.o config.o \ guest.o debug.o reset.o sys_regs.o stacktrace.o \ - vgic-sys-reg-v3.o fpsimd.o pkvm.o \ + vgic-sys-reg-v3.o fpsimd.o pkvm.o rmi.o \ arch_timer.o trng.o vmid.o emulate-nested.o nested.o at.o \ vgic/vgic.o vgic/vgic-init.o \ vgic/vgic-irqfd.o vgic/vgic-v2.o \ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 50adfff75be8..b961c22fce3d 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -42,6 +42,7 @@ #include #include #include +#include #include #include =20 @@ -111,6 +112,8 @@ long kvm_get_cap_for_kvm_ioctl(unsigned int ioctl, long= *ext) return -EINVAL; } =20 +DEFINE_STATIC_KEY_FALSE(kvm_rmi_is_available); + DECLARE_KVM_HYP_PER_CPU(unsigned long, kvm_hyp_vector); =20 DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_base); @@ -3019,6 +3022,8 @@ static __init int kvm_arm_init(void) =20 in_hyp_mode =3D is_kernel_in_hyp_mode(); =20 + kvm_init_rmi(); + if (cpus_have_final_cap(ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE) || cpus_have_final_cap(ARM64_WORKAROUND_1508412)) kvm_info("Guests without required CPU erratum workarounds can deadlock s= ystem!\n" \ diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c new file mode 100644 index 000000000000..384991d69f78 --- /dev/null +++ b/arch/arm64/kvm/rmi.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#include + +#include +#include + +void kvm_init_rmi(void) +{ + /* + * TODO: Support Realm guests in nVHE mode, this will require adding + * EL2 stub(s) for REC entry and possibly other things. + */ + if (!is_kernel_in_hyp_mode()) + return; + + if (!is_rmi_available()) + return; + + /* Future patch will enable static branch kvm_rmi_is_available */ +} --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4E53638837C; Wed, 15 Jul 2026 14:29:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125760; cv=none; b=ZsoIan5ksFfhYJu871syXUt4eLvbQ6EAFUFUzZDfWZVIJ/la7bKv3/XTHjwDD/7oCwHw6eJ0NRWYzoo6DR9KieJj/xKYx6VM1eSxFdYqkSpGR/N1kLr+IxJyJ4elbaVKEptmY6xcm45Me7hqESRTzLAzgkir9Aqe5bp2K8dHdHE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125760; c=relaxed/simple; bh=nW7/u/8ytSl027az4/gQTrog0UWHJWQHxjfzk2ofIrk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jkg0uLryUOYkn1idw+ANnjdhoiH2pVZWwty4ILgy0lKIwTOr60+yUvVW4llkNbIWl0sUcR2xLDPfIcR+ewq1jRx/qcJK24eYJN0VNw2MLCOSjYUAYcFs2NUqi4xoGkfTg+RdZfr504GvhlXd9ahGlnDKkB8nJGjyQKUI7i4kwJ0= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o79Cj0UhKUE0ZUJMcVo9NDGCbiXgRWZ+bShrkDmKFuklkECL2mOQMjgsW4Y4akVqT OA++hUC1Enfa80QB53kaSBps6rSWkGJ1KiWEf3HUdRCRaHawGpY25mf5JM950VaSOm XN2g7hgfkJUw5HN2Fkkr4AiXQdr+Pj2btk3V0sds= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 05/37] KVM: arm64: CCA: Check for LPA2 support Date: Wed, 15 Jul 2026 15:28:07 +0100 Message-ID: <20260715142841.80544-6-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If KVM has enabled LPA2 support then check that the RMM also supports it. If there is a mismatch then disable support for realm guests as the VMM may attempt to create a guest which is incompatible with the RMM. Signed-off-by: Steven Price Reviewed-by: Suzuki K Poulose --- v15: * Extend rmi_has_feature() to take the register number and check the presence of SHA-256 support which is default. v13: * New patch --- arch/arm64/kvm/rmi.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 384991d69f78..247c4f033945 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -5,9 +5,31 @@ =20 #include =20 +#include #include #include =20 +static bool rmi_has_feature(int reg, unsigned long feature) +{ + return !!u64_get_bits(rmi_feat_reg(reg), feature); +} + +static int rmm_check_features(void) +{ + if (kvm_lpa2_is_enabled() && + !rmi_has_feature(0, RMI_FEATURE_REGISTER_0_LPA2)) { + kvm_err("RMM doesn't support LPA2\n"); + return -ENXIO; + } + + if (!rmi_has_feature(1, RMI_FEATURE_REGISTER_1_HASH_SHA_256)) { + kvm_err("RMM doesn't support SHA-256 measurements\n"); + return -ENXIO; + } + + return 0; +} + void kvm_init_rmi(void) { /* @@ -20,5 +42,8 @@ void kvm_init_rmi(void) if (!is_rmi_available()) return; =20 + if (rmm_check_features()) + return; + /* Future patch will enable static branch kvm_rmi_is_available */ } --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 7B05E38B7D2; Wed, 15 Jul 2026 14:29:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125765; cv=none; b=UPfjdY0Z4K8IwXItltZfRCg6N+kLqQ8jpIxljKoLFRAvFgklYmaGmRSAXzEZMhzFvdHf0dQwYjfQtvzUn6ScFUPX9xQdXcO7PzqoTBAFEdFrz5tIGilIutUdWYqQM30MI4ZlRHEe3MAYHc2La9chZbR3QfX2mHoGsb57iwC2Ubg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125765; c=relaxed/simple; bh=Aq3mAH3poSFbImflFNQAkOr2RDqb2iCoUJzNSYta8b8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gg4wk+wT54wtMDw8J2/c56t0KmT3eyxD1qJMtZibhBlHdaHVIxKoMeWRtFQUVYz2wiG0RzBVG5bW/RIc1lVYm/2UCyIBhmKK3qKMWoqttBYrtN62ioJBNxF1xtFIAoLfDQCRwgIzA/soVkPKzT/OKsnk+ZrPCHIxk8zPo8f76Cg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=mqg01ire; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="mqg01ire" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 981861576; Wed, 15 Jul 2026 07:29:18 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2C5A33F7B4; Wed, 15 Jul 2026 07:29:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125762; bh=Aq3mAH3poSFbImflFNQAkOr2RDqb2iCoUJzNSYta8b8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mqg01ireFUQuau+Jq/lxkK2DmZz8g+6xcHbQFdwNnJY70ENUgp+eJZbnndvwKFmo+ 6LyiP9k2YrmabTXrvxVfiyA27QDCp/tHOFlhCi/z3fwCod7axxSgocMmaQurcBR44i mdLZkJaAQED8zGKy2lEEaS4D4L45h0+PG2lh21yA= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 06/37] KVM: arm64: CCA: Define the user ABI Date: Wed, 15 Jul 2026 15:28:08 +0100 Message-ID: <20260715142841.80544-7-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" There is one CAP (KVM_CAP_ARM_RMI) which identifies the presence of CCA, and one ioctl. The ioctl (KVM_ARM_RMI_POPULATE) is used to populate memory during creation of the realm as this requires the RMM to copy data from an unprotected address to the protected memory - CCA does not support shared <-> private memory conversion where the memory contents is preserved as this is incompatible with memory encryption. Signed-off-by: Steven Price --- Changes since v13: * KVM_ARM_VCPU_RMI_PSCI_COMPLETE removed. * KVM_ARM_RMI_POPULATE documentation updated to reflect that the structure is written by the kernel. * CAP number bumped. Changes since v12: * Change KVM_ARM_RMI_POPULATE to update the structure with the amount that has been progressed rather than return the number of bytes populated. * Describe the flag KVM_ARM_RMI_POPULATE_FLAGS_MEASURE. * CAP number is bumped. * NOTE: The PSCI ioctl may be removed in a future spec release. Changes since v11: * Completely reworked to be more implicit. Rather than having explicit CAP operations to progress the realm construction these operations are done when needed (on populating and on first vCPU run). * Populate and PSCI complete are promoted to proper ioctls. Changes since v10: * Rename symbols from RME to RMI. Changes since v9: * Improvements to documentation. * Bump the magic number for KVM_CAP_ARM_RME to avoid conflicts. Changes since v8: * Minor improvements to documentation following review. * Bump the magic numbers to avoid conflicts. Changes since v7: * Add documentation of new ioctls * Bump the magic numbers to avoid conflicts Changes since v6: * Rename some of the symbols to make their usage clearer and avoid repetition. Changes from v5: * Actually expose the new VCPU capability (KVM_ARM_VCPU_REC) by bumping KVM_VCPU_MAX_FEATURES - note this also exposes KVM_ARM_VCPU_HAS_EL2! --- Documentation/virt/kvm/api.rst | 41 ++++++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 13 +++++++++++ 2 files changed, 54 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index 304b9c3209ae..b38e090ad95d 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -6642,6 +6642,38 @@ if the guest_memfd memory was pinned in IOMMU page t= ables. =20 See also: :ref: `KVM_SET_MEMORY_ATTRIBUTES`. =20 +4.146 KVM_ARM_RMI_POPULATE +-------------------------- + +:Capability: KVM_CAP_ARM_RMI +:Architectures: arm64 +:Type: vm ioctl +:Parameters: struct kvm_arm_rmi_populate (in/out) +:Returns: 0 on success, < 0 on error + +:: + + struct kvm_arm_rmi_populate { + __u64 base; + __u64 size; + __u64 source_uaddr; + __u32 flags; + __u32 reserved; + }; + +Populate a region of protected address space by copying the data from the +(non-protected) user space pointer provided into a protected region (backe= d by +guestmem_fd). It implicitly sets the destination region to RIPAS RAM. This= is +only valid before any VCPUs have been run. The ioctl might not populate the +entire region and in this case the kernel updates the fields `base`, `size= ` and +`source_uaddr`. User space may have to repeatedly call it until `size` is = 0 to +populate the entire region. + +`flags` can be set to `KVM_ARM_RMI_POPULATE_FLAGS_MEASURE` to request that= the +populated data is hashed and added to the guest's Realm Initial Measurement +(RIM) stored by the RMM. This can then be retrieved by the guest (using th= e RSI +interface) to present to an attestation server. + .. _kvm_run: =20 5. The kvm_run structure @@ -9025,6 +9057,15 @@ enabled, cmma can't be enabled anymore and pfmfi and= the storage key interpretation are disabled. If cmma has already been enabled or the hpage_2g module parameter is not set to 1, -EINVAL is returned. =20 +7.48 KVM_CAP_ARM_RMI +-------------------- + +:Architectures: arm64 +:Target: VM +:Parameters: None + +This capability indicates that support for CCA realms is available. + 8. Other capabilities. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 129d6f630325..0231ff174a50 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -998,6 +998,7 @@ struct kvm_enable_cap { #define KVM_CAP_S390_VSIE_ESAMODE 248 #define KVM_CAP_S390_HPAGE_2G 249 #define KVM_CAP_GUEST_MEMFD_MEMORY_ATTRIBUTES 250 +#define KVM_CAP_ARM_RMI 251 =20 struct kvm_irq_routing_irqchip { __u32 irqchip; @@ -1686,4 +1687,16 @@ struct kvm_pre_fault_memory { __u64 padding[5]; }; =20 +/* Available with KVM_CAP_ARM_RMI, only for VMs with KVM_VM_TYPE_ARM_REALM= */ +#define KVM_ARM_RMI_POPULATE _IOWR(KVMIO, 0xd7, struct kvm_arm_rmi_populat= e) +#define KVM_ARM_RMI_POPULATE_FLAGS_MEASURE (1 << 0) + +struct kvm_arm_rmi_populate { + __u64 base; + __u64 size; + __u64 source_uaddr; + __u32 flags; + __u32 reserved; +}; + #endif /* __LINUX_KVM_H */ --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EDEA538E5ED; Wed, 15 Jul 2026 14:29:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125771; cv=none; b=D3E5BMx/CgZxz9Jh/Hr/8V2DdIoC4f+Zdulh+GseRMftpAUOFQ5j33nEDMHk3DoomWjle3S7i+B7l6ROn1fLB0K8pLCiYzcPT6Cj5h5zrpBsxdw+V8/KEszqQzsLJ4nRaBkMLzu7x6vs5qws/JH0jOgLiSnxQPRWCYFpgvJmros= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125771; c=relaxed/simple; bh=rmPEquWPj5n1UxPn4TykO3yHtPl/Ea9cY0nMnoWq67k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zjk76kbmEazHiIqa6CicYdTzdmdXhJwGGAlqb6MnckaHthRvRYXKqrwVdoF8D69rtH3blUs7YcdbG4B3zI7nGoc43hrTjju39GRH4oPJzjmaSc7X0lfgC7nb9tZc++2HPPyXyZ9SNGZHfXHNWnABlxlBNsv/2r/dKh+DY2fULr4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=BFy0i7fb; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="BFy0i7fb" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 20AD0153B; Wed, 15 Jul 2026 07:29:24 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3C1803F7B4; Wed, 15 Jul 2026 07:29:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125768; bh=rmPEquWPj5n1UxPn4TykO3yHtPl/Ea9cY0nMnoWq67k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BFy0i7fb8C8uar/N2eYsQ4TyqG3xzFV9XHWrMSBU+SsWsiGiCu//MyW8LT0SKcAAr 8NqbK8UK9N2A+1ERHHph2ZABv/5YIU7IcNPQsZ2OeBEYZQ/qnZYmvFbvKlDEnMOmLA FURlo7o9eH/xwnzHTofchK5NthvrtmQTAQ4mtd2Y= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 07/37] KVM: arm64: CCA: Add basic infrastructure for creating a realm Date: Wed, 15 Jul 2026 15:28:09 +0100 Message-ID: <20260715142841.80544-8-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the skeleton functions for creating and destroying a realm. The IPA size requested is checked against what the RMM supports. The actual work of constructing the realm will be added in future patches. Signed-off-by: Steven Price --- Changes since v14: * Adapt to the RMM v2.0-bet2 realm parameter layout and SRO-based realm creation. Changes since v13: * Rebased and updated to RMM-v2.0-bet1. * Auxiliary granules have been removed in RMM-v2.0-bet1 Changes since v12: * Drop the RMM_PAGE_{SHIFT,SIZE} defines - the RMM is now configured to be the same as the host's page size. * Rework delegate/undelegate functions to use the new RMI range based operations. Changes since v11: * Major rework to drop the realm configuration and make the construction of realms implicit rather than driven by the VMM directly. * The code to create RDs, handle VMIDs etc is moved to later patches. Changes since v10: * Rename from RME to RMI. * Move the stage2 cleanup to a later patch. Changes since v9: * Avoid walking the stage 2 page tables when destroying the realm - the real ones are not accessible to the non-secure world, and the RMM may leave junk in the physical pages when returning them. * Fix an error path in realm_create_rd() to actually return an error value. Changes since v8: * Fix free_delegated_granule() to not call kvm_account_pgtable_pages(); a separate wrapper will be introduced in a later patch to deal with RTTs. * Minor code cleanups following review. Changes since v7: * Minor code cleanup following Gavin's review. Changes since v6: * Separate RMM RTT calculations from host PAGE_SIZE. This allows the host page size to be larger than 4k while still communicating with an RMM which uses 4k granules. Changes since v5: * Introduce free_delegated_granule() to replace many undelegate/free_page() instances and centralise the comment on leaking when the undelegate fails. * Several other minor improvements suggested by reviews - thanks for the feedback! Changes since v2: * Improved commit description. * Improved return failures for rmi_check_version(). * Clear contents of PGD after it has been undelegated in case the RMM left stale data. * Minor changes to reflect changes in previous patches. --- arch/arm64/include/asm/kvm_emulate.h | 24 ++++++++++ arch/arm64/include/asm/kvm_rmi.h | 65 +++++++++++++++++++++++++++ arch/arm64/kvm/arm.c | 12 +++++ arch/arm64/kvm/mmu.c | 18 +++++++- arch/arm64/kvm/rmi.c | 67 ++++++++++++++++++++++++++++ 5 files changed, 184 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 5bf3d7e1d92c..e26d6755279f 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -688,4 +688,28 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) vcpu->arch.hcrx_el2 |=3D HCRX_EL2_EnASR; } } + +static inline bool kvm_is_realm(struct kvm *kvm) +{ + if (static_branch_unlikely(&kvm_rmi_is_available)) + return kvm->arch.is_realm; + return false; +} + +static inline enum realm_state kvm_realm_state(struct kvm *kvm) +{ + return READ_ONCE(kvm->arch.realm.state); +} + +static inline void kvm_set_realm_state(struct kvm *kvm, + enum realm_state new_state) +{ + WRITE_ONCE(kvm->arch.realm.state, new_state); +} + +static inline bool kvm_realm_is_created(struct kvm *kvm) +{ + return kvm_is_realm(kvm) && kvm_realm_state(kvm) !=3D REALM_STATE_NONE; +} + #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 57d24b244c95..5c40616aa1a1 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -6,12 +6,77 @@ #ifndef __ASM_KVM_RMI_H #define __ASM_KVM_RMI_H =20 +#include + +/** + * enum realm_state - State of a Realm + * + * Mirrors the RMM's Realm lifecycle states where they are meaningful to K= VM, + * with REALM_STATE_DYING being a KVM-internal state used to prevent furth= er + * requests while teardown is in progress. KVM does not track REALM_SYSTEM= _OFF + * or REALM_ZOMBIE separately as they naturally lead to teardown. + */ +enum realm_state { + /** + * @REALM_STATE_NONE: + * Realm has not yet been created. rmi_realm_create() has not + * yet been called. + */ + REALM_STATE_NONE, + /** + * @REALM_STATE_NEW: + * Realm is under construction, rmi_realm_create() has been + * called, but it is not yet activated. Pages may be populated. + */ + REALM_STATE_NEW, + /** + * @REALM_STATE_ACTIVE: + * Realm has been created and is eligible for execution with + * rmi_rec_enter(). Pages may no longer be populated with + * rmi_data_create(). + */ + REALM_STATE_ACTIVE, + /** + * @REALM_STATE_DYING: + * Realm is in the process of being destroyed or has already been + * destroyed. + */ + REALM_STATE_DYING, + /** + * @REALM_STATE_DEAD: + * Realm has been destroyed. + */ + REALM_STATE_DEAD +}; + /** * struct realm - Additional per VM data for a Realm + * + * @rd: Kernel mapping of the RMM-managed Realm Descriptor (RD) granule + * @params: Parameters for the RMI_REALM_CREATE command + * @sro: Preallocated SRO state context for Realm MMU operations + * @state: The lifetime state machine for the realm + * @ia_bits: Number of valid Input Address bits in the IPA */ struct realm { + void *rd; + struct realm_params *params; + /* + * Reused by RTT map/unmap SRO commands. Those commands are only + * issued from Realm stage-2 map/unmap paths while kvm->mmu_lock is + * held for write, including Realm fault handling where + * kvm_fault_lock() takes the write side, so concurrent use is + * serialized. + */ + struct rmi_sro_state *sro; + enum realm_state state; + unsigned int ia_bits; }; =20 void kvm_init_rmi(void); +u32 kvm_rmm_ipa_limit(void); + +int kvm_init_realm(struct kvm *kvm); +void kvm_destroy_realm(struct kvm *kvm); =20 #endif /* __ASM_KVM_RMI_H */ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index b961c22fce3d..c4d906861736 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -266,6 +266,13 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long ty= pe) =20 bitmap_zero(kvm->arch.vcpu_features, KVM_VCPU_MAX_FEATURES); =20 + /* Initialise the realm bits after the generic bits are enabled */ + if (kvm_is_realm(kvm)) { + ret =3D kvm_init_realm(kvm); + if (ret) + goto err_uninit_mmu; + } + return 0; =20 err_uninit_mmu: @@ -328,6 +335,8 @@ void kvm_arch_destroy_vm(struct kvm *kvm) kvm_unshare_hyp(kvm, kvm + 1); =20 kvm_arm_teardown_hypercalls(kvm); + if (kvm_is_realm(kvm)) + kvm_destroy_realm(kvm); } =20 static bool kvm_has_full_ptr_auth(void) @@ -488,6 +497,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) else r =3D kvm_supports_cacheable_pfnmap(); break; + case KVM_CAP_ARM_RMI: + r =3D static_key_enabled(&kvm_rmi_is_available); + break; =20 default: r =3D 0; diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 6c941aaa10c6..8b9efa8a3539 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -904,10 +904,14 @@ static struct kvm_pgtable_mm_ops kvm_s2_mm_ops =3D { =20 static int kvm_init_ipa_range(struct kvm_s2_mmu *mmu, unsigned long type) { + struct kvm *kvm =3D kvm_s2_mmu_to_kvm(mmu); u32 kvm_ipa_limit =3D get_kvm_ipa_limit(); u64 mmfr0, mmfr1; u32 phys_shift; =20 + if (kvm_is_realm(kvm)) + kvm_ipa_limit =3D kvm_rmm_ipa_limit(); + phys_shift =3D KVM_VM_TYPE_ARM_IPA_SIZE(type); if (is_protected_kvm_enabled()) { phys_shift =3D kvm_ipa_limit; @@ -957,9 +961,18 @@ static void stage2_destroy_range(struct kvm_pgtable *p= gt, phys_addr_t addr, =20 static void kvm_stage2_destroy(struct kvm_pgtable *pgt) { + struct kvm *kvm =3D kvm_s2_mmu_to_kvm(pgt->mmu); unsigned int ia_bits =3D VTCR_EL2_IPA(pgt->mmu->vtcr); =20 - stage2_destroy_range(pgt, 0, BIT(ia_bits)); + /* + * Realm RTTs are inaccessible to the host and may contain stale data + * after the RMM has released them. The non-root RTTs are explicitly + * destroyed through RMI before the RD is destroyed; only the root PGD + * pages remain to be freed here. + */ + if (!kvm_is_realm(kvm)) + stage2_destroy_range(pgt, 0, BIT(ia_bits)); + KVM_PGT_FN(kvm_pgtable_stage2_destroy_pgd)(pgt); } =20 @@ -1001,6 +1014,8 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s= 2_mmu *mmu, unsigned long t return -EINVAL; } =20 + mmu->arch =3D &kvm->arch; + err =3D kvm_init_ipa_range(mmu, type); if (err) return err; @@ -1009,7 +1024,6 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_s= 2_mmu *mmu, unsigned long t if (!pgt) return -ENOMEM; =20 - mmu->arch =3D &kvm->arch; err =3D KVM_PGT_FN(kvm_pgtable_stage2_init)(pgt, mmu, &kvm_s2_mm_ops); if (err) goto out_free_pgtable; diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 247c4f033945..b81c404ead9f 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -5,6 +5,8 @@ =20 #include =20 +#include +#include #include #include #include @@ -14,6 +16,71 @@ static bool rmi_has_feature(int reg, unsigned long featu= re) return !!u64_get_bits(rmi_feat_reg(reg), feature); } =20 +u32 kvm_rmm_ipa_limit(void) +{ + return u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_S2SZ); +} + +void kvm_destroy_realm(struct kvm *kvm) +{ + struct realm *realm =3D &kvm->arch.realm; + size_t pgd_size =3D kvm_pgtable_stage2_pgd_size(kvm->arch.mmu.vtcr); + + if (realm->params) { + free_page((unsigned long)realm->params); + realm->params =3D NULL; + } + + if (!kvm_realm_is_created(kvm)) { + kfree(realm->sro); + realm->sro =3D NULL; + return; + } + + kvm_set_realm_state(kvm, REALM_STATE_DYING); + + if (realm->rd) { + phys_addr_t rd_phys =3D virt_to_phys(realm->rd); + + if (WARN_ON(rmi_realm_terminate(rd_phys, realm->sro))) + return; + + if (WARN_ON(rmi_realm_destroy(rd_phys, realm->sro))) + return; + free_delegated_page(rd_phys); + realm->rd =3D NULL; + } + + if (WARN_ON(rmi_undelegate_range(kvm->arch.mmu.pgd_phys, + pgd_size))) + return; + + kvm_set_realm_state(kvm, REALM_STATE_DEAD); + + /* Now that the realm is destroyed, free the entry-level RTTs. */ + kvm_free_stage2_pgd(&kvm->arch.mmu); + + kfree(realm->sro); + realm->sro =3D NULL; +} + +int kvm_init_realm(struct kvm *kvm) +{ + struct realm *realm =3D &kvm->arch.realm; + + realm->params =3D (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); + realm->sro =3D kmalloc_obj(*realm->sro); + if (!realm->params || !realm->sro) { + free_page((unsigned long)realm->params); + kfree(realm->sro); + realm->params =3D NULL; + realm->sro =3D NULL; + return -ENOMEM; + } + + return 0; +} + static int rmm_check_features(void) { if (kvm_lpa2_is_enabled() && --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B12B5384245; Wed, 15 Jul 2026 14:29:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125775; cv=none; b=NKpYMYSNzcDFiNYchiAFWwBCBoMynFUm5bX+TIWmM8kW/DhUIWkAM2cMYPoEoTpSN5Iw4wlcvgkIZ9pOuqCPoCb9nG2EJdAMUG+lfNtd37VmoLZemvc3LhQKnJ5LtWzBaMQ9k7ZtBUr98200KJJC408dBz+R/OsvGEOElcfrlPI= ARC-Message-Signature: i=1; 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V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 08/37] KVM: arm64: CCA: Don't expose unsupported capabilities for realm guests Date: Wed, 15 Jul 2026 15:28:10 +0100 Message-ID: <20260715142841.80544-9-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Suzuki K Poulose RMM v2.0 provides no mechanism for the host to perform debug operations on the guest. So limit the extensions that are visible to an allowlist so that only those capabilities we can support are advertised. Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price --- Changes since v13: * Add missing check in kvm_vm_ioctl_enable_cap(). Changes since v10: * Add a kvm_realm_ext_allowed() function which limits which extensions are exposed to an allowlist. This removes the need for special casing various extensions. Changes since v7: * Remove the helper functions and inline the kvm_is_realm() check with a ternary operator. * Rewrite the commit message to explain this patch. --- arch/arm64/kvm/arm.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index c4d906861736..6f39831dcf5d 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -135,6 +135,26 @@ int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu) return kvm_vcpu_exiting_guest_mode(vcpu) =3D=3D IN_GUEST_MODE; } =20 +static bool kvm_realm_ext_allowed(long ext) +{ + switch (ext) { + case KVM_CAP_IRQCHIP: + case KVM_CAP_ARM_PSCI: + case KVM_CAP_ARM_PSCI_0_2: + case KVM_CAP_NR_VCPUS: + case KVM_CAP_MAX_VCPUS: + case KVM_CAP_MAX_VCPU_ID: + case KVM_CAP_MSI_DEVID: + case KVM_CAP_ARM_VM_IPA_SIZE: + case KVM_CAP_ARM_PTRAUTH_ADDRESS: + case KVM_CAP_ARM_PTRAUTH_GENERIC: + case KVM_CAP_ARM_RMI: + case KVM_CAP_SYNC_MMU: + return true; + } + return false; +} + int kvm_vm_ioctl_enable_cap(struct kvm *kvm, struct kvm_enable_cap *cap) { @@ -146,6 +166,9 @@ int kvm_vm_ioctl_enable_cap(struct kvm *kvm, if (is_protected_kvm_enabled() && !kvm_pkvm_ext_allowed(kvm, cap->cap)) return -EINVAL; =20 + if (kvm && kvm_is_realm(kvm) && !kvm_realm_ext_allowed(cap->cap)) + return -EINVAL; + switch (cap->cap) { case KVM_CAP_ARM_NISV_TO_USER: r =3D 0; @@ -380,6 +403,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long = ext) if (is_protected_kvm_enabled() && !kvm_pkvm_ext_allowed(kvm, ext)) return 0; =20 + if (kvm && kvm_is_realm(kvm) && !kvm_realm_ext_allowed(ext)) + return 0; + switch (ext) { case KVM_CAP_IRQCHIP: r =3D vgic_present; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E47353859FA; Wed, 15 Jul 2026 14:29:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125780; cv=none; b=PUnDpbW8GM0gTSSK6xc0aAvcZiexeMq/MgbD83s1738yPr8bDd+ykXich+zhXTtvfgbe29x9dLR7qsHB19JGYkwLYRrLE//NjDNlfQ3MBmFkVtyzw6DheIvJFfoWBMfvNuUqzGUzix2tLvOqWoT2sPhyScm3QkLkypeAhoaRYOQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125780; c=relaxed/simple; bh=zixYPQ+w+37O4gvY4lHd1xlI1aPi6dhUKtIpVG5gxWM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cmpmOSBcnPJgQ8UM5irnXAcnJxzJiZTSMp/Xs7ySNvrwSzCK6y3QAJfx8aPNQJS0UR9OEb/1x+MLjUbgnp77oHULGPwAFY+4DtHAxpBgmprFCZGgHHNb4fOjvQw7nkm8un0/myKWtti9aVtafZY998DCNyFK1UjIa7OiJRmkMNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Q1n9fhcR; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Q1n9fhcR" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1C2071576; Wed, 15 Jul 2026 07:29:34 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B5793F7B4; Wed, 15 Jul 2026 07:29:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125778; bh=zixYPQ+w+37O4gvY4lHd1xlI1aPi6dhUKtIpVG5gxWM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Q1n9fhcRpdoIR0XGyMLVabJHxznFgtVeFu8FAxAQEoRf7pA+4j6bcsRZkT4KUojOj GGkSMq4IbgZ7ckgLDg78LeZO5+1tW+RYerumDWb4A7DxgeknRB7cgihtfMozrMxlSr UD5G7ag5jwn25TRuKcdYYk18bfyoMTLVAsN3z7MU= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 09/37] KVM: arm64: CCA: Allow passing the machine type in KVM creation Date: Wed, 15 Jul 2026 15:28:11 +0100 Message-ID: <20260715142841.80544-10-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Previously machine type was used purely for specifying the physical address size of the guest. Reserve the higher bits to specify an ARM specific machine type and declare a new type 'KVM_VM_TYPE_ARM_REALM' used to create a realm guest. Signed-off-by: Steven Price --- Changes since v13: * Rework to use the two top bits for the machine type now that pKVM has merged and used the top bit for KVM_VM_TYPE_ARM_PROTECTED. * Update the documentation to include KVM_VM_TYPE_ARM_PROTECTED as well. Changes since v9: * Explictly set realm.state to REALM_STATE_NONE rather than rely on the zeroing of the structure. Changes since v7: * Add some documentation explaining the new machine type. Changes since v6: * Make the check for kvm_rme_is_available more visible and report an error code of -EPERM (instead of -EINVAL) to make it explicit that the kernel supports RME, but the platform doesn't. --- Documentation/virt/kvm/api.rst | 18 ++++++++++++++++-- arch/arm64/kvm/arm.c | 11 +++++++++++ include/uapi/linux/kvm.h | 7 ++++++- 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index b38e090ad95d..e39d146b34a3 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -181,8 +181,22 @@ flag KVM_VM_MIPS_VZ. ARM64: ^^^^^^ =20 -On arm64, the physical address size for a VM (IPA Size limit) is limited -to 40bits by default. The limit can be configured if the host supports the +On arm64, the machine type identifier is used to encode a type and the +physical address size for the VM. The lower byte (bits[7-0]) encode the +address size and the upper bits[30-31] encode a machine type. The machine +types that might be available are: + + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + KVM_VM_TYPE_ARM_NORMAL A standard VM + KVM_VM_TYPE_ARM_REALM A "Realm" VM using the Arm Confidential + Compute extensions, the VM's memory is + protected from the host. + KVM_VM_TYPE_ARM_PROTECTED A "protected" VM using pKVM to isolate the + VM from the host. + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The physical address size for a VM (IPA Size limit) is limited to 40bits +by default. The limit can be configured if the host supports the extension KVM_CAP_ARM_VM_IPA_SIZE. When supported, use KVM_VM_TYPE_ARM_IPA_SIZE(IPA_Bits) to set the size in the machine type identifier, where IPA_Bits is the maximum width of any physical diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 6f39831dcf5d..9881fd6c511c 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -249,6 +249,17 @@ int kvm_arch_init_vm(struct kvm *kvm, unsigned long ty= pe) mutex_unlock(&kvm->lock); #endif =20 + if ((type & KVM_VM_TYPE_ARM_PROTECTED) && + (type & KVM_VM_TYPE_ARM_REALM)) + return -EINVAL; + + if (type & KVM_VM_TYPE_ARM_REALM) { + if (!static_branch_unlikely(&kvm_rmi_is_available)) + return -EINVAL; + kvm_set_realm_state(kvm, REALM_STATE_NONE); + kvm->arch.is_realm =3D true; + } + kvm_init_nested(kvm); =20 ret =3D kvm_share_hyp(kvm, kvm + 1); diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 0231ff174a50..adee3936d6ae 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -700,14 +700,19 @@ struct kvm_enable_cap { * address size for the VM. Bits[7-0] are reserved for the guest * PA size shift (i.e, log2(PA_Size)). For backward compatibility, * value 0 implies the default IPA size, 40bits. + * + * Bits[30-31] are reserved for the VM type */ #define KVM_VM_TYPE_ARM_IPA_SIZE_MASK 0xffULL #define KVM_VM_TYPE_ARM_IPA_SIZE(x) \ ((x) & KVM_VM_TYPE_ARM_IPA_SIZE_MASK) =20 +#define KVM_VM_TYPE_ARM_NORMAL 0 +#define KVM_VM_TYPE_ARM_REALM (1UL << 30) #define KVM_VM_TYPE_ARM_PROTECTED (1UL << 31) #define KVM_VM_TYPE_ARM_MASK (KVM_VM_TYPE_ARM_IPA_SIZE_MASK | \ - KVM_VM_TYPE_ARM_PROTECTED) + KVM_VM_TYPE_ARM_PROTECTED | \ + KVM_VM_TYPE_ARM_REALM) =20 /* * ioctls for /dev/kvm fds: --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5687B39150D; Wed, 15 Jul 2026 14:29:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125787; cv=none; b=dR5kSfUwZIjLEt7ynHqYFu4gxjNGb1A9MOLKqG6veuLJgmpFkhFlJiBgNZDWBELfs3n5oPrcP80ua69ELzl/odNgeTLTzPWbTSyMH9DmXATKO3Wu28bO3RRX7nOChDnzhCbAGf3Rvuxa+XUM6Zfu1kaYuF9vvN4QZpZUmEInE70= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125787; c=relaxed/simple; bh=xQBGf9ev+hZrupI/CTsmEhaQdHI42R/C3WEsticGYTU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IG9GnvS5grkwmRXTF5GkQi59C1u67ZL8FOYHypp/3/Ei6YqdT9x91XmodB+/1mQ+cQ1YaOEH2ARuqoBBBPE0bk9kLdSGzJVR8oNF1828Hkp6kRCKOcdMmziqTULK/cHvACMnCi+SZTDvG59mNWdBF0yV5mHFhUJJnCDv2vCgAGU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=j3EYz3KA; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="j3EYz3KA" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 018141576; Wed, 15 Jul 2026 07:29:39 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9F5E93F7B4; Wed, 15 Jul 2026 07:29:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125783; bh=xQBGf9ev+hZrupI/CTsmEhaQdHI42R/C3WEsticGYTU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j3EYz3KA1BpjYFulTrxYCkbhpYO+M3xdqT1IYTIFKaXgfrx3KQtDzXtga2UT3sbgb DL9wUAeVp7aD0nFAZmW4cy+gQRNDPRhUVioXrYbPmK04ktwqvf6LvIZe7zf9Duq/Nc q1QI3iAAi4j4eonvCi+F0Z2sh4GKbLcNziB4F9bA= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 10/37] KVM: arm64: CCA: Tear down RTTs Date: Wed, 15 Jul 2026 15:28:12 +0100 Message-ID: <20260715142841.80544-11-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM owns the stage 2 page tables for a realm, and KVM must request that the RMM creates/destroys entries as necessary. The physical pages to store the page tables are delegated to the realm as required, and can be undelegated when no longer used. Creating new RTTs is the easy part, tearing down is a little more tricky. The result of realm_rtt_destroy() can be used to effectively walk the tree and destroy the entries (undelegating pages that were given to the realm). Signed-off-by: Steven Price --- Changes since v14: * Teardown is now serialized under config_lock and idempotent. Changes since v13: * Avoid the double call of kvm_free_stage2_pgd() by splitting the work across that and a new function kvm_realm_uninit_stage2() which is only called for realm guests. Changes since v12: * Simplify some functions now we know RMM page size is the same as the host's. Changes since v11: * Moved some code from earlier in the series to this one so that it's added when it's first used. Changes since v10: * RME->RMI rename. * Some code to handle freeing stage 2 PGD moved into this patch where it belongs. Changes since v9: * Add a comment clarifying that root level RTTs are not destroyed until after the RD is destroyed. Changes since v8: * Introduce free_rtt() wrapper which calls free_delegated_granule() followed by kvm_account_pgtable_pages(). This makes it clear where an RTT is being freed rather than just a delegated granule. Changes since v6: * Move rme_rtt_level_mapsize() and supporting defines from kvm_rme.h into rme.c as they are only used in that file. Changes since v5: * Rename some RME_xxx defines to do with page sizes as RMM_xxx - they are a property of the RMM specification not the RME architecture. Changes since v2: * Moved {alloc,free}_delegated_page() and ensure_spare_page() to a later patch when they are actually used. * Some simplifications now rmi_xxx() functions allow NULL as an output parameter. * Improved comments and code layout. --- arch/arm64/include/asm/kvm_rmi.h | 11 ++ arch/arm64/kvm/mmu.c | 17 ++- arch/arm64/kvm/rmi.c | 196 +++++++++++++++++++++++++++++++ 3 files changed, 223 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 5c40616aa1a1..31ec856561c6 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -57,6 +57,8 @@ enum realm_state { * @sro: Preallocated SRO state context for Realm MMU operations * @state: The lifetime state machine for the realm * @ia_bits: Number of valid Input Address bits in the IPA + * @stage2_unmapped: The Realm stage-2 mappings have been removed + * @rtts_destroyed: The non-root RTTs have been torn down */ struct realm { void *rd; @@ -71,6 +73,8 @@ struct realm { struct rmi_sro_state *sro; enum realm_state state; unsigned int ia_bits; + bool stage2_unmapped; + bool rtts_destroyed; }; =20 void kvm_init_rmi(void); @@ -78,5 +82,12 @@ u32 kvm_rmm_ipa_limit(void); =20 int kvm_init_realm(struct kvm *kvm); void kvm_destroy_realm(struct kvm *kvm); +int kvm_realm_teardown_stage2(struct kvm *kvm); + +static inline bool kvm_realm_is_private_address(struct realm *realm, + unsigned long addr) +{ + return !(addr & BIT(realm->ia_bits - 1)); +} =20 #endif /* __ASM_KVM_RMI_H */ diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 8b9efa8a3539..cd06881c1497 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1060,9 +1060,24 @@ int kvm_init_stage2_mmu(struct kvm *kvm, struct kvm_= s2_mmu *mmu, unsigned long t return err; } =20 +static void kvm_realm_uninit_stage2(struct kvm_s2_mmu *mmu) +{ + struct kvm *kvm =3D kvm_s2_mmu_to_kvm(mmu); + + mutex_lock(&kvm->arch.config_lock); + if (kvm_realm_state(kvm) =3D=3D REALM_STATE_ACTIVE) { + kvm_set_realm_state(kvm, REALM_STATE_DYING); + WARN_ON(kvm_realm_teardown_stage2(kvm)); + } + mutex_unlock(&kvm->arch.config_lock); +} + void kvm_uninit_stage2_mmu(struct kvm *kvm) { - kvm_free_stage2_pgd(&kvm->arch.mmu); + if (kvm_is_realm(kvm)) + kvm_realm_uninit_stage2(&kvm->arch.mmu); + else + kvm_free_stage2_pgd(&kvm->arch.mmu); kvm_mmu_free_memory_cache(&kvm->arch.mmu.split_page_cache); } =20 diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index b81c404ead9f..db32448a0fc1 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -11,6 +11,14 @@ #include #include =20 +static inline unsigned long rmi_rtt_level_mapsize(int level) +{ + if (WARN_ON(level > KVM_PGTABLE_LAST_LEVEL)) + return PAGE_SIZE; + + return (1UL << ARM64_HW_PGTABLE_LEVEL_SHIFT(level)); +} + static bool rmi_has_feature(int reg, unsigned long feature) { return !!u64_get_bits(rmi_feat_reg(reg), feature); @@ -21,11 +29,187 @@ u32 kvm_rmm_ipa_limit(void) return u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_S2SZ); } =20 +static int get_start_level(struct realm *realm) +{ + return 4 - stage2_pgtable_levels(realm->ia_bits); +} + +static void free_rtt(phys_addr_t phys) +{ + if (free_delegated_page(phys)) + return; + + kvm_account_pgtable_pages(phys_to_virt(phys), -1); +} + +/* + * realm_rtt_destroy - Destroy an RTT at @level for @addr. + * + * Returns - Result of the RMI_RTT_DESTROY call, and: + * @rtt_granule: RTT granule, if the RTT was destroyed. + * @next_addr: IPA corresponding to the next possible valid entry we + * can target + */ +static int realm_rtt_destroy(struct realm *realm, unsigned long addr, + int level, phys_addr_t *rtt_granule, + unsigned long *next_addr) +{ + unsigned long out_rtt; + int ret; + + ret =3D rmi_rtt_destroy(virt_to_phys(realm->rd), addr, level, + &out_rtt, next_addr); + + *rtt_granule =3D out_rtt; + + return ret; +} + +static int realm_tear_down_rtt_level(struct realm *realm, int level, + unsigned long start, unsigned long end) +{ + ssize_t map_size; + unsigned long addr, next_addr; + + if (WARN_ON(level > KVM_PGTABLE_LAST_LEVEL)) + return -EINVAL; + + map_size =3D rmi_rtt_level_mapsize(level - 1); + + for (addr =3D start; addr < end; addr =3D next_addr) { + phys_addr_t rtt_granule; + int ret; + unsigned long align_addr =3D ALIGN(addr, map_size); + + next_addr =3D ALIGN(addr + 1, map_size); + + if (next_addr > end || align_addr !=3D addr) { + /* + * The target range is smaller than what this level + * covers, recurse deeper. + */ + ret =3D realm_tear_down_rtt_level(realm, + level + 1, + addr, + min(next_addr, end)); + if (ret) + return ret; + continue; + } + + ret =3D realm_rtt_destroy(realm, addr, level, + &rtt_granule, &next_addr); + + switch (RMI_RETURN_STATUS(ret)) { + case RMI_SUCCESS: + free_rtt(rtt_granule); + break; + case RMI_ERROR_RTT: + if (next_addr > addr) { + /* Missing RTT, skip */ + break; + } + /* + * We tear down the RTT range for the full IPA + * space, after everything is unmapped. Also we + * descend down only if we cannot tear down a + * top level RTT. Thus RMM must be able to walk + * to the requested level. e.g., a block mapping + * exists at L1 or L2. + */ + if (WARN_ON(RMI_RETURN_INDEX(ret) !=3D level)) + return -EBUSY; + if (WARN_ON(level =3D=3D KVM_PGTABLE_LAST_LEVEL)) + return -EBUSY; + + /* + * The table has active entries in it, recurse deeper + * and tear down the RTTs. + */ + next_addr =3D ALIGN(addr + 1, map_size); + ret =3D realm_tear_down_rtt_level(realm, + level + 1, + addr, + next_addr); + if (ret) + return ret; + /* + * Now that the child RTTs are destroyed, + * retry at this level. + */ + next_addr =3D addr; + break; + default: + WARN_ON(1); + return -ENXIO; + } + } + + return 0; +} + +static int realm_tear_down_rtt_range(struct realm *realm, + unsigned long start, unsigned long end) +{ + /* + * Root level RTTs can only be destroyed after the RD is destroyed. So + * tear down everything below the root level + */ + return realm_tear_down_rtt_level(realm, get_start_level(realm) + 1, + start, end); +} + +static int realm_destroy_rtts(struct kvm *kvm) +{ + struct realm *realm =3D &kvm->arch.realm; + unsigned int ia_bits =3D realm->ia_bits; + int ret; + + lockdep_assert_held(&kvm->arch.config_lock); + + if (realm->rtts_destroyed) + return 0; + + ret =3D realm_tear_down_rtt_range(realm, 0, (1UL << ia_bits)); + if (ret) + return ret; + + realm->rtts_destroyed =3D true; + return 0; +} + +static void realm_unmap_stage2(struct kvm *kvm) +{ + struct realm *realm =3D &kvm->arch.realm; + + lockdep_assert_held(&kvm->arch.config_lock); + + if (realm->stage2_unmapped) + return; + + write_lock(&kvm->mmu_lock); + kvm_stage2_unmap_range(&kvm->arch.mmu, 0, + BIT(realm->ia_bits - 1), true); + write_unlock(&kvm->mmu_lock); + + realm->stage2_unmapped =3D true; +} + +int kvm_realm_teardown_stage2(struct kvm *kvm) +{ + lockdep_assert_held(&kvm->arch.config_lock); + + realm_unmap_stage2(kvm); + return realm_destroy_rtts(kvm); +} + void kvm_destroy_realm(struct kvm *kvm) { struct realm *realm =3D &kvm->arch.realm; size_t pgd_size =3D kvm_pgtable_stage2_pgd_size(kvm->arch.mmu.vtcr); =20 + guard(mutex)(&kvm->arch.config_lock); + if (realm->params) { free_page((unsigned long)realm->params); realm->params =3D NULL; @@ -39,12 +223,24 @@ void kvm_destroy_realm(struct kvm *kvm) =20 kvm_set_realm_state(kvm, REALM_STATE_DYING); =20 + /* + * REALM_DESTROY requires the realm to be non-live: all RECs must have + * been destroyed and the root RTTs must be empty. Unmap the IPA space + * and destroy any non-root RTTs before tearing down the RD. The root + * RTT pages are still owned by the RMM at this point, so keep the KVM + * pgtable alive until after REALM_DESTROY and undelegation. + */ + realm_unmap_stage2(kvm); + if (realm->rd) { phys_addr_t rd_phys =3D virt_to_phys(realm->rd); =20 if (WARN_ON(rmi_realm_terminate(rd_phys, realm->sro))) return; =20 + if (WARN_ON(realm_destroy_rtts(kvm))) + return; + if (WARN_ON(rmi_realm_destroy(rd_phys, realm->sro))) return; free_delegated_page(rd_phys); --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B44BF38735A; Wed, 15 Jul 2026 14:29:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125792; cv=none; b=FJV9li7fWmlQnRB16xeNooWyPr8zwvAbPMr2ATJCqbrxfbQk88qLcl6uFEKq9kmWW53EF7W69tkKxc5+8NufgR0rM725uHJbgdZe8bTa+krqzoeuOV5vlzjTvpuO6+9FFrb4jTmYFt5ciE0XGy8UUES3X3f3ke8S7iiqQa56YRQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125792; c=relaxed/simple; bh=i/sQSnE603pausWZ6kD5UkzrMpNRSULcD4834UkICJY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FIECYO4Vze1gi2qEPgIrtc53NnDe9VdqPsqeSQNW+Nl+fzAzCz7zGJ5dAwSEsBVIkBxx5dPepX+MNu4l7W8NP5A91IKDx/ETLiMvBOYBqVbd+P71mc24NgOIDeXS/T2Ug6TahvNlLtuFJC7vU/TO7073Sr8hM1rOLJ/SsZIlCJQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=hmaBSOkR; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="hmaBSOkR" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D388D153B; Wed, 15 Jul 2026 07:29:43 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 882B53F7B4; Wed, 15 Jul 2026 07:29:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125788; bh=i/sQSnE603pausWZ6kD5UkzrMpNRSULcD4834UkICJY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hmaBSOkRY2UBVjRNElbwCv8W4DECle9GMvIK9vePmx1zrTyVi+a+RzQnaPaSQWXv8 zyQkofsuuEZDP2gWojMuVwiiGKlPcyM5jq1v/M+2GtvhI/TvEUVJCPvRFdMrxRE+dv /v8+7vdZ0+oeSB8gvGft38Q5fCn3LnCt3UH5SXak= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 11/37] KVM: arm64: CCA: Allocate and free RECs to match vCPUs Date: Wed, 15 Jul 2026 15:28:13 +0100 Message-ID: <20260715142841.80544-12-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM maintains a data structure known as the Realm Execution Context (or REC). It is similar to struct kvm_vcpu and tracks the state of the virtual CPUs. KVM must delegate memory and request the structures are created when vCPUs are created, and suitably tear down on destruction. RECs may require additional pages (e.g. for storing larger register state for SVE). The RMM can request extra pages for this purpose using the Stateful RMI Operations (SRO) functionality to request pages during REC creation. These pages are then passed back to the host from the RMM ('reclaimed') when the REC is destroyed. The kernel tracking object (struct rmi_sro_state) is stored in the realm_rec structure to avoid memory allocation during the destruction path. Note that only some of register state for the REC can be set by KVM, the rest is defined by the RMM (zeroed). The register state then cannot be changed by KVM after the REC is created (except when the guest explicitly requests this e.g. by performing a PSCI call). Note that the function kvm_create_rec() is unused at this point, a future patch will add the call and remove the __maybe_unused attribute. Signed-off-by: Steven Price --- Changes since v14: * Handle partial REC creation better by NULLing rec->run, rec->rec_page and rec->sro when freeing. Changes since v13: * Support SRO for REC creation/destruction instead of auxiliary granules. Changes since v12: * Use the new range-based delegation RMI. Changes since v11: * Remove the KVM_ARM_VCPU_REC feature. User space no longer needs to configure each VCPU separately, RECs are created on the first VCPU run of the guest. Changes since v9: * Size the aux_pages array according to the PAGE_SIZE of the host. Changes since v7: * Add comment explaining the aux_pages array. * Rename "undeleted_failed" variable to "should_free" to avoid a confusing double negative. Changes since v6: * Avoid reporting the KVM_ARM_VCPU_REC feature if the guest isn't a realm guest. * Support host page size being larger than RMM's granule size when allocating/freeing aux granules. Changes since v5: * Separate the concept of vcpu_is_rec() and kvm_arm_vcpu_rec_finalized() by using the KVM_ARM_VCPU_REC feature as the indication that the VCPU is a REC. Changes since v2: * Free rec->run earlier in kvm_destroy_realm() and adapt to previous patch= es. --- arch/arm64/include/asm/kvm_emulate.h | 5 ++ arch/arm64/include/asm/kvm_host.h | 3 + arch/arm64/include/asm/kvm_rmi.h | 16 +++++ arch/arm64/kvm/arm.c | 6 ++ arch/arm64/kvm/reset.c | 1 + arch/arm64/kvm/rmi.c | 100 +++++++++++++++++++++++++++ 6 files changed, 131 insertions(+) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index e26d6755279f..2e69fe494716 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -712,4 +712,9 @@ static inline bool kvm_realm_is_created(struct kvm *kvm) return kvm_is_realm(kvm) && kvm_realm_state(kvm) !=3D REALM_STATE_NONE; } =20 +static inline bool vcpu_is_rec(const struct kvm_vcpu *vcpu) +{ + return kvm_is_realm(vcpu->kvm); +} + #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 1a5e15040111..9b46b39ed11e 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -949,6 +949,9 @@ struct kvm_vcpu_arch { =20 /* Hyp-readable copy of kvm_vcpu::pid */ pid_t pid; + + /* Realm meta data */ + struct realm_rec rec; }; =20 /* diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 31ec856561c6..ccd09d55c69f 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -77,12 +77,28 @@ struct realm { bool rtts_destroyed; }; =20 +/** + * struct realm_rec - Additional per VCPU data for a Realm + * + * @mpidr: MPIDR (Multiprocessor Affinity Register) value to identify this= VCPU + * @rec_page: Kernel VA of the RMM's private page for this REC + * @run: Kernel VA of the RmiRecRun structure shared with the RMM + * @sro: A preallocated SRO state context + */ +struct realm_rec { + unsigned long mpidr; + void *rec_page; + struct rec_run *run; + struct rmi_sro_state *sro; +}; + void kvm_init_rmi(void); u32 kvm_rmm_ipa_limit(void); =20 int kvm_init_realm(struct kvm *kvm); void kvm_destroy_realm(struct kvm *kvm); int kvm_realm_teardown_stage2(struct kvm *kvm); +void kvm_destroy_rec(struct kvm_vcpu *vcpu); =20 static inline bool kvm_realm_is_private_address(struct realm *realm, unsigned long addr) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 9881fd6c511c..38fac98cd6a4 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -589,6 +589,8 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) /* Force users to call KVM_ARM_VCPU_INIT */ vcpu_clear_flag(vcpu, VCPU_INITIALIZED); =20 + vcpu->arch.rec.mpidr =3D INVALID_HWID; + vcpu->arch.mmu_page_cache.gfp_zero =3D __GFP_ZERO; =20 /* Set up the timer */ @@ -1668,6 +1670,10 @@ static int kvm_vcpu_init_check_features(struct kvm_v= cpu *vcpu, if (test_bit(KVM_ARM_VCPU_HAS_EL2, &features)) return -EINVAL; =20 + /* Realms are incompatible with AArch32 */ + if (vcpu_is_rec(vcpu)) + return -EINVAL; + return 0; } =20 diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index b963fd975aac..c18cdca7d125 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -161,6 +161,7 @@ void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) free_page((unsigned long)vcpu->arch.ctxt.vncr_array); kfree(vcpu->arch.vncr_tlb); kfree(vcpu->arch.ccsidr); + kvm_destroy_rec(vcpu); } =20 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index db32448a0fc1..aa97ad5fd7e9 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -203,6 +203,106 @@ int kvm_realm_teardown_stage2(struct kvm *kvm) return realm_destroy_rtts(kvm); } =20 +static int __maybe_unused kvm_create_rec(struct kvm_vcpu *vcpu) +{ + struct user_pt_regs *vcpu_regs =3D vcpu_gp_regs(vcpu); + unsigned long mpidr =3D kvm_vcpu_get_mpidr_aff(vcpu); + struct realm *realm =3D &vcpu->kvm->arch.realm; + struct realm_rec *rec =3D &vcpu->arch.rec; + unsigned long rec_page_phys; + struct rec_params *params; + int r, i; + + if (rec->run) + return -EBUSY; + + /* + * The RMM will report PSCI v1.0 to Realms and the KVM_ARM_VCPU_PSCI_0_2 + * flag covers v0.2 and onwards. + */ + if (!vcpu_has_feature(vcpu, KVM_ARM_VCPU_PSCI_0_2)) + return -EINVAL; + + BUILD_BUG_ON(sizeof(*params) > PAGE_SIZE); + BUILD_BUG_ON(sizeof(*rec->run) > PAGE_SIZE); + + params =3D (struct rec_params *)get_zeroed_page(GFP_KERNEL); + rec->rec_page =3D (void *)__get_free_page(GFP_KERNEL); + rec->run =3D (struct rec_run *)get_zeroed_page(GFP_KERNEL); + rec->sro =3D kmalloc_obj(*rec->sro); + if (!params || !rec->rec_page || !rec->run || !rec->sro) { + r =3D -ENOMEM; + goto out_free_pages; + } + + for (i =3D 0; i < ARRAY_SIZE(params->gprs); i++) + params->gprs[i] =3D vcpu_regs->regs[i]; + + params->pc =3D vcpu_regs->pc; + + if (vcpu->vcpu_id =3D=3D 0) + params->flags |=3D REC_PARAMS_FLAG_RUNNABLE; + + rec_page_phys =3D virt_to_phys(rec->rec_page); + + if (rmi_delegate_page(rec_page_phys)) { + r =3D -ENXIO; + goto out_free_pages; + } + + params->mpidr =3D mpidr; + + if (rmi_rec_create(virt_to_phys(realm->rd), rec_page_phys, + virt_to_phys(params), rec->sro)) { + r =3D -ENXIO; + goto out_undelegate_rmm_rec; + } + + rec->mpidr =3D mpidr; + + free_page((unsigned long)params); + return 0; + +out_undelegate_rmm_rec: + if (WARN_ON(rmi_undelegate_page(rec_page_phys))) + rec->rec_page =3D NULL; +out_free_pages: + free_page((unsigned long)rec->run); + free_page((unsigned long)rec->rec_page); + free_page((unsigned long)params); + kfree(rec->sro); + rec->run =3D NULL; + rec->rec_page =3D NULL; + rec->sro =3D NULL; + return r; +} + +void kvm_destroy_rec(struct kvm_vcpu *vcpu) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + unsigned long rec_page_phys; + + if (!vcpu_is_rec(vcpu)) + return; + + if (!rec->run) { + /* Nothing to do if the VCPU hasn't been finalized */ + return; + } + + rec_page_phys =3D virt_to_phys(rec->rec_page); + + if (WARN_ON(rmi_rec_destroy(rec_page_phys, rec->sro))) + return; + + free_page((unsigned long)rec->run); + kfree(rec->sro); + free_delegated_page(rec_page_phys); + rec->run =3D NULL; + rec->sro =3D NULL; + rec->rec_page =3D NULL; +} + void kvm_destroy_realm(struct kvm *kvm) { struct realm *realm =3D &kvm->arch.realm; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CD45238737B; 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V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 12/37] KVM: arm64: CCA: Support the VGIC in realms Date: Wed, 15 Jul 2026 15:28:14 +0100 Message-ID: <20260715142841.80544-13-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM provides emulation of a VGIC to the realm guest. With RMM v2.0 the registers are passed in the system registers so this works similar to a normal guest, but kvm_arch_vcpu_put() need reordering to early out, and realm guests don't support GICv2 even if the host does. Signed-off-by: Steven Price --- Changes from v12: * GIC registers are now passed in the system registers rather than via rec_entry/rec_exit which removes most of the changes. Changes from v11: * Minor changes to align with the previous patches. Note that the VGIC handling will change with RMM v2.0. Changes from v10: * Make sure we sync the VGIC v4 state, and only populate valid lrs from the list. Changes from v9: * Copy gicv3_vmcr from the RMM at the same time as gicv3_hcr rather than having to handle that as a special case. Changes from v8: * Propagate gicv3_hcr to from the RMM. Changes from v5: * Handle RMM providing fewer GIC LRs than the hardware supports. --- arch/arm64/kvm/arm.c | 11 ++++++++--- arch/arm64/kvm/vgic/vgic-init.c | 2 +- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 38fac98cd6a4..2959a1451232 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -791,19 +791,24 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) kvm_call_hyp_nvhe(__pkvm_vcpu_put); } =20 + kvm_timer_vcpu_put(vcpu); + kvm_vgic_put(vcpu); kvm_vcpu_put_debug(vcpu); + + vcpu->cpu =3D -1; + + if (vcpu_is_rec(vcpu)) + return; + kvm_arch_vcpu_put_fp(vcpu); if (has_vhe()) kvm_vcpu_put_vhe(vcpu); - kvm_timer_vcpu_put(vcpu); - kvm_vgic_put(vcpu); kvm_vcpu_pmu_restore_host(vcpu); if (vcpu_has_nv(vcpu)) kvm_vcpu_put_hw_mmu(vcpu); kvm_arm_vmid_clear_active(); =20 vcpu_clear_on_unsupported_cpu(vcpu); - vcpu->cpu =3D -1; } =20 static void __kvm_arm_vcpu_power_off(struct kvm_vcpu *vcpu) diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-ini= t.c index 907057881b26..fd77db35ef02 100644 --- a/arch/arm64/kvm/vgic/vgic-init.c +++ b/arch/arm64/kvm/vgic/vgic-init.c @@ -81,7 +81,7 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) * the proper checks already. */ if (type =3D=3D KVM_DEV_TYPE_ARM_VGIC_V2 && - !kvm_vgic_global_state.can_emulate_gicv2) + (!kvm_vgic_global_state.can_emulate_gicv2 || kvm_is_realm(kvm))) return -ENODEV; =20 /* --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 47430386561; Wed, 15 Jul 2026 14:29:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125802; cv=none; b=lXl9FNRI05C0/WDv2mCabrWrQ6Rq2cL4KhP/s6IQgJcfkJ2ZG9KDoltR9YYGjq0Y4j+j0wub2eGO3Q+eEgsis3oSaYQQL7L8UkDpT2EU/2U9fy4kBsstT7OzLIbo6w7RO6OUdfzl+40mNtvzpIxIfrNORxGn79bg96se16OI0FM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125802; c=relaxed/simple; bh=ALLLCbjfHABpvO+YbrVszcEBpAomTIT3qE5M78Zf9q0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SUlhyxPXnbw4AbX4OynTQZbanLxwyvFVBFNOheOAded6leLuXRY6kBA7FgUS7O94zSJCxobF6eGMm+atHcdCQzja9hFwdtk3WBHy/XUTdNZiDVhb4gAYLOY099BwOgBi1+ZAW+gjTMAu3fuvCpxN+TUVMAGqQ2yKbqRFdJhtnuA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=iFCnmRDM; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="iFCnmRDM" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2852F153B; Wed, 15 Jul 2026 07:29:53 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id F0D5F3F7B4; Wed, 15 Jul 2026 07:29:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125797; bh=ALLLCbjfHABpvO+YbrVszcEBpAomTIT3qE5M78Zf9q0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iFCnmRDM0jeVC9Yrqx/QO2Lz8C+Ex5cCZgAmxrJenWt9ZOD2mBhtpSoY8uaPYujWl N3WAtbiWFZhtSXtbjuaveZc2iratk7L+Xu581qWJxz6JihSbBMGelwsGOh6+d51DS6 eUDm3mBrJD9xeLEN6e0s1lCzPpJhvS2UyJFiCREM= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 13/37] KVM: arm64: CCA: Support timers in realm RECs Date: Wed, 15 Jul 2026 15:28:15 +0100 Message-ID: <20260715142841.80544-14-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM keeps track of the timer while the realm REC is running, but on exit to the normal world KVM is responsible for handling the timers. A later patch adds the support for propagating the timer values from the exit data structure and calling kvm_realm_timers_update(). Signed-off-by: Steven Price --- Changes since v14: * Special case in kvm_timer_vcpu_load()/kvm_timer_vcpu_put() the timer handling. Changes since v12: * Adapt to upstream changes. Changes since v11: * Drop the kvm_is_realm() check from timer_set_offset(). We already ensure that the offset is 0 when calling the function. Changes since v10: * KVM_CAP_COUNTER_OFFSET is now already hidden by a previous patch. Changes since v9: * No need to move the call to kvm_timer_unblocking() in kvm_timer_vcpu_load(). Changes since v7: * Hide KVM_CAP_COUNTER_OFFSET for realm guests. --- arch/arm64/kvm/arch_timer.c | 38 +++++++++++++++++++++++++++++++++--- include/kvm/arm_arch_timer.h | 2 ++ 2 files changed, 37 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c index 4155fe89b58a..fdd68f1f5b7b 100644 --- a/arch/arm64/kvm/arch_timer.c +++ b/arch/arm64/kvm/arch_timer.c @@ -482,6 +482,20 @@ static void kvm_timer_update_irq(struct kvm_vcpu *vcpu= , bool new_level, timer_ctx); } =20 +void kvm_realm_timers_update(struct kvm_vcpu *vcpu) +{ + struct arch_timer_cpu *arch_timer =3D &vcpu->arch.timer_cpu; + int i; + + for (i =3D 0; i < NR_KVM_EL0_TIMERS; i++) { + struct arch_timer_context *timer =3D &arch_timer->timers[i]; + bool status =3D timer_get_ctl(timer) & ARCH_TIMER_CTRL_IT_STAT; + bool level =3D kvm_timer_enabled(timer) && status; + + kvm_timer_update_irq(vcpu, level, timer); + } +} + /* Only called for a fully emulated timer */ static void timer_emulate(struct arch_timer_context *ctx) { @@ -888,6 +902,11 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; =20 + if (vcpu_is_rec(vcpu)) { + kvm_timer_unblocking(vcpu); + return; + } + get_timer_map(vcpu, &map); =20 if (static_branch_likely(&has_gic_active_state)) { @@ -923,6 +942,12 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu) if (unlikely(!timer->enabled)) return; =20 + if (vcpu_is_rec(vcpu)) { + if (kvm_vcpu_is_blocking(vcpu)) + kvm_timer_blocking(vcpu); + return; + } + get_timer_map(vcpu, &map); =20 timer_save_state(map.direct_vtimer); @@ -1073,7 +1098,7 @@ static void timer_context_init(struct kvm_vcpu *vcpu,= int timerid) =20 ctxt->timer_id =3D timerid; =20 - if (!kvm_vm_is_protected(vcpu->kvm)) { + if (!kvm_vm_is_protected(vcpu->kvm) && !vcpu_is_rec(vcpu)) { if (timerid =3D=3D TIMER_VTIMER) ctxt->offset.vm_offset =3D &kvm->arch.timer_data.voffset; else @@ -1104,7 +1129,7 @@ void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu) timer_context_init(vcpu, i); =20 /* Synchronize offsets across timers of a VM if not already provided */ - if (!vcpu_is_protected(vcpu) && + if (!vcpu_is_protected(vcpu) && !vcpu_is_rec(vcpu) && !test_bit(KVM_ARCH_FLAG_VM_COUNTER_OFFSET, &vcpu->kvm->arch.flags)) { timer_set_offset(vcpu_vtimer(vcpu), kvm_phys_timer_read()); timer_set_offset(vcpu_ptimer(vcpu), 0); @@ -1600,6 +1625,13 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) return -EINVAL; } =20 + /* + * We don't use mapped IRQs for Realms because the RMI doesn't allow + * us setting the LR.HW bit in the VGIC. + */ + if (vcpu_is_rec(vcpu)) + return 0; + get_timer_map(vcpu, &map); =20 ops =3D vgic_is_v5(vcpu->kvm) ? &arch_timer_irq_ops_vgic_v5 : @@ -1729,7 +1761,7 @@ int kvm_vm_ioctl_set_counter_offset(struct kvm *kvm, if (offset->reserved) return -EINVAL; =20 - if (kvm_vm_is_protected(kvm)) + if (kvm_vm_is_protected(kvm) || kvm_is_realm(kvm)) return -EINVAL; =20 mutex_lock(&kvm->lock); diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h index 15a4f97f8105..31e48d5dbc31 100644 --- a/include/kvm/arm_arch_timer.h +++ b/include/kvm/arm_arch_timer.h @@ -108,6 +108,8 @@ int kvm_arm_timer_set_attr(struct kvm_vcpu *vcpu, struc= t kvm_device_attr *attr); int kvm_arm_timer_get_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *= attr); int kvm_arm_timer_has_attr(struct kvm_vcpu *vcpu, struct kvm_device_attr *= attr); =20 +void kvm_realm_timers_update(struct kvm_vcpu *vcpu); + u64 kvm_phys_timer_read(void); =20 void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu); --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D076E396B96; Wed, 15 Jul 2026 14:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125804; cv=none; b=d7fDPIS/nLmaNcjQCsTLfiYXlhweyvCGR2/h/5LduyMRgCW7FtUyVdzYGAd9h4jiVw3xK+O+gSbaJN008OYwNZAWKsscGvB8b/X7gLa1nk1JYS2PzMKM6Z165R4C/li+8YOx4k5yfYg45xc3gVRm02/Eo1G1sK/ixxzio8N8Ixs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125804; c=relaxed/simple; bh=6eG+MNECETE0oFosju2zgPAJsRKT5jskt3SD7r+mXj0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jFa4EL60Ix+8i6n6L5AkssEJuBCy2xDFRVV2A6ypHqPW3a0glPJR6vPs4AeFHsA+11FMB5pFrHViHNizfdomWFaEPzUxmTGDrbhuINu1tgiqQiFRMsPYaj7tKGEq0a7QumiKllXLlUQBwSTXndk2XkUrxut6RbJ5PCFCCCqaa+U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Uk6nBNw/; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Uk6nBNw/" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 332FC1576; Wed, 15 Jul 2026 07:29:58 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B819E3F7B4; Wed, 15 Jul 2026 07:29:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125802; bh=6eG+MNECETE0oFosju2zgPAJsRKT5jskt3SD7r+mXj0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Uk6nBNw/zKpsBzDiAtyj6t8FBUoTr++tHABEognOQo+ZuFik4bFiE69R2G5ei/nBx Q1X+6Gw0QNTPo7qLHH4cUH5oOlMwx6EAndpbYe8qPO3XjKWknWNvaNdSOUCe2WSjLr agEo6VYTYw3HSy+NnO4V701clmaJU/pagMAnCyZc= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 14/37] KVM: arm64: CCA: Handle realm enter/exit Date: Wed, 15 Jul 2026 15:28:16 +0100 Message-ID: <20260715142841.80544-15-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Entering a realm is done using a SMC call to the RMM. On exit the exit-codes need to be handled slightly differently to the normal KVM path so define our own functions for realm enter/exit and hook them in if the guest is a realm guest. Signed-off-by: Steven Price Reviewed-by: Gavin Shan --- Changes since v13: * The RMM is now required to provide an ESR value with the correct information to emulate MMIO, so we no longer need to hardcode 0s in rec_exit_sys_reg(). * The PSCI changes mean that there is a potential race when turning on a VCPU which can cause a RMI_ERROR_REC return. Exit to user space with -EAGAIN in this case. Changes since v12: * Call guest_state_{enter,exit}_irqoff() around rmi_rec_enter(). * Add handling of the IRQ exception case where IRQs need to be briefly enabled before exiting guest timing. Changes since v8: * Introduce kvm_rec_pre_enter() called before entering an atomic section to handle operations that might require memory allocation (specifically completing a RIPAS change introduced in a later patch). * Updates to align with upstream changes to hpfar_el2 which now (ab)uses HPFAR_EL2_NS as a valid flag. * Fix exit reason when racing with PSCI shutdown to return KVM_EXIT_SHUTDOWN rather than KVM_EXIT_UNKNOWN. Changes since v7: * A return of 0 from kvm_handle_sys_reg() doesn't mean the register has been read (although that can never happen in the current code). Tidy up the condition to handle any future refactoring. Changes since v6: * Use vcpu_err() rather than pr_err/kvm_err when there is an associated vcpu to the error. * Return -EFAULT for KVM_EXIT_MEMORY_FAULT as per the documentation for this exit type. * Split code handling a RIPAS change triggered by the guest to the following patch. Changes since v5: * For a RIPAS_CHANGE request from the guest perform the actual RIPAS change on next entry rather than immediately on the exit. This allows the VMM to 'reject' a RIPAS change by refusing to continue scheduling. Changes since v4: * Rename handle_rme_exit() to handle_rec_exit() * Move the loop to copy registers into the REC enter structure from the to rec_exit_handlers callbacks to kvm_rec_enter(). This fixes a bug where the handler exits to user space and user space wants to modify the GPRS. * Some code rearrangement in rec_exit_ripas_change(). Changes since v2: * realm_set_ipa_state() now provides an output parameter for the top_iap that was changed. Use this to signal the VMM with the correct range that has been transitioned. * Adapt to previous patch changes. --- arch/arm64/include/asm/kvm_rmi.h | 4 + arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 25 ++++- arch/arm64/kvm/rmi-exit.c | 182 +++++++++++++++++++++++++++++++ arch/arm64/kvm/rmi.c | 42 +++++++ 5 files changed, 249 insertions(+), 6 deletions(-) create mode 100644 arch/arm64/kvm/rmi-exit.c diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index ccd09d55c69f..b1e4cf0f6803 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -100,6 +100,10 @@ void kvm_destroy_realm(struct kvm *kvm); int kvm_realm_teardown_stage2(struct kvm *kvm); void kvm_destroy_rec(struct kvm_vcpu *vcpu); =20 +int kvm_rec_enter(struct kvm_vcpu *vcpu); +int kvm_rec_pre_enter(struct kvm_vcpu *vcpu); +int handle_rec_exit(struct kvm_vcpu *vcpu, int rec_run_status); + static inline bool kvm_realm_is_private_address(struct realm *realm, unsigned long addr) { diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index ed3cf30eb06e..4a2d52fdb6a2 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -16,7 +16,7 @@ CFLAGS_handle_exit.o +=3D -Wno-override-init kvm-y +=3D arm.o mmu.o mmio.o psci.o hypercalls.o pvtime.o \ inject_fault.o va_layout.o handle_exit.o config.o \ guest.o debug.o reset.o sys_regs.o stacktrace.o \ - vgic-sys-reg-v3.o fpsimd.o pkvm.o rmi.o \ + vgic-sys-reg-v3.o fpsimd.o pkvm.o rmi.o rmi-exit.o \ arch_timer.o trng.o vmid.o emulate-nested.o nested.o at.o \ vgic/vgic.o vgic/vgic-init.o \ vgic/vgic-irqfd.o vgic/vgic-v2.o \ diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 2959a1451232..534d33b7c67a 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1341,6 +1341,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) if (ret > 0) ret =3D check_vcpu_requests(vcpu); =20 + if (ret > 0 && vcpu_is_rec(vcpu)) + ret =3D kvm_rec_pre_enter(vcpu); + /* * Preparing the interrupts to be injected also * involves poking the GIC, which must be done in a @@ -1388,7 +1391,10 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) trace_kvm_entry(*vcpu_pc(vcpu)); guest_timing_enter_irqoff(); =20 - ret =3D kvm_arm_vcpu_enter_exit(vcpu); + if (vcpu_is_rec(vcpu)) + ret =3D kvm_rec_enter(vcpu); + else + ret =3D kvm_arm_vcpu_enter_exit(vcpu); =20 vcpu->mode =3D OUTSIDE_GUEST_MODE; vcpu->stat.exits++; @@ -1434,7 +1440,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) * context synchronization event) is necessary to ensure that * pending interrupts are taken. */ - if (ARM_EXCEPTION_CODE(ret) =3D=3D ARM_EXCEPTION_IRQ) { + if ((!vcpu_is_rec(vcpu) && ARM_EXCEPTION_CODE(ret) =3D=3D ARM_EXCEPTION_= IRQ) || + (vcpu_is_rec(vcpu) && vcpu->arch.rec.run->exit.exit_reason =3D=3D RM= I_EXIT_IRQ)) { local_irq_enable(); isb(); local_irq_disable(); @@ -1446,8 +1453,13 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) =20 trace_kvm_exit(ret, kvm_vcpu_trap_get_class(vcpu), *vcpu_pc(vcpu)); =20 - /* Exit types that need handling before we can be preempted */ - handle_exit_early(vcpu, ret); + if (!vcpu_is_rec(vcpu)) { + /* + * Exit types that need handling before we can be + * preempted + */ + handle_exit_early(vcpu, ret); + } =20 kvm_nested_sync_hwstate(vcpu); =20 @@ -1472,7 +1484,10 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) ret =3D ARM_EXCEPTION_IL; } =20 - ret =3D handle_exit(vcpu, ret); + if (vcpu_is_rec(vcpu)) + ret =3D handle_rec_exit(vcpu, ret); + else + ret =3D handle_exit(vcpu, ret); } =20 if (unlikely(!irqchip_in_kernel(vcpu->kvm))) diff --git a/arch/arm64/kvm/rmi-exit.c b/arch/arm64/kvm/rmi-exit.c new file mode 100644 index 000000000000..973250563d7b --- /dev/null +++ b/arch/arm64/kvm/rmi-exit.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023-2026 ARM Ltd. + */ + +#include +#include +#include + +#include +#include +#include +#include + +typedef int (*exit_handler_fn)(struct kvm_vcpu *vcpu); + +static int rec_exit_reason_notimpl(struct kvm_vcpu *vcpu) +{ + vcpu_err(vcpu, "Unhandled exit reason from realm (ESR: %#llx)\n", + kvm_vcpu_get_esr(vcpu)); + return -ENXIO; +} + +static int rec_exit_sync_dabt(struct kvm_vcpu *vcpu) +{ + return kvm_handle_guest_abort(vcpu); +} + +static int rec_exit_sync_iabt(struct kvm_vcpu *vcpu) +{ + vcpu_err(vcpu, "Unhandled instruction abort (ESR: %#llx).\n", + kvm_vcpu_get_esr(vcpu)); + return -ENXIO; +} + +static int rec_exit_sys_reg(struct kvm_vcpu *vcpu) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + unsigned long esr =3D kvm_vcpu_get_esr(vcpu); + int rt =3D kvm_vcpu_sys_get_rt(vcpu); + bool is_write =3D (esr & ESR_ELx_SYS64_ISS_DIR_MASK) =3D=3D ESR_ELx_SYS64= _ISS_DIR_WRITE; + int ret; + + if (is_write) + vcpu_set_reg(vcpu, rt, rec->run->exit.gprs[rt]); + + ret =3D kvm_handle_sys_reg(vcpu); + if (!is_write) + rec->run->enter.gprs[rt] =3D vcpu_get_reg(vcpu, rt); + + return ret; +} + +static exit_handler_fn rec_exit_handlers[] =3D { + [0 ... ESR_ELx_EC_MAX] =3D rec_exit_reason_notimpl, + [ESR_ELx_EC_SYS64] =3D rec_exit_sys_reg, + [ESR_ELx_EC_DABT_LOW] =3D rec_exit_sync_dabt, + [ESR_ELx_EC_IABT_LOW] =3D rec_exit_sync_iabt +}; + +static int rec_exit_psci(struct kvm_vcpu *vcpu) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + int i; + + for (i =3D 0; i < REC_RUN_GPRS; i++) + vcpu_set_reg(vcpu, i, rec->run->exit.gprs[i]); + + return kvm_smccc_call_handler(vcpu); +} + +static int rec_exit_ripas_change(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; + struct realm *realm =3D &kvm->arch.realm; + struct realm_rec *rec =3D &vcpu->arch.rec; + unsigned long base =3D rec->run->exit.ripas_base; + unsigned long top =3D rec->run->exit.ripas_top; + unsigned long ripas =3D rec->run->exit.ripas_value; + + if (!kvm_realm_is_private_address(realm, base) || + !kvm_realm_is_private_address(realm, top - 1)) { + vcpu_err(vcpu, "Invalid RIPAS_CHANGE for %#lx - %#lx, ripas: %#lx\n", + base, top, ripas); + /* Set RMI_REJECT bit */ + rec->run->enter.flags =3D REC_ENTER_FLAG_RIPAS_RESPONSE; + return -EINVAL; + } + + /* Exit to VMM, the actual RIPAS change is done on next entry */ + kvm_prepare_memory_fault_exit(vcpu, base, top - base, false, false, + ripas =3D=3D RMI_RAM); + + /* + * KVM_EXIT_MEMORY_FAULT requires an return code of -EFAULT, see the + * API documentation + */ + return -EFAULT; +} + +static void update_arch_timer_irq_lines(struct kvm_vcpu *vcpu) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + + __vcpu_assign_sys_reg(vcpu, CNTV_CTL_EL0, rec->run->exit.cntv_ctl); + __vcpu_assign_sys_reg(vcpu, CNTV_CVAL_EL0, rec->run->exit.cntv_cval); + __vcpu_assign_sys_reg(vcpu, CNTP_CTL_EL0, rec->run->exit.cntp_ctl); + __vcpu_assign_sys_reg(vcpu, CNTP_CVAL_EL0, rec->run->exit.cntp_cval); + + kvm_realm_timers_update(vcpu); +} + +/* + * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on + * proper exit to userspace. + */ +int handle_rec_exit(struct kvm_vcpu *vcpu, int rec_run_ret) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + u8 esr_ec =3D ESR_ELx_EC(rec->run->exit.esr); + unsigned long status, index; + + status =3D RMI_RETURN_STATUS(rec_run_ret); + index =3D RMI_RETURN_INDEX(rec_run_ret); + + /* + * If a PSCI_SYSTEM_OFF request raced with a vcpu executing, we might + * see the following status code and index indicating an attempt to run + * a REC when the RD state is SYSTEM_OFF. In this case, we just need to + * return to user space which can deal with the system event or will try + * to run the KVM VCPU again, at which point we will no longer attempt + * to enter the Realm because we will have a sleep request pending on + * the VCPU as a result of KVM's PSCI handling. + */ + if (status =3D=3D RMI_ERROR_REALM) { + vcpu->run->exit_reason =3D KVM_EXIT_SHUTDOWN; + return 0; + } + + /* + * If a VCPU has been turned on, but the REC state hasn't been updated + * we may experience RMI_ERROR_REC. Exit to the userspace with -EAGAIN + * for a retry. + */ + if (status =3D=3D RMI_ERROR_REC) + return -EAGAIN; + if (rec_run_ret) + return -ENXIO; + + vcpu->arch.fault.esr_el2 =3D rec->run->exit.esr; + vcpu->arch.fault.far_el2 =3D rec->run->exit.far; + /* HPFAR_EL2 is only valid for RMI_EXIT_SYNC */ + vcpu->arch.fault.hpfar_el2 =3D 0; + + update_arch_timer_irq_lines(vcpu); + + /* Reset the emulation flags for the next run of the REC */ + rec->run->enter.flags =3D 0; + + switch (rec->run->exit.exit_reason) { + case RMI_EXIT_SYNC: + /* + * HPFAR_EL2_NS is hijacked to indicate a valid HPFAR value, + * see __get_fault_info() + */ + vcpu->arch.fault.hpfar_el2 =3D rec->run->exit.hpfar | HPFAR_EL2_NS; + return rec_exit_handlers[esr_ec](vcpu); + case RMI_EXIT_IRQ: + case RMI_EXIT_FIQ: + case RMI_EXIT_SERROR: + return 1; + case RMI_EXIT_PSCI: + return rec_exit_psci(vcpu); + case RMI_EXIT_RIPAS_CHANGE: + return rec_exit_ripas_change(vcpu); + } + + kvm_pr_unimpl("Unsupported exit reason: %u\n", + rec->run->exit.exit_reason); + vcpu->run->exit_reason =3D KVM_EXIT_INTERNAL_ERROR; + return 0; +} diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index aa97ad5fd7e9..430b82c02d15 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -203,6 +203,48 @@ int kvm_realm_teardown_stage2(struct kvm *kvm) return realm_destroy_rtts(kvm); } =20 +/* + * kvm_rec_pre_enter - Complete operations before entering a REC + * + * Some operations require work to be completed before entering a realm. T= hat + * work may require memory allocation so cannot be done in the kvm_rec_ent= er() + * call. + * + * Return: 1 if we should enter the guest + * 0 if we should exit to userspace + * < 0 if we should exit to userspace, where the return value indicates + * an error + */ +int kvm_rec_pre_enter(struct kvm_vcpu *vcpu) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + + if (kvm_realm_state(vcpu->kvm) !=3D REALM_STATE_ACTIVE) + return -EINVAL; + + switch (rec->run->exit.exit_reason) { + case RMI_EXIT_HOST_CALL: + for (int i =3D 0; i < REC_RUN_GPRS; i++) + rec->run->enter.gprs[i] =3D vcpu_get_reg(vcpu, i); + break; + } + + return 1; +} + +int noinstr kvm_rec_enter(struct kvm_vcpu *vcpu) +{ + struct realm_rec *rec =3D &vcpu->arch.rec; + int ret; + + guest_state_enter_irqoff(); + ret =3D rmi_rec_enter(virt_to_phys(rec->rec_page), + virt_to_phys(rec->run)); + guest_state_exit_irqoff(); + + return ret; +} + static int __maybe_unused kvm_create_rec(struct kvm_vcpu *vcpu) { struct user_pt_regs *vcpu_regs =3D vcpu_gp_regs(vcpu); --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E2B1F39A04D; Wed, 15 Jul 2026 14:30:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125809; cv=none; b=XAIg8VOkgbkIle5Od1h++Bl8hVrOaroKDX9+2h2mvMd+Uq9mBSeaDZu/1mJ/wVO8aqK6ZfSyUEfmkkxOnDXEpIndGpQIQzbdeNdYVfCLDa1w7ZIOz7snmN1HvF4ShcBRv8CnTmzbVIxUeYFFC1OocChW9O+mNze83Ns5Iu1hNq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125809; c=relaxed/simple; bh=VER/7iDZloZKoBITKTwf0bwc2DOHOeZOB2ubtxmEj08=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g3S3lEqUwcY2tW1ikYSMyfTOeCL3pwJObyal2k+TO3Ao9QnAQ+ymIbLqdScb8i/OvFLsKM1bZEdHpyuyvSTefnbAZs9oknKMLSZpHxI86MyLDUKJf4JY76Psgc4W7hQjsZegEAQxMQvb7D23QoCg4oeq9ThzXZWuMHQxSqfx0UQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=e845u5qJ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="e845u5qJ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C7F21595; Wed, 15 Jul 2026 07:30:03 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C972E3F7B4; Wed, 15 Jul 2026 07:30:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125807; bh=VER/7iDZloZKoBITKTwf0bwc2DOHOeZOB2ubtxmEj08=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e845u5qJ2t+B23Z8lI+AgTtMWwXnGL0glXcvMH00NblDc/I9+Rc/Qd9uMQK0LDQGI 9wA3Jh2MK8VZU+DPOm20Iia2TsWvDWN0AsWOnixCgRIJgENJotdaHD3mVWWVtsYbXB qy1W8WI5lWmbPBs2HkL7n+yjNhFqHUXKIBM868gY= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 15/37] KVM: arm64: CCA: Handle RMI_EXIT_RIPAS_CHANGE Date: Wed, 15 Jul 2026 15:28:17 +0100 Message-ID: <20260715142841.80544-16-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The guest can request that a region of its protected address space is switched between RIPAS_RAM and RIPAS_EMPTY (and back) using RSI_IPA_STATE_SET. This causes a guest exit with the RMI_EXIT_RIPAS_CHANGE code. We treat this as a request to convert a protected region to unprotected (or back), exiting to the VMM to make the necessary changes to the guest_memfd and memslot mappings. On the next entry the RIPAS changes are committed by making RMI_RTT_SET_RIPAS calls. The VMM may wish to reject the RIPAS change requested by the guest. For now it can only do this by no longer scheduling the VCPU as we don't currently have a usecase for returning that rejection to the guest, but by postponing the RMI_RTT_SET_RIPAS changes to entry we leave the door open for adding a new ioctl in the future for this purpose. Signed-off-by: Steven Price --- Changes since v14: * Use addition rather than bitwise OR for adding the shared_bit in realm_unmap_shared_range(), this handles the case where the region includes the last address (which means 'end' already has the bit set). Changes since v13: * Switch to the new RMI_RTT_UNPROT_UNMAP range-based API. * Drop ugly hack for RMM bug which errored when the RIPAS was already set to the desired value. Changes since v12: * Switch to the new RMM v2.0 RMI_RTT_DATA_UNMAP which can unmap an address range. Changes since v11: * Combine the "Allow VMM to set RIPAS" patch into this one to avoid adding functions before they are used. * Drop the CAP for setting RIPAS and adapt to changes from previous patches. Changes since v10: * Add comment explaining the assignment of rec->run->exit.ripas_base in kvm_complete_ripas_change(). Changes since v8: * Make use of ripas_change() from a previous patch to implement realm_set_ipa_state(). * Update exit.ripas_base after a RIPAS change so that, if instead of entering the guest we exit to user space, we don't attempt to repeat the RIPAS change (triggering an error from the RMM). Changes since v7: * Rework the loop in realm_set_ipa_state() to make it clear when the 'next' output value of rmi_rtt_set_ripas() is used. New patch for v7: The code was previously split awkwardly between two other patches. --- arch/arm64/include/asm/kvm_rmi.h | 6 + arch/arm64/kvm/mmu.c | 8 +- arch/arm64/kvm/rmi.c | 457 +++++++++++++++++++++++++++++++ 3 files changed, 468 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index b1e4cf0f6803..5461c49bea4d 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -104,6 +104,12 @@ int kvm_rec_enter(struct kvm_vcpu *vcpu); int kvm_rec_pre_enter(struct kvm_vcpu *vcpu); int handle_rec_exit(struct kvm_vcpu *vcpu, int rec_run_status); =20 +void kvm_realm_unmap_range(struct kvm *kvm, + unsigned long ipa, + unsigned long size, + bool unmap_private, + bool may_block); + static inline bool kvm_realm_is_private_address(struct realm *realm, unsigned long addr) { diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index cd06881c1497..dcc2ab08d0e4 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -319,6 +319,7 @@ static void invalidate_icache_guest_page(void *va, size= _t size) * @start: The intermediate physical base address of the range to unmap * @size: The size of the area to unmap * @may_block: Whether or not we are permitted to block + * @only_shared: If true then protected mappings should not be unmapped * * Clear a range of stage-2 mappings, lowering the various ref-counts. Mu= st * be called while holding mmu_lock (unless for freeing the stage2 pgd bef= ore @@ -326,7 +327,7 @@ static void invalidate_icache_guest_page(void *va, size= _t size) * with things behind our backs. */ static void __unmap_stage2_range(struct kvm_s2_mmu *mmu, phys_addr_t start= , u64 size, - bool may_block) + bool may_block, bool only_shared) { struct kvm *kvm =3D kvm_s2_mmu_to_kvm(mmu); phys_addr_t end =3D start + size; @@ -343,7 +344,7 @@ void kvm_stage2_unmap_range(struct kvm_s2_mmu *mmu, phy= s_addr_t start, if (kvm_vm_is_protected(kvm_s2_mmu_to_kvm(mmu))) return; =20 - __unmap_stage2_range(mmu, start, size, may_block); + __unmap_stage2_range(mmu, start, size, may_block, false); } =20 void kvm_stage2_flush_range(struct kvm_s2_mmu *mmu, phys_addr_t addr, phys= _addr_t end) @@ -2467,7 +2468,8 @@ bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_= gfn_range *range) =20 __unmap_stage2_range(&kvm->arch.mmu, range->start << PAGE_SHIFT, (range->end - range->start) << PAGE_SHIFT, - range->may_block); + range->may_block, + !(range->attr_filter & KVM_FILTER_PRIVATE)); =20 kvm_nested_s2_unmap(kvm, range->may_block); return false; diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 430b82c02d15..1ef676eed172 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -34,6 +34,83 @@ static int get_start_level(struct realm *realm) return 4 - stage2_pgtable_levels(realm->ia_bits); } =20 +static int find_map_level(struct realm *realm, + unsigned long start, + unsigned long end) +{ + int level =3D KVM_PGTABLE_LAST_LEVEL; + + while (level > get_start_level(realm)) { + unsigned long map_size =3D rmi_rtt_level_mapsize(level - 1); + + if (!IS_ALIGNED(start, map_size) || + (start + map_size) > end) + break; + + level--; + } + + return level; +} + +static unsigned long rmi_range_entry_size(int rmi_size) +{ + if (WARN_ON(rmi_size > KVM_PGTABLE_LAST_LEVEL)) + return 0; + + return kvm_granule_size(KVM_PGTABLE_LAST_LEVEL - rmi_size); +} + +static int undelegate_range_desc(unsigned long desc) +{ + unsigned long size =3D rmi_range_entry_size(RMI_ADDR_RANGE_SIZE(desc)); + unsigned long count =3D RMI_ADDR_RANGE_COUNT(desc); + unsigned long addr =3D RMI_ADDR_RANGE_ADDR(desc); + unsigned long state =3D RMI_ADDR_RANGE_STATE(desc); + + if (state =3D=3D RMI_OP_MEM_UNDELEGATED) + return 0; + + if (size * count =3D=3D 0) + return 0; + + return rmi_undelegate_range(addr, size * count); +} + +static phys_addr_t alloc_delegated_granule(struct kvm_mmu_memory_cache *mc) +{ + phys_addr_t phys; + void *virt; + + if (mc) { + virt =3D kvm_mmu_memory_cache_alloc(mc); + } else { + virt =3D (void *)__get_free_page(GFP_ATOMIC | __GFP_ZERO | + __GFP_ACCOUNT); + } + + if (!virt) + return PHYS_ADDR_MAX; + + phys =3D virt_to_phys(virt); + if (rmi_delegate_page(phys)) { + free_page((unsigned long)virt); + return PHYS_ADDR_MAX; + } + + return phys; +} + +static phys_addr_t alloc_rtt(struct kvm_mmu_memory_cache *mc) +{ + phys_addr_t phys =3D alloc_delegated_granule(mc); + + if (phys !=3D PHYS_ADDR_MAX) + kvm_account_pgtable_pages(phys_to_virt(phys), 1); + + return phys; +} + static void free_rtt(phys_addr_t phys) { if (free_delegated_page(phys)) @@ -42,6 +119,32 @@ static void free_rtt(phys_addr_t phys) kvm_account_pgtable_pages(phys_to_virt(phys), -1); } =20 +static int realm_rtt_create(struct realm *realm, + unsigned long addr, + int level, + phys_addr_t phys) +{ + addr =3D ALIGN_DOWN(addr, rmi_rtt_level_mapsize(level - 1)); + return rmi_rtt_create(virt_to_phys(realm->rd), phys, addr, level); +} + +static int realm_rtt_fold(struct realm *realm, + unsigned long addr, + int level, + phys_addr_t *rtt_granule) +{ + unsigned long out_rtt; + int ret; + + addr =3D ALIGN_DOWN(addr, rmi_rtt_level_mapsize(level - 1)); + ret =3D rmi_rtt_fold(virt_to_phys(realm->rd), addr, level, &out_rtt); + + if (rtt_granule) + *rtt_granule =3D out_rtt; + + return ret; +} + /* * realm_rtt_destroy - Destroy an RTT at @level for @addr. * @@ -65,6 +168,38 @@ static int realm_rtt_destroy(struct realm *realm, unsig= ned long addr, return ret; } =20 +static int realm_create_rtt_levels(struct realm *realm, + unsigned long ipa, + int level, + int max_level, + struct kvm_mmu_memory_cache *mc) +{ + while (level++ < max_level) { + phys_addr_t rtt =3D alloc_rtt(mc); + int ret; + + if (rtt =3D=3D PHYS_ADDR_MAX) + return -ENOMEM; + + ret =3D realm_rtt_create(realm, ipa, level, rtt); + if (RMI_RETURN_STATUS(ret) =3D=3D RMI_ERROR_RTT && + RMI_RETURN_INDEX(ret) =3D=3D level - 1) { + /* The RTT already exists, continue */ + free_rtt(rtt); + continue; + } + + if (ret) { + WARN(1, "Failed to create RTT at level %d: %d\n", + level, ret); + free_rtt(rtt); + return -ENXIO; + } + } + + return 0; +} + static int realm_tear_down_rtt_level(struct realm *realm, int level, unsigned long start, unsigned long end) { @@ -159,6 +294,62 @@ static int realm_tear_down_rtt_range(struct realm *rea= lm, start, end); } =20 +/* + * Returns 0 on successful fold, a negative value on error, a positive val= ue if + * we were not able to fold all tables at this level. + */ +static int realm_fold_rtt_level(struct realm *realm, int level, + unsigned long start, unsigned long end) +{ + int not_folded =3D 0; + ssize_t map_size; + unsigned long addr, next_addr; + + if (WARN_ON(level > KVM_PGTABLE_LAST_LEVEL)) + return -EINVAL; + + map_size =3D rmi_rtt_level_mapsize(level - 1); + + for (addr =3D start; addr < end; addr =3D next_addr) { + phys_addr_t rtt_granule; + int ret; + unsigned long align_addr =3D ALIGN(addr, map_size); + + next_addr =3D ALIGN(addr + 1, map_size); + + ret =3D realm_rtt_fold(realm, align_addr, level, &rtt_granule); + + switch (RMI_RETURN_STATUS(ret)) { + case RMI_SUCCESS: + free_rtt(rtt_granule); + break; + case RMI_ERROR_RTT: + if (level =3D=3D KVM_PGTABLE_LAST_LEVEL || + RMI_RETURN_INDEX(ret) < level) { + not_folded++; + break; + } + /* Recurse a level deeper */ + ret =3D realm_fold_rtt_level(realm, + level + 1, + addr, + next_addr); + if (ret < 0) { + return ret; + } else if (ret =3D=3D 0) { + /* Try again at this level */ + next_addr =3D addr; + } + break; + default: + WARN_ON(1); + return -ENXIO; + } + } + + return not_folded; +} + static int realm_destroy_rtts(struct kvm *kvm) { struct realm *realm =3D &kvm->arch.realm; @@ -203,6 +394,269 @@ int kvm_realm_teardown_stage2(struct kvm *kvm) return realm_destroy_rtts(kvm); } =20 +static void realm_unmap_shared_range(struct kvm *kvm, + unsigned long start, + unsigned long end, + bool may_block) +{ + struct realm *realm =3D &kvm->arch.realm; + unsigned long rd =3D virt_to_phys(realm->rd); + unsigned long next_addr, addr; + unsigned long shared_bit =3D BIT(realm->ia_bits - 1); + + if (start >=3D end) + return; + + start +=3D shared_bit; + end +=3D shared_bit; + + for (addr =3D start; addr < end; addr =3D next_addr) { + int ret; + + ret =3D rmi_rtt_unprot_unmap(rd, addr, end, RMI_ADDR_TYPE_NONE, + 0, &next_addr, NULL, NULL); + switch (RMI_RETURN_STATUS(ret)) { + case RMI_SUCCESS: + break; + case RMI_ERROR_RTT: { + int err_level =3D RMI_RETURN_INDEX(ret); + int level =3D find_map_level(realm, addr, end); + + if (err_level >=3D level) { + /* Nothing present, so skip */ + next_addr =3D addr + rmi_rtt_level_mapsize(err_level); + break; + } + + ret =3D realm_create_rtt_levels(realm, addr, err_level, + level, NULL); + if (WARN_ON(ret)) + return; + /* Retry with the RTT levels in place */ + next_addr =3D addr; + break; + } + default: + WARN_ON(1); + return; + } + + if (may_block) + cond_resched_rwlock_write(&kvm->mmu_lock); + } + + realm_fold_rtt_level(realm, get_start_level(realm) + 1, + start, end); +} + +static void realm_unmap_private_range(struct kvm *kvm, + unsigned long start, + unsigned long end, + bool may_block) +{ + struct realm *realm =3D &kvm->arch.realm; + unsigned long rd =3D virt_to_phys(realm->rd); + unsigned long next_addr, addr; + int ret; + + for (addr =3D start; addr < end; addr =3D next_addr) { + unsigned long out_range; + unsigned long flags =3D RMI_ADDR_TYPE_SINGLE; + /* TODO: Optimise using RMI_ADDR_TYPE_LIST */ + +retry: + ret =3D rmi_rtt_data_unmap(rd, addr, end, flags, 0, + &next_addr, &out_range, NULL); + + if (RMI_RETURN_STATUS(ret) =3D=3D RMI_ERROR_RTT) { + phys_addr_t rtt; + + if (next_addr > addr) + continue; /* UNASSIGNED */ + + rtt =3D alloc_rtt(NULL); + if (WARN_ON(rtt =3D=3D PHYS_ADDR_MAX)) + return; + ret =3D realm_rtt_create(realm, addr, + RMI_RETURN_INDEX(ret) + 1, rtt); + if (WARN_ON(ret)) { + free_rtt(rtt); + return; + } + goto retry; + } else if (WARN_ON(ret)) { + continue; + } + + ret =3D undelegate_range_desc(out_range); + if (WARN_ON(ret)) + break; + + if (may_block) + cond_resched_rwlock_write(&kvm->mmu_lock); + } + + realm_fold_rtt_level(realm, get_start_level(realm) + 1, + start, end); +} + +void kvm_realm_unmap_range(struct kvm *kvm, unsigned long start, + unsigned long size, bool unmap_private, + bool may_block) +{ + unsigned long end =3D start + size; + struct realm *realm =3D &kvm->arch.realm; + + if (!kvm_realm_is_created(kvm)) + return; + + end =3D min(BIT(realm->ia_bits - 1), end); + + realm_unmap_shared_range(kvm, start, end, may_block); + if (unmap_private) + realm_unmap_private_range(kvm, start, end, may_block); +} + +enum ripas_action { + RIPAS_INIT, + RIPAS_SET, +}; + +static int ripas_change(struct kvm *kvm, + struct kvm_vcpu *vcpu, + unsigned long ipa, + unsigned long end, + enum ripas_action action, + unsigned long *top_ipa) +{ + struct realm *realm =3D &kvm->arch.realm; + phys_addr_t rd_phys =3D virt_to_phys(realm->rd); + phys_addr_t rec_phys; + struct kvm_mmu_memory_cache *memcache =3D NULL; + int ret =3D 0; + + if (vcpu) { + rec_phys =3D virt_to_phys(vcpu->arch.rec.rec_page); + memcache =3D &vcpu->arch.mmu_page_cache; + + WARN_ON(action !=3D RIPAS_SET); + } else { + WARN_ON(action !=3D RIPAS_INIT); + } + + while (ipa < end) { + unsigned long next =3D ~0; + + switch (action) { + case RIPAS_INIT: + ret =3D rmi_rtt_init_ripas(rd_phys, ipa, end, &next); + break; + case RIPAS_SET: + ret =3D rmi_rtt_set_ripas(rd_phys, rec_phys, ipa, end, + &next); + break; + } + + switch (RMI_RETURN_STATUS(ret)) { + case RMI_SUCCESS: + ipa =3D next; + break; + case RMI_ERROR_RTT: { + int err_level =3D RMI_RETURN_INDEX(ret); + int level =3D find_map_level(realm, ipa, end); + + /* + * If the operation failed at deeper level than + * what is required for the address range, this + * implies encountering an unexpected entry, + * (e.g., RIPAS_DESTROYED), which the RMM prevents + * us from modifying. This is only applicable for + * RMI_RTT_INIT_RIPAS. All the other requests + * are generated by the Realm and thus RMM should + * be able to allow the transition. + */ + if (action =3D=3D RIPAS_INIT && WARN_ON_ONCE(err_level >=3D level)) + return -ENXIO; + + ret =3D realm_create_rtt_levels(realm, ipa, err_level, + level, memcache); + if (ret) + goto out; + /* Retry with the RTT levels in place */ + break; + } + default: + WARN_ON(1); + ret =3D -ENXIO; + goto out; + } + } + +out: + if (top_ipa) + *top_ipa =3D ipa; + + return ret; +} + +static int realm_set_ipa_state(struct kvm_vcpu *vcpu, + unsigned long start, + unsigned long end, + unsigned long ripas, + unsigned long *top_ipa) +{ + struct kvm *kvm =3D vcpu->kvm; + int ret =3D ripas_change(kvm, vcpu, start, end, RIPAS_SET, top_ipa); + + if (!ret && ripas =3D=3D RMI_EMPTY && *top_ipa !=3D start) + realm_unmap_private_range(kvm, start, *top_ipa, false); + + return ret; +} + +static void kvm_complete_ripas_change(struct kvm_vcpu *vcpu) +{ + struct kvm *kvm =3D vcpu->kvm; + struct realm_rec *rec =3D &vcpu->arch.rec; + unsigned long base =3D rec->run->exit.ripas_base; + unsigned long top =3D rec->run->exit.ripas_top; + unsigned long ripas =3D rec->run->exit.ripas_value; + unsigned long top_ipa =3D base; + int ret; + + do { + kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_cache, + kvm_mmu_cache_min_pages(vcpu->arch.hw_mmu)); + write_lock(&kvm->mmu_lock); + ret =3D realm_set_ipa_state(vcpu, base, top, ripas, &top_ipa); + write_unlock(&kvm->mmu_lock); + + if (ret =3D=3D -ENOMEM) { + /* If no progress, then stop */ + if (top_ipa =3D=3D base) + break; + base =3D top_ipa; + continue; + } + + if (WARN_RATELIMIT(ret, + "Unable to satisfy RIPAS_CHANGE for %#lx - %#lx, ripas: %#lx\n", + base, top, ripas)) + break; + + base =3D top_ipa; + } while (base < top); + + /* + * If this function is called again before the REC_ENTER call then + * avoid calling realm_set_ipa_state() again by changing to the value + * of ripas_base for the part that has already been covered. The RMM + * ignores the contains of the rec_exit structure so this doesn't + * affect the RMM. + */ + rec->run->exit.ripas_base =3D base; +} + /* * kvm_rec_pre_enter - Complete operations before entering a REC * @@ -227,6 +681,9 @@ int kvm_rec_pre_enter(struct kvm_vcpu *vcpu) for (int i =3D 0; i < REC_RUN_GPRS; i++) rec->run->enter.gprs[i] =3D vcpu_get_reg(vcpu, i); break; + case RMI_EXIT_RIPAS_CHANGE: + kvm_complete_ripas_change(vcpu); + break; } =20 return 1; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id ACA1639B978; Wed, 15 Jul 2026 14:30:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125815; cv=none; b=eGtnV4uLnw8A+FbiQe75298Qb+PFUQ6MZ1HwaDIXl5faY8OUMHLq8WsUVYbTsYOPLD4yDNmDaNgop8nQ4bjjZS6loceVbdIa+OswvgpAe12EuOv9vKje/CONxXiifuj1Kgk27yy8WsaqRByeA/DGSBK6oKzAuWdCApXk4w9yI+0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125815; c=relaxed/simple; bh=GmiIXYY2KDIHLf9GKLUGeavkGI3LBc/BAUOdJieuNSk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FGuqJe4C2ec8NDga4ea6dMEd2IEoKiVXiM8uUqV/fXOO05/cnNuohzsUirgjCqqHp2DKKozSA8TCfi5pV6+2XQcOGGBcq6DV2lSKF5Av9fn61VWvLfx0pkrJ3eKcxEtuXUizuDA0a+P0W+rXfoQIFVeYLgztRm5e8++cunXv0xI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Ej9Nt0Au; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Ej9Nt0Au" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B94B1153B; Wed, 15 Jul 2026 07:30:08 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D9C253F7B4; Wed, 15 Jul 2026 07:30:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125813; bh=GmiIXYY2KDIHLf9GKLUGeavkGI3LBc/BAUOdJieuNSk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ej9Nt0Au/MgcpK06xGTjv5/RznheqR5PCD/iE70xUs9CPUboo6NoA63FtHm5cs7xx VvFh2MyC0b1q7E9/kJD9Ppbq78uG2Uhv4y+b04/GiMxUAcaASgK7oYQh8H1MDLUV76 IrNK7nmtP4apC8ruVA1E3Ox75in3Fk190f71maCo= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 16/37] KVM: arm64: CCA: Handle realm MMIO emulation Date: Wed, 15 Jul 2026 15:28:18 +0100 Message-ID: <20260715142841.80544-17-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" MMIO emulation for a realm cannot be done directly with the VM's registers as they are protected from the host. However, for emulatable data aborts, the RMM uses GPRS[0] to provide the read/written value. We can transfer this from/to the equivalent VCPU's register entry and then depend on the generic MMIO handling code in KVM. For a MMIO read, the value is placed in the shared RecExit structure during kvm_handle_mmio_return() rather than in the VCPU's register entry. Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- Changes since v7: * New comment for rec_exit_sync_dabt() explaining the call to vcpu_set_reg(). Changes since v5: * Inject SEA to the guest is an emulatable MMIO access triggers a data abort. * kvm_handle_mmio_return() - disable kvm_incr_pc() for a REC (as the PC isn't under the host's control) and move the REC_ENTER_EMULATED_MMIO flag setting to this location (as that tells the RMM to skip the instruction). --- arch/arm64/kvm/inject_fault.c | 4 +++- arch/arm64/kvm/mmio.c | 16 ++++++++++++---- arch/arm64/kvm/rmi-exit.c | 15 +++++++++++++++ 3 files changed, 30 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index 89982bd3345f..6492397b73d7 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -228,7 +228,9 @@ static void inject_abt32(struct kvm_vcpu *vcpu, bool is= _pabt, u32 addr) =20 static void __kvm_inject_sea(struct kvm_vcpu *vcpu, bool iabt, u64 addr) { - if (vcpu_el1_is_32bit(vcpu)) + if (unlikely(vcpu_is_rec(vcpu))) + vcpu->arch.rec.run->enter.flags |=3D REC_ENTER_FLAG_INJECT_SEA; + else if (vcpu_el1_is_32bit(vcpu)) inject_abt32(vcpu, iabt, addr); else inject_abt64(vcpu, iabt, addr); diff --git a/arch/arm64/kvm/mmio.c b/arch/arm64/kvm/mmio.c index e2285ed8c91d..a8c125205695 100644 --- a/arch/arm64/kvm/mmio.c +++ b/arch/arm64/kvm/mmio.c @@ -6,6 +6,7 @@ =20 #include #include +#include #include =20 #include "trace.h" @@ -138,14 +139,21 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu) trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr, &data); data =3D vcpu_data_host_to_guest(vcpu, data, len); - vcpu_set_reg(vcpu, kvm_vcpu_dabt_get_rd(vcpu), data); + + if (vcpu_is_rec(vcpu)) + vcpu->arch.rec.run->enter.gprs[0] =3D data; + else + vcpu_set_reg(vcpu, kvm_vcpu_dabt_get_rd(vcpu), data); } =20 /* * The MMIO instruction is emulated and should not be re-executed * in the guest. */ - kvm_incr_pc(vcpu); + if (vcpu_is_rec(vcpu)) + vcpu->arch.rec.run->enter.flags |=3D REC_ENTER_FLAG_EMULATED_MMIO; + else + kvm_incr_pc(vcpu); =20 return 1; } @@ -167,14 +175,14 @@ int io_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t f= ault_ipa) * No valid syndrome? Ask userspace for help if it has * volunteered to do so, and bail out otherwise. * - * In the protected VM case, there isn't much userspace can do + * In the protected/realm VM case, there isn't much userspace can do * though, so directly deliver an exception to the guest. */ if (!kvm_vcpu_dabt_isvalid(vcpu)) { trace_kvm_mmio_nisv(*vcpu_pc(vcpu), esr, kvm_vcpu_get_hfar(vcpu), fault_ipa); =20 - if (vcpu_is_protected(vcpu)) + if (vcpu_is_protected(vcpu) || vcpu_is_rec(vcpu)) return kvm_inject_sea_dabt(vcpu, kvm_vcpu_get_hfar(vcpu)); =20 if (test_bit(KVM_ARCH_FLAG_RETURN_NISV_IO_ABORT_TO_USER, diff --git a/arch/arm64/kvm/rmi-exit.c b/arch/arm64/kvm/rmi-exit.c index 973250563d7b..c668cbfa971a 100644 --- a/arch/arm64/kvm/rmi-exit.c +++ b/arch/arm64/kvm/rmi-exit.c @@ -23,6 +23,21 @@ static int rec_exit_reason_notimpl(struct kvm_vcpu *vcpu) =20 static int rec_exit_sync_dabt(struct kvm_vcpu *vcpu) { + struct realm_rec *rec =3D &vcpu->arch.rec; + + /* + * In the case of a write, copy over gprs[0] to the target GPR, + * preparing to handle MMIO write fault. The content to be written has + * been saved to gprs[0] by the RMM (even if another register was used + * by the guest). In the case of normal memory access this is redundant + * (the guest will replay the instruction), but the overhead is + * minimal. + */ + if (kvm_vcpu_dabt_iswrite(vcpu) && kvm_vcpu_dabt_isvalid(vcpu)) { + vcpu_set_reg(vcpu, kvm_vcpu_dabt_get_rd(vcpu), + rec->run->exit.gprs[0]); + } + return kvm_handle_guest_abort(vcpu); } =20 --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 43A7438AC75; Wed, 15 Jul 2026 14:30:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125820; cv=none; b=COWQ7Nk1pOWV4jY7/x/YFpX5Vk1IcWR5xspYQ+qtWV+DRiWAkwtivqKbKW2XYHIppjd+/JnQd91LhfzgQNDiTP/s83KvJw5ZKGHCzgWwwacXVTukqhY39vPCu47U2/vtZuY2UFRtChf41IWHrrgyYISMpvztN1uib0zwZPsZZ10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125820; c=relaxed/simple; bh=Cc6GoF1j4LXTGdBQGtewBJQChy0qePL6iG0TADmp2Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KSHkIekbSOp0ap9n7q0VuOcs5kl8qVrwlsvIXnobtpXn9BrHV8lQ3o3y9+ryeaU/YjhnIJyyE3UHALJEl5ub6THAdHASRKw3xSdg6DLKidkMTPg74IN1mTZ0U2xxzxU7nZcG+Wt9BRd7VlYSuDyvrWCzcP2xvS/emX4r0uWiDvs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=HYpUpVcw; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="HYpUpVcw" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 95E7F1576; Wed, 15 Jul 2026 07:30:13 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 66F7D3F7B4; Wed, 15 Jul 2026 07:30:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125817; bh=Cc6GoF1j4LXTGdBQGtewBJQChy0qePL6iG0TADmp2Dg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HYpUpVcwYSBXotiwDYU+p81k6SuEtc6oAMQvKW/4qdcThq/ZOtn4NDvzBRHfwmFjk 1365lwZPsGctd2c8DyuT7D5dUacvPJ2MGzSzMT9sTQmG+r9ZHotH6rRIfWCw8kBLpn W9kZ3ytf3CyuCgVPwy7A+i8E6eZTlndwhAH2zMbg= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 17/37] KVM: arm64: Expose support for private memory Date: Wed, 15 Jul 2026 15:28:19 +0100 Message-ID: <20260715142841.80544-18-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Select KVM_GENERIC_MEMORY_ATTRIBUTES and provide the necessary support functions. Signed-off-by: Steven Price Reviewed-by: Suzuki K Poulose --- Changes since v13: * Also update documentation to show that KVM_CAP_MEMORY_ATTRIBUTES is used on arm64. Changes since v12: * Only define kvm_arch_has_private_mem() when CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES is set to avoid build issues when KVM is disabled. Changes since v10: * KVM_GENERIC_PRIVATE_MEM replacd with KVM_GENERIC_MEMORY_ATTRIBUTES. Changes since v9: * Drop the #ifdef CONFIG_KVM_PRIVATE_MEM guard from the definition of kvm_arch_has_private_mem() Changes since v2: * Switch kvm_arch_has_private_mem() to a macro to avoid overhead of a function call. * Guard definitions of kvm_arch_{pre,post}_set_memory_attributes() with #ifdef CONFIG_KVM_GENERIC_MEMORY_ATTRIBUTES. * Early out in kvm_arch_post_set_memory_attributes() if the WARN_ON should trigger. --- arch/arm64/include/asm/kvm_host.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 9b46b39ed11e..993ead6e6449 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1509,6 +1509,8 @@ struct kvm *kvm_arch_alloc_vm(void); =20 #define vcpu_is_protected(vcpu) kvm_vm_is_protected((vcpu)->kvm) =20 +#define kvm_arch_has_private_mem(kvm) ((kvm)->arch.is_realm) + int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); =20 --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5EEE73A2E3F; Wed, 15 Jul 2026 14:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125825; cv=none; b=JuXMMs/J0a8wGF9yDslxIo2hDqiuUC55BZCDt47IiNFY9sBWdrd22+s7/ySY50vBrgvYJnCOqMS8q5qUIXB5M2i5gsz1h3roAMuqzhA6iorAxjtIpPZ96FAb7/LJDCY8hQ7r9kdVPd5c8lVAeTEfU96+TlIh0ZZOSeHSzXh1Ku8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125825; c=relaxed/simple; bh=G9XH5zZJ1GvOceYjyx4dHra6hejDLcr12uK8ZZtBmz8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rS55siKcDtkOc5LdRkwf0L4tHtRQYwtyeFvyFdASoQvyB9ZadChjjWHecuGnL/z32EXM8wlK0FEkrSml636rdhy5/KTOFfcSKMxkjEoFr+GPh2BzFUSIAqv2MbqWihXcwtCNB7dQNY7Mk3G219PFCN6MnGm+SKHHQWCwE2vA0fM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=KBg9JTgU; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="KBg9JTgU" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9C61F153B; Wed, 15 Jul 2026 07:30:18 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 525E53F7B4; Wed, 15 Jul 2026 07:30:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125822; bh=G9XH5zZJ1GvOceYjyx4dHra6hejDLcr12uK8ZZtBmz8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KBg9JTgU9fq3MMswbBA9g1KIVx8UAsBZXG3Da+XM514kButrHc9Mx6E2a4c5z5z+A rBNnaCvHaFaOr+uvlsbY6CjBuBWIN1GED/CC39xzJriQzrvyc/NkXSJObSyYxu/Pw5 ntFryhi6rw/H3wmmWIN9fgU20dqVxINIAfo9u6dc= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 18/37] KVM: arm64: CCA: Create the realm descriptor Date: Wed, 15 Jul 2026 15:28:20 +0100 Message-ID: <20260715142841.80544-19-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Creating a realm involves first creating a realm descriptor (RD). This involves passing the configuration information to the RMM. Do this as part of realm_ensure_created() so that the realm is created when it is first needed. The call to realm_ensure_created() will be added in a later patch. Signed-off-by: Steven Price --- Changes since v14: * Explicitly set hash_algo =3D RMI_HASH_SHA_256 (which is the default). * Support SRO flow during realm creation. Changes since v13: * The RMM no longer uses AUX granules, so no need to ask it how many it needs. * Adapted to other changes. Changes since v12: * Since RMM page size is now equal to the host's page size various calculations are simplified. * Switch to using range based APIs to delegate/undelegate. * VMID handling is now handled entirely by the RMM. --- arch/arm64/kvm/rmi.c | 91 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 1ef676eed172..94776a9262c9 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -449,6 +449,79 @@ static void realm_unmap_shared_range(struct kvm *kvm, start, end); } =20 +static int realm_create_rd(struct kvm *kvm) +{ + struct realm *realm =3D &kvm->arch.realm; + struct realm_params *params =3D realm->params; + void *rd =3D NULL; + phys_addr_t rd_phys, params_phys, top_delegated; + size_t pgd_size =3D kvm_pgtable_stage2_pgd_size(kvm->arch.mmu.vtcr); + int r; + + realm->ia_bits =3D VTCR_EL2_IPA(kvm->arch.mmu.vtcr); + + if (WARN_ON(realm->rd || !realm->params)) + return -EEXIST; + + rd =3D (void *)__get_free_page(GFP_KERNEL_ACCOUNT); + if (!rd) + return -ENOMEM; + + rd_phys =3D virt_to_phys(rd); + if (rmi_delegate_page(rd_phys)) { + r =3D -ENXIO; + goto free_rd; + } + + if (rmi_delegate_range(kvm->arch.mmu.pgd_phys, pgd_size, + &top_delegated)) { + r =3D -ENXIO; + goto out_undelegate_tables; + } + + params->s2sz =3D VTCR_EL2_IPA(kvm->arch.mmu.vtcr); + params->rtt_level_start =3D get_start_level(realm); + params->rtt_num_start =3D pgd_size / PAGE_SIZE; + params->rtt_base =3D kvm->arch.mmu.pgd_phys; + params->hash_algo =3D RMI_HASH_SHA_256; + + if (kvm->arch.arm_pmu) { + params->pmu_num_ctrs =3D kvm->arch.nr_pmu_counters; + params->flags0 |=3D RMI_REALM_PARAM_FLAG_PMU; + } + + if (kvm_lpa2_is_enabled()) + params->flags0 |=3D RMI_REALM_PARAM_FLAG_LPA2; + + params_phys =3D virt_to_phys(params); + + if (rmi_realm_create(rd_phys, params_phys, realm->sro)) { + r =3D -ENXIO; + goto out_undelegate_tables; + } + + realm->rd =3D rd; + kvm_set_realm_state(kvm, REALM_STATE_NEW); + /* The realm is up, free the parameters. */ + free_page((unsigned long)realm->params); + realm->params =3D NULL; + + return 0; + +out_undelegate_tables: + if (WARN_ON(rmi_undelegate_range(kvm->arch.mmu.pgd_phys, top_delegated - = kvm->arch.mmu.pgd_phys))) { + /* Leak the pages if they cannot be returned */ + kvm->arch.mmu.pgt =3D NULL; + } + if (WARN_ON(rmi_undelegate_page(rd_phys))) { + /* Leak the page if it isn't returned */ + return r; + } +free_rd: + free_page((unsigned long)rd); + return r; +} + static void realm_unmap_private_range(struct kvm *kvm, unsigned long start, unsigned long end, @@ -614,6 +687,24 @@ static int realm_set_ipa_state(struct kvm_vcpu *vcpu, return ret; } =20 +static int __maybe_unused realm_ensure_created(struct kvm *kvm) +{ + lockdep_assert_held(&kvm->arch.config_lock); + + switch (kvm_realm_state(kvm)) { + case REALM_STATE_NONE: + break; + case REALM_STATE_NEW: + return 0; + case REALM_STATE_DEAD: + return -ENXIO; + default: + return -EBUSY; + } + + return realm_create_rd(kvm); +} + static void kvm_complete_ripas_change(struct kvm_vcpu *vcpu) { struct kvm *kvm =3D vcpu->kvm; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AE7F140EBA8; Wed, 15 Jul 2026 14:30:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125830; cv=none; b=GVZi355r1ZH5CjpU8G80sf3m4pesHx1vtHYEUIDi0F7lkrl9CFERjz7gLSrBnGtXHja3k1Xzn6ku577LCx36KlxKUQy5PCEoHvZv5iAVVVTStxw5LVEqUqPiukbJsU+8K684EZgs9S4B7XQL4kGLFfpYknhafqSKtSrOF2gSRV4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125830; c=relaxed/simple; bh=LrO5HmU/ibLzJRg9BZGCtuLiyBzz5qn2yu+Rs6vdwr0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sS4NQ1NJST57WKWw9jfU5ZZPauhhvqzFynYWa8iQulE6Abwvo65XMoLJ7h43icNsFMCc7+50N7ChcTZDBTRCvQk8fMy+kjZU9t35or/kWqBl3zHtSzlFGnpt7ZwkL9oSnr0+T+dIX1JfOlhGNbO5YCceJUMSNshv0VYMghgFakU= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NgKFafBpcNrozMkY3ZI3/MZOZv9KSw3iCP9c41LG+bwRNeaAbG51H2DB03FRw2JGC xIuEQSWuyIM/P3d9N0EYNrn7jHu6Zjo5aNYzXvK5W3vFaprTARBttRJ1ofUvPV4rtm 7ffTpuO8lsRacLCbKDyyrE7IqbLKtmrXu82CFIgw= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 19/37] KVM: arm64: CCA: Activate realms on first vCPU run Date: Wed, 15 Jul 2026 15:28:21 +0100 Message-ID: <20260715142841.80544-20-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use kvm_arch_vcpu_run_pid_change() to check if this is the first time the realm guest has run. If this is the first run then activate the realm. Signed-off-by: Steven Price --- Changes since v12: * Fix commit message * Change realm_state checks to be >=3D REALM_STATE_ACTIVE to avoid a dead guest being revived by kvm_activate_realm(). --- arch/arm64/include/asm/kvm_rmi.h | 1 + arch/arm64/kvm/arm.c | 6 +++++ arch/arm64/kvm/rmi.c | 45 ++++++++++++++++++++++++++++++-- 3 files changed, 50 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 5461c49bea4d..5cb99c187202 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -96,6 +96,7 @@ void kvm_init_rmi(void); u32 kvm_rmm_ipa_limit(void); =20 int kvm_init_realm(struct kvm *kvm); +int kvm_activate_realm(struct kvm *kvm); void kvm_destroy_realm(struct kvm *kvm); int kvm_realm_teardown_stage2(struct kvm *kvm); void kvm_destroy_rec(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 534d33b7c67a..df33322b8fea 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1034,6 +1034,12 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vc= pu) return ret; } =20 + if (kvm_is_realm(vcpu->kvm)) { + ret =3D kvm_activate_realm(kvm); + if (ret) + return ret; + } + mutex_lock(&kvm->arch.config_lock); set_bit(KVM_ARCH_FLAG_HAS_RAN_ONCE, &kvm->arch.flags); mutex_unlock(&kvm->arch.config_lock); diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 94776a9262c9..53b5b18f2275 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -687,7 +687,7 @@ static int realm_set_ipa_state(struct kvm_vcpu *vcpu, return ret; } =20 -static int __maybe_unused realm_ensure_created(struct kvm *kvm) +static int realm_ensure_created(struct kvm *kvm) { lockdep_assert_held(&kvm->arch.config_lock); =20 @@ -793,7 +793,7 @@ int noinstr kvm_rec_enter(struct kvm_vcpu *vcpu) return ret; } =20 -static int __maybe_unused kvm_create_rec(struct kvm_vcpu *vcpu) +static int kvm_create_rec(struct kvm_vcpu *vcpu) { struct user_pt_regs *vcpu_regs =3D vcpu_gp_regs(vcpu); unsigned long mpidr =3D kvm_vcpu_get_mpidr_aff(vcpu); @@ -893,6 +893,47 @@ void kvm_destroy_rec(struct kvm_vcpu *vcpu) rec->rec_page =3D NULL; } =20 +int kvm_activate_realm(struct kvm *kvm) +{ + struct realm *realm =3D &kvm->arch.realm; + struct kvm_vcpu *vcpu; + unsigned long i; + int ret; + + if (kvm_realm_state(kvm) >=3D REALM_STATE_ACTIVE) + return 0; + + if (!irqchip_in_kernel(kvm)) { + /* Userspace irqchip not yet supported with realms */ + return -EOPNOTSUPP; + } + + guard(mutex)(&kvm->arch.config_lock); + /* Check again with the lock held */ + if (kvm_realm_state(kvm) >=3D REALM_STATE_ACTIVE) + return 0; + + ret =3D realm_ensure_created(kvm); + if (ret) + return ret; + + /* Mark state as dead in case we fail */ + kvm_set_realm_state(kvm, REALM_STATE_DEAD); + + kvm_for_each_vcpu(i, vcpu, kvm) { + ret =3D kvm_create_rec(vcpu); + if (ret) + return ret; + } + + ret =3D rmi_realm_activate(virt_to_phys(realm->rd)); + if (ret) + return -ENXIO; + + kvm_set_realm_state(kvm, REALM_STATE_ACTIVE); + return 0; +} + void kvm_destroy_realm(struct kvm *kvm) { struct realm *realm =3D &kvm->arch.realm; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3A718437879; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="HiPsrwLh" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5F05C1576; Wed, 15 Jul 2026 07:30:27 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6E2E53F7B4; Wed, 15 Jul 2026 07:30:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125831; bh=xB20vi2nNALS9GBzmutQDk9WbDugbz1wVrS9SO+qgWw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HiPsrwLhRBVIxGq/u5Mm62zS4lNbScLifEZPvmFVJCAmHxi6g35GAiV46G4aCXQ7S bCYrCSUVXcK3lLT2xgAoSz3RGUlIpQ4YpsfWZKFou4FSR9fZ9ClMcdJeMyBpEsp4Tu 7hw1FdoZT8tW+gcR/FG4q01DgIzRY83Ynui99I5E= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 20/37] KVM: arm64: CCA: Allow populating initial contents Date: Wed, 15 Jul 2026 15:28:22 +0100 Message-ID: <20260715142841.80544-21-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The VMM needs to populate the realm with some data before starting (e.g. a kernel and initrd). This is measured by the RMM and used as part of the attestation later on. Signed-off-by: Steven Price --- Changes since v14: * Holding of locks slots_lock and config_lock have been moved up the callstack with lockdesp assertions placed in the lower functions. * Add overflow check into kvm_arm_rmi_populate(). Changes since v13: * Rename realm_create_protected_data_page() to realm_data_map_init(). Changes since v12: * The ioctl now updates the structure with the amount populated rather than returning this through the ioctl return code. * Use the new RMM v2.0 range based RMI calls. * Adapt to upstream changes in kvm_gmem_populate(). Changes since v11: * The multiplex CAP is gone and there's a new ioctl which makes use of the generic kvm_gmem_populate() functionality. Changes since v7: * Improve the error codes. * Other minor changes from review. Changes since v6: * Handle host potentially having a larger page size than the RMM granule. * Drop historic "par" (protected address range) from populate_par_region() - it doesn't exist within the current architecture. * Add a cond_resched() call in kvm_populate_realm(). Changes since v5: * Refactor to use PFNs rather than tracking struct page in realm_create_protected_data_page(). * Pull changes from a later patch (in the v5 series) for accessing pages from a guest memfd. * Do the populate in chunks to avoid holding locks for too long and triggering RCU stall warnings. --- arch/arm64/include/asm/kvm_rmi.h | 4 ++ arch/arm64/kvm/Kconfig | 1 + arch/arm64/kvm/arm.c | 13 ++++ arch/arm64/kvm/rmi.c | 119 +++++++++++++++++++++++++++++++ 4 files changed, 137 insertions(+) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 5cb99c187202..fd0c57594a22 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -105,6 +105,10 @@ int kvm_rec_enter(struct kvm_vcpu *vcpu); int kvm_rec_pre_enter(struct kvm_vcpu *vcpu); int handle_rec_exit(struct kvm_vcpu *vcpu, int rec_run_status); =20 +struct kvm_arm_rmi_populate; + +int kvm_arm_rmi_populate(struct kvm *kvm, + struct kvm_arm_rmi_populate *arg); void kvm_realm_unmap_range(struct kvm *kvm, unsigned long ipa, unsigned long size, diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index 189e8ad78b22..83b95e836b4d 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -37,6 +37,7 @@ menuconfig KVM select SCHED_INFO select GUEST_PERF_EVENTS if PERF_EVENTS select KVM_GUEST_MEMFD + select HAVE_KVM_ARCH_GMEM_POPULATE select ARM_RMM help Support hosting virtualized guest machines. diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index df33322b8fea..1558bb12b1b1 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -2153,6 +2153,19 @@ int kvm_arch_vm_ioctl(struct file *filp, unsigned in= t ioctl, unsigned long arg) return -EFAULT; return kvm_vm_ioctl_get_reg_writable_masks(kvm, &range); } + case KVM_ARM_RMI_POPULATE: { + struct kvm_arm_rmi_populate req; + int ret; + + if (!kvm_is_realm(kvm)) + return -ENXIO; + if (copy_from_user(&req, argp, sizeof(req))) + return -EFAULT; + ret =3D kvm_arm_rmi_populate(kvm, &req); + if (copy_to_user(argp, &req, sizeof(req))) + return -EFAULT; + return ret; + } default: return -EINVAL; } diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 53b5b18f2275..e2b4c64e982d 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -590,6 +590,76 @@ void kvm_realm_unmap_range(struct kvm *kvm, unsigned l= ong start, realm_unmap_private_range(kvm, start, end, may_block); } =20 +static int realm_data_map_init(struct kvm *kvm, unsigned long ipa, + kvm_pfn_t dst_pfn, kvm_pfn_t src_pfn, + unsigned long flags) +{ + struct realm *realm =3D &kvm->arch.realm; + phys_addr_t rd =3D virt_to_phys(realm->rd); + phys_addr_t dst_phys, src_phys; + int ret; + + lockdep_assert_held(&kvm->slots_lock); + lockdep_assert_held(&kvm->arch.config_lock); + + dst_phys =3D __pfn_to_phys(dst_pfn); + src_phys =3D __pfn_to_phys(src_pfn); + + if (rmi_delegate_page(dst_phys)) + return -ENXIO; + +retry: + ret =3D rmi_rtt_data_map_init(rd, dst_phys, ipa, src_phys, flags); + if (RMI_RETURN_STATUS(ret) =3D=3D RMI_ERROR_RTT) { + /* Create missing RTTs and retry */ + int level =3D RMI_RETURN_INDEX(ret); + + KVM_BUG_ON(level >=3D KVM_PGTABLE_LAST_LEVEL, kvm); + + ret =3D realm_create_rtt_levels(realm, ipa, level, + level + 1, NULL); + if (!ret) + goto retry; + } + + if (ret && WARN_ON(rmi_undelegate_page(dst_phys))) { + /* Leak the page if the undelegate fails */ + get_page(pfn_to_page(dst_pfn)); + } + + return ret <=3D 0 ? ret : -ENXIO; +} + +static int populate_region_cb(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, + struct page *src_page, void *opaque) +{ + unsigned long data_flags =3D *(unsigned long *)opaque; + phys_addr_t ipa =3D gfn_to_gpa(gfn); + + return realm_data_map_init(kvm, ipa, pfn, page_to_pfn(src_page), + data_flags); +} + +static long populate_region(struct kvm *kvm, + gfn_t base_gfn, + unsigned long pages, + u64 uaddr, + unsigned long data_flags) +{ + long ret =3D 0; + + lockdep_assert_held(&kvm->slots_lock); + lockdep_assert_held(&kvm->arch.config_lock); + + if (!uaddr) + return -EINVAL; + + ret =3D kvm_gmem_populate(kvm, base_gfn, u64_to_user_ptr(uaddr), pages, + false, populate_region_cb, &data_flags); + + return ret; +} + enum ripas_action { RIPAS_INIT, RIPAS_SET, @@ -705,6 +775,55 @@ static int realm_ensure_created(struct kvm *kvm) return realm_create_rd(kvm); } =20 +int kvm_arm_rmi_populate(struct kvm *kvm, + struct kvm_arm_rmi_populate *args) +{ + unsigned long data_flags =3D 0; + unsigned long ipa_start =3D args->base; + unsigned long ipa_end =3D ipa_start + args->size; + long pages_populated; + int ret; + + if (args->reserved || + (args->flags & ~KVM_ARM_RMI_POPULATE_FLAGS_MEASURE) || + args->base + args->size < args->base || + !IS_ALIGNED(ipa_start, PAGE_SIZE) || + !IS_ALIGNED(ipa_end, PAGE_SIZE) || + !IS_ALIGNED(args->source_uaddr, PAGE_SIZE)) + return -EINVAL; + + if (args->flags & KVM_ARM_RMI_POPULATE_FLAGS_MEASURE) + data_flags |=3D RMI_MEASURE_CONTENT; + + mutex_lock(&kvm->slots_lock); + mutex_lock(&kvm->arch.config_lock); + + ret =3D realm_ensure_created(kvm); + if (ret) + goto out_unlock; + + if (args->size =3D=3D 0) + goto out_unlock; + + pages_populated =3D populate_region(kvm, gpa_to_gfn(ipa_start), + args->size >> PAGE_SHIFT, + args->source_uaddr, data_flags); + + if (pages_populated < 0) { + ret =3D pages_populated; + goto out_unlock; + } + + args->size -=3D pages_populated << PAGE_SHIFT; + args->source_uaddr +=3D pages_populated << PAGE_SHIFT; + args->base +=3D pages_populated << PAGE_SHIFT; + +out_unlock: + mutex_unlock(&kvm->arch.config_lock); + mutex_unlock(&kvm->slots_lock); + return ret; +} + static void kvm_complete_ripas_change(struct kvm_vcpu *vcpu) { struct kvm *kvm =3D vcpu->kvm; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9624738D3E3; Wed, 15 Jul 2026 14:30:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125839; cv=none; b=GUbI/8cf9xEJ3ock62QHS3g6sHI6QWfweTgopFUnv8qSpOyXUpTUGo16Th8xaYqdKnEMLwGZmengfe0Z/O2YohbVwfnxUDN8PDd/8EGS3wTBYlaBhkFRo4UXpXU/c6s/i0RCypLAc5kbchbyO+fObwi/lSxfSN52mKmOM1adVl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125839; c=relaxed/simple; bh=LVpTnAu3uJ7T4L4lsdBjk/5iVJcIHD+HZJ2BNsxHVGo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kp5LjnFCh42NhS5ZfQ5o0mOp9mq3kBF9ZrX0GZgpU2l2M9apP8cQPRapDBVfJQ21mTvcnRMZ0BMkm2Tbr5zVYtI1V8pZpcF/SKFVCoRBZND/8rxoQSFVKP2J1XPcJNXL2D0jwLNHo/Iesh4KQb3abMAvVXa727zL56xYOyKffMM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=L51nJ+Pe; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="L51nJ+Pe" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E6E29153B; Wed, 15 Jul 2026 07:30:32 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EAC633F7B4; Wed, 15 Jul 2026 07:30:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125837; bh=LVpTnAu3uJ7T4L4lsdBjk/5iVJcIHD+HZJ2BNsxHVGo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=L51nJ+PeMf42u5bZ/OygcSXpLA79Ko5eeRp/7BAjXRHVtmH85QuqSHNoAc1yovfC5 oV+1iyurEkn428aJ6w3R3sQVLujFTC3g7bGfMGirRShwxLVNjjRymVliH84EtN476w q13Y3mniOWGS+TQ2gC0f5nhPbzgcNZxnK63FIBHc= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 21/37] KVM: arm64: CCA: Set RIPAS of initial memslots Date: Wed, 15 Jul 2026 15:28:23 +0100 Message-ID: <20260715142841.80544-22-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The memory which the realm guest accesses must be set to RIPAS_RAM. Iterate over the memslots and set all gmem memslots to RIPAS_RAM. Signed-off-by: Steven Price --- New patch for v12. --- arch/arm64/kvm/rmi.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index e2b4c64e982d..1e6c04145f6c 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -757,6 +757,14 @@ static int realm_set_ipa_state(struct kvm_vcpu *vcpu, return ret; } =20 +static int realm_init_ipa_state(struct kvm *kvm, + unsigned long gfn, + unsigned long pages) +{ + return ripas_change(kvm, NULL, gfn_to_gpa(gfn), gfn_to_gpa(gfn + pages), + RIPAS_INIT, NULL); +} + static int realm_ensure_created(struct kvm *kvm) { lockdep_assert_held(&kvm->arch.config_lock); @@ -775,6 +783,32 @@ static int realm_ensure_created(struct kvm *kvm) return realm_create_rd(kvm); } =20 +static int set_ripas_of_protected_regions(struct kvm *kvm) +{ + struct kvm_memslots *slots; + struct kvm_memory_slot *memslot; + int idx, bkt; + int ret =3D 0; + + lockdep_assert_held(&kvm->arch.config_lock); + + idx =3D srcu_read_lock(&kvm->srcu); + + slots =3D kvm_memslots(kvm); + kvm_for_each_memslot(memslot, bkt, slots) { + if (!kvm_slot_has_gmem(memslot)) + continue; + + ret =3D realm_init_ipa_state(kvm, memslot->base_gfn, + memslot->npages); + if (ret) + break; + } + srcu_read_unlock(&kvm->srcu, idx); + + return ret; +} + int kvm_arm_rmi_populate(struct kvm *kvm, struct kvm_arm_rmi_populate *args) { @@ -1045,6 +1079,10 @@ int kvm_activate_realm(struct kvm *kvm) return ret; } =20 + ret =3D set_ripas_of_protected_regions(kvm); + if (ret) + return ret; + ret =3D rmi_realm_activate(virt_to_phys(realm->rd)); if (ret) return -ENXIO; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9B155478E5D; Wed, 15 Jul 2026 14:30:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125844; cv=none; b=JWjzs6fgxsdvPboWe9u6VOqZx8UbzbEJUXXmVZKKpzuUF7h7PEY5xYKbTEb56uKxlLmPQmkmO4N8xHBE9a7crhmFM7CjPheDOggiNhbfkmamAydTOhxU5zjq9NJr4KLfVxk3NwUXn2kVMGVh4b9YFmYJbGnJoigDq7x+qUfnDMY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125844; c=relaxed/simple; bh=8BRGy94lwEE+hFzwZjAZ/i4l15c1vxqkmuQjLmKxGpc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SZmfO0O+8cpW3aX4uDUj8sBVmFrS+6KexPGn+7cjRne/ZAWhe2aW+pdfRZ083efa4qgqaz9HZ0FmDeb4YVEtuZ2czdZYdLtX/6YvylPK+rvZZ2GQ3Ct136fFfba/meCqBp+tQw4WwK1xgKZ9eIwyWqbMh6CHf1z16TxNjEjUDb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=GB+tlIY/; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="GB+tlIY/" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E80BB1576; Wed, 15 Jul 2026 07:30:37 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8FE793F7B4; Wed, 15 Jul 2026 07:30:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125842; bh=8BRGy94lwEE+hFzwZjAZ/i4l15c1vxqkmuQjLmKxGpc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GB+tlIY/4dNRSxWkFsgED9iZeo0Bf2V66wEUWQyzJWBi4x1Y3k8RNRCXXWafFGHol K05HI9RpSXVjn+3GGvpkrZ+DA+p079XqVGHpj1DY20ucTL0fuHAykRV8jayEKv5MeW HIGJFowZBTT4g2cTehGnG1N3qTEaFQvMGxiKALCA= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 22/37] KVM: arm64: CCA: Support runtime faulting of memory Date: Wed, 15 Jul 2026 15:28:24 +0100 Message-ID: <20260715142841.80544-23-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" At runtime if the realm guest accesses memory which hasn't yet been mapped then KVM needs to either populate the region or fault the guest. For memory in the lower (protected) region of IPA a fresh page is provided to the RMM which will zero the contents. For memory in the upper (shared) region of IPA, the memory from the memslot is mapped into the realm VM non secure. Signed-off-by: Steven Price --- Changes since v13: * Numerous changes due to rebasing. * Fix addr_range_desc() to encode the correct block size. Changes since v12: * Switch to RMM v2.0 range based APIs. Changes since v11: * Adapt to upstream changes. Changes since v10: * RME->RMI renaming. * Adapt to upstream gmem changes. Changes since v9: * Fix call to kvm_stage2_unmap_range() in kvm_free_stage2_pgd() to set may_block to avoid stall warnings. * Minor coding style fixes. Changes since v8: * Propagate the may_block flag. * Minor comments and coding style changes. Changes since v7: * Remove redundant WARN_ONs for realm_create_rtt_levels() - it will internally WARN when necessary. Changes since v6: * Handle PAGE_SIZE being larger than RMM granule size. * Some minor renaming following review comments. Changes since v5: * Reduce use of struct page in preparation for supporting the RMM having a different page size to the host. * Handle a race when delegating a page where another CPU has faulted on a the same page (and already delegated the physical page) but not yet mapped it. In this case simply return to the guest to either use the mapping from the other CPU (or refault if the race is lost). * The changes to populate_par_region() are moved into the previous patch where they belong. Changes since v4: * Code cleanup following review feedback. * Drop the PTE_SHARED bit when creating unprotected page table entries. This is now set by the RMM and the host has no control of it and the spec requires the bit to be set to zero. Changes since v2: * Avoid leaking memory if failing to map it in the realm. * Correctly mask RTT based on LPA2 flag (see rtt_get_phys()). * Adapt to changes in previous patches. --- arch/arm64/include/asm/kvm_emulate.h | 8 + arch/arm64/include/asm/kvm_rmi.h | 5 + arch/arm64/kvm/mmu.c | 97 ++++++++---- arch/arm64/kvm/rmi.c | 214 +++++++++++++++++++++++++++ 4 files changed, 298 insertions(+), 26 deletions(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index 2e69fe494716..8b6f9d26b5d8 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -712,6 +712,14 @@ static inline bool kvm_realm_is_created(struct kvm *kv= m) return kvm_is_realm(kvm) && kvm_realm_state(kvm) !=3D REALM_STATE_NONE; } =20 +static inline gpa_t kvm_gpa_from_fault(struct kvm *kvm, phys_addr_t ipa) +{ + if (!kvm_is_realm(kvm)) + return ipa; + + return ipa & ~BIT(kvm->arch.realm.ia_bits - 1); +} + static inline bool vcpu_is_rec(const struct kvm_vcpu *vcpu) { return kvm_is_realm(vcpu->kvm); diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index fd0c57594a22..718c7128a3c3 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -6,6 +6,7 @@ #ifndef __ASM_KVM_RMI_H #define __ASM_KVM_RMI_H =20 +#include #include =20 /** @@ -114,6 +115,10 @@ void kvm_realm_unmap_range(struct kvm *kvm, unsigned long size, bool unmap_private, bool may_block); +int realm_map_ipa(struct kvm *kvm, phys_addr_t ipa, + kvm_pfn_t pfn, unsigned long map_size, + enum kvm_pgtable_prot prot, + struct kvm_mmu_memory_cache *memcache); =20 static inline bool kvm_realm_is_private_address(struct realm *realm, unsigned long addr) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index dcc2ab08d0e4..79119cb136b0 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -334,8 +334,15 @@ static void __unmap_stage2_range(struct kvm_s2_mmu *mm= u, phys_addr_t start, u64 =20 lockdep_assert_held_write(&kvm->mmu_lock); WARN_ON(size & ~PAGE_MASK); - WARN_ON(stage2_apply_range(mmu, start, end, KVM_PGT_FN(kvm_pgtable_stage2= _unmap), - may_block)); + + if (kvm_is_realm(kvm)) { + kvm_realm_unmap_range(kvm, start, size, !only_shared, + may_block); + } else { + WARN_ON(stage2_apply_range(mmu, start, end, + KVM_PGT_FN(kvm_pgtable_stage2_unmap), + may_block)); + } } =20 void kvm_stage2_unmap_range(struct kvm_s2_mmu *mmu, phys_addr_t start, @@ -358,7 +365,10 @@ static void stage2_flush_memslot(struct kvm *kvm, phys_addr_t addr =3D memslot->base_gfn << PAGE_SHIFT; phys_addr_t end =3D addr + PAGE_SIZE * memslot->npages; =20 - kvm_stage2_flush_range(&kvm->arch.mmu, addr, end); + if (kvm_is_realm(kvm)) + kvm_realm_unmap_range(kvm, addr, end - addr, false, true); + else + kvm_stage2_flush_range(&kvm->arch.mmu, addr, end); } =20 /** @@ -1137,6 +1147,10 @@ void stage2_unmap_vm(struct kvm *kvm) struct kvm_memory_slot *memslot; int idx, bkt; =20 + /* For realms this is handled by the RMM so nothing to do here */ + if (kvm_is_realm(kvm)) + return; + idx =3D srcu_read_lock(&kvm->srcu); mmap_read_lock(current->mm); write_lock(&kvm->mmu_lock); @@ -1641,18 +1655,20 @@ static int gmem_abort(const struct kvm_s2_fault_des= c *s2fd) bool perm_fault =3D kvm_vcpu_trap_is_permission_fault(s2fd->vcpu); enum kvm_pgtable_walk_flags flags =3D KVM_PGTABLE_WALK_SHARED; enum kvm_pgtable_prot prot =3D KVM_PGTABLE_PROT_R; - struct kvm_pgtable *pgt =3D s2fd->vcpu->arch.hw_mmu->pgt; + struct kvm_vcpu *vcpu =3D s2fd->vcpu; + struct kvm_pgtable *pgt =3D vcpu->arch.hw_mmu->pgt; + gpa_t gpa =3D kvm_gpa_from_fault(vcpu->kvm, s2fd->fault_ipa); unsigned long mmu_seq; struct page *page; - struct kvm *kvm =3D s2fd->vcpu->kvm; + struct kvm *kvm =3D vcpu->kvm; void *memcache =3D NULL; kvm_pfn_t pfn; gfn_t gfn; int ret; =20 if (!perm_fault) { - memcache =3D get_mmu_memcache(s2fd->vcpu); - ret =3D topup_mmu_memcache(s2fd->vcpu, memcache); + memcache =3D get_mmu_memcache(vcpu); + ret =3D topup_mmu_memcache(vcpu, memcache); if (ret) return ret; } @@ -1660,10 +1676,10 @@ static int gmem_abort(const struct kvm_s2_fault_des= c *s2fd) if (s2fd->nested) gfn =3D kvm_s2_trans_output(s2fd->nested) >> PAGE_SHIFT; else - gfn =3D s2fd->fault_ipa >> PAGE_SHIFT; + gfn =3D gpa >> PAGE_SHIFT; =20 - write_fault =3D kvm_is_write_fault(s2fd->vcpu); - exec_fault =3D kvm_vcpu_trap_is_exec_fault(s2fd->vcpu); + write_fault =3D kvm_is_write_fault(vcpu); + exec_fault =3D kvm_vcpu_trap_is_exec_fault(vcpu); =20 VM_WARN_ON_ONCE(write_fault && exec_fault); =20 @@ -1673,7 +1689,7 @@ static int gmem_abort(const struct kvm_s2_fault_desc = *s2fd) =20 ret =3D kvm_gmem_get_pfn(kvm, s2fd->memslot, gfn, &pfn, &page, NULL); if (ret) { - kvm_prepare_memory_fault_exit(s2fd->vcpu, s2fd->fault_ipa, PAGE_SIZE, + kvm_prepare_memory_fault_exit(vcpu, gpa, PAGE_SIZE, write_fault, exec_fault, false); return ret; } @@ -1693,7 +1709,14 @@ static int gmem_abort(const struct kvm_s2_fault_desc= *s2fd) kvm_fault_lock(kvm); if (mmu_invalidate_retry(kvm, mmu_seq)) { ret =3D -EAGAIN; - goto out_unlock; + goto out_release_page; + } + + if (kvm_is_realm(kvm)) { + prot &=3D ~KVM_PGTABLE_PROT_X; + ret =3D realm_map_ipa(kvm, s2fd->fault_ipa, pfn, + PAGE_SIZE, prot, memcache); + goto out_release_page; } =20 if (perm_fault) { @@ -1710,7 +1733,7 @@ static int gmem_abort(const struct kvm_s2_fault_desc = *s2fd) memcache, flags); } =20 -out_unlock: +out_release_page: kvm_release_faultin_page(kvm, page, !!ret, prot & KVM_PGTABLE_PROT_W); kvm_fault_unlock(kvm); =20 @@ -1896,7 +1919,7 @@ static int kvm_s2_fault_get_vma_info(const struct kvm= _s2_fault_desc *s2fd, * mapping size to ensure we find the right PFN and lay down the * mapping in the right place. */ - s2vi->gfn =3D ALIGN_DOWN(s2fd->fault_ipa, s2vi->vma_pagesize) >> PAGE_SHI= FT; + s2vi->gfn =3D kvm_gpa_from_fault(kvm, ALIGN_DOWN(s2fd->fault_ipa, s2vi->v= ma_pagesize)) >> PAGE_SHIFT; =20 s2vi->mte_allowed =3D kvm_vma_mte_allowed(vma); =20 @@ -2092,12 +2115,15 @@ static int kvm_s2_fault_map(const struct kvm_s2_fau= lt_desc *s2fd, if (!perm_fault_granule && !s2vi->map_non_cacheable && kvm_has_mte(kvm)) sanitise_mte_tags(kvm, pfn, mapping_size); =20 - /* - * Under the premise of getting a FSC_PERM fault, we just need to relax - * permissions only if mapping_size equals perm_fault_granule. Otherwise, - * kvm_pgtable_stage2_map() should be called to change block size. - */ - if (mapping_size =3D=3D perm_fault_granule) { + if (kvm_is_realm(kvm)) { + ret =3D realm_map_ipa(kvm, s2fd->fault_ipa, pfn, mapping_size, + prot, memcache); + } else if (mapping_size =3D=3D perm_fault_granule) { + /* + * Under the premise of getting a FSC_PERM fault, we just need to relax + * permissions only if mapping_size equals perm_fault_granule. Otherwise, + * kvm_pgtable_stage2_map() should be called to change block size. + */ /* * Drop the SW bits in favour of those stored in the * PTE, which will be preserved. @@ -2263,6 +2289,13 @@ int kvm_handle_guest_sea(struct kvm_vcpu *vcpu) return 0; } =20 +static bool shared_ipa_fault(struct kvm *kvm, phys_addr_t fault_ipa) +{ + gpa_t gpa =3D kvm_gpa_from_fault(kvm, fault_ipa); + + return (gpa !=3D fault_ipa); +} + /** * kvm_handle_guest_abort - handles all 2nd stage aborts * @vcpu: the VCPU pointer @@ -2373,8 +2406,9 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) nested =3D &nested_trans; } =20 - gfn =3D ipa >> PAGE_SHIFT; + gfn =3D kvm_gpa_from_fault(vcpu->kvm, ipa) >> PAGE_SHIFT; memslot =3D gfn_to_memslot(vcpu->kvm, gfn); + hva =3D gfn_to_hva_memslot_prot(memslot, gfn, &writable); write_fault =3D kvm_is_write_fault(vcpu); if (kvm_is_error_hva(hva) || (write_fault && !writable)) { @@ -2417,7 +2451,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) * of the page size. */ ipa |=3D FAR_TO_FIPA_OFFSET(kvm_vcpu_get_hfar(vcpu)); - ret =3D io_mem_abort(vcpu, ipa); + ret =3D io_mem_abort(vcpu, kvm_gpa_from_fault(vcpu->kvm, ipa)); goto out_unlock; } =20 @@ -2445,7 +2479,9 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu) !write_fault && !kvm_vcpu_trap_is_exec_fault(vcpu)); =20 - if (kvm_slot_has_gmem(memslot)) + if (kvm_slot_has_gmem(memslot) && + (kvm_memslot_is_gmem_only(memslot) || + !shared_ipa_fault(vcpu->kvm, fault_ipa))) ret =3D gmem_abort(&s2fd); else ret =3D user_mem_abort(&s2fd); @@ -2482,6 +2518,10 @@ bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_ran= ge *range) if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) return false; =20 + /* We don't support aging for Realms */ + if (kvm_is_realm(kvm)) + return true; + return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt, range->start << PAGE_SHIFT, size, true); @@ -2498,6 +2538,10 @@ bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gf= n_range *range) if (!kvm->arch.mmu.pgt || kvm_vm_is_protected(kvm)) return false; =20 + /* We don't support aging for Realms */ + if (kvm_is_realm(kvm)) + return true; + return KVM_PGT_FN(kvm_pgtable_stage2_test_clear_young)(kvm->arch.mmu.pgt, range->start << PAGE_SHIFT, size, false); @@ -2677,10 +2721,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm, return -EFAULT; =20 /* - * Only support guest_memfd backed memslots with mappable memory, since - * there aren't any CoCo VMs that support only private memory on arm64. + * Only support guest_memfd backed memslots with mappable memory, + * unless the guest is a CCA realm guest. */ - if (kvm_slot_has_gmem(new) && !kvm_memslot_is_gmem_only(new)) + if (kvm_slot_has_gmem(new) && !kvm_memslot_is_gmem_only(new) && + !kvm_is_realm(kvm)) return -EINVAL; =20 hva =3D new->userspace_addr; diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 1e6c04145f6c..31effae067c8 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -630,6 +630,220 @@ static int realm_data_map_init(struct kvm *kvm, unsig= ned long ipa, return ret <=3D 0 ? ret : -ENXIO; } =20 +static unsigned long addr_range_desc(unsigned long phys, unsigned long siz= e, + unsigned long state) +{ + unsigned long count =3D 1; + unsigned long out; + int rmi_size; + + for (rmi_size =3D KVM_PGTABLE_LAST_LEVEL; rmi_size >=3D 0; rmi_size--) { + unsigned long entry_size =3D rmi_range_entry_size(rmi_size); + + if (size =3D=3D entry_size) + break; + if (size > entry_size) { + rmi_size =3D -1; + break; + } + } + + if (rmi_size < 0) { + /* + * Only support mapping at the page level granularity when + * it's an unusual length. This should get us back onto a larger + * block size for the subsequent mappings. + */ + rmi_size =3D 0; + count =3D MIN(size >> PAGE_SHIFT, PTRS_PER_PTE - 1); + } + + WARN_ON(phys & ~PAGE_MASK); + + out =3D FIELD_PREP(RMI_ADDR_RANGE_SIZE_MASK, rmi_size) | + FIELD_PREP(RMI_ADDR_RANGE_COUNT_MASK, count) | + FIELD_PREP(RMI_ADDR_RANGE_STATE_MASK, state); + out |=3D phys & PAGE_MASK; + + return out; +} + +static int realm_map_protected(struct kvm *kvm, + unsigned long ipa, + kvm_pfn_t pfn, + unsigned long map_size, + struct kvm_mmu_memory_cache *memcache) +{ + struct realm *realm =3D &kvm->arch.realm; + phys_addr_t phys =3D __pfn_to_phys(pfn); + phys_addr_t base_phys =3D phys; + phys_addr_t rd =3D virt_to_phys(realm->rd); + phys_addr_t delegated_phys; + unsigned long base_ipa =3D ipa; + unsigned long ipa_top; + int ret =3D 0; + + if (WARN_ON(!IS_ALIGNED(map_size, PAGE_SIZE) || + !IS_ALIGNED(ipa, map_size))) + return -EINVAL; + + if (rmi_delegate_range(phys, map_size, &delegated_phys)) { + if (delegated_phys =3D=3D phys) { + /* + * It's likely we raced with another VCPU on the same + * fault. Assume the other VCPU has handled the fault + * and return to the guest. + */ + return 0; + } + /* Partial delegation - map as much as we can */ + map_size =3D delegated_phys - phys; + } + + ipa_top =3D ipa + map_size; + + while (ipa < ipa_top) { + unsigned long flags =3D RMI_ADDR_TYPE_SINGLE; + unsigned long range_desc =3D addr_range_desc(phys, ipa_top - ipa, + RMI_OP_MEM_DELEGATED); + unsigned long out_top; + + ret =3D rmi_rtt_data_map(rd, ipa, ipa_top, flags, range_desc, + &out_top); + + if (RMI_RETURN_STATUS(ret) =3D=3D RMI_ERROR_RTT) { + /* Create missing RTTs and retry */ + int level =3D RMI_RETURN_INDEX(ret); + + if (WARN_ON(level >=3D KVM_PGTABLE_LAST_LEVEL)) + goto err_undelegate; + ret =3D realm_create_rtt_levels(realm, ipa, level, + level + 1, + memcache); + if (ret) + goto err_undelegate; + + continue; + } + + if (WARN_ON(ret)) + goto err_undelegate; + + phys +=3D out_top - ipa; + ipa =3D out_top; + } + + return 0; + +err_undelegate: + realm_unmap_private_range(kvm, base_ipa, ipa, true); + if (WARN_ON(rmi_undelegate_range(base_phys, map_size))) { + /* Page can't be returned to NS world so is lost */ + get_page(phys_to_page(base_phys)); + } + return -ENXIO; +} + +static int realm_map_non_secure(struct kvm *kvm, + unsigned long ipa, + kvm_pfn_t pfn, + unsigned long size, + enum kvm_pgtable_prot prot, + struct kvm_mmu_memory_cache *memcache) +{ + struct realm *realm =3D &kvm->arch.realm; + unsigned long attr, flags =3D 0; + phys_addr_t rd =3D virt_to_phys(realm->rd); + phys_addr_t phys =3D __pfn_to_phys(pfn); + unsigned long ipa_top =3D ipa + size; + int ret; + + if (WARN_ON(!IS_ALIGNED(size, PAGE_SIZE))) + return -EINVAL; + + switch (prot & (KVM_PGTABLE_PROT_DEVICE | KVM_PGTABLE_PROT_NORMAL_NC)) { + case KVM_PGTABLE_PROT_DEVICE | KVM_PGTABLE_PROT_NORMAL_NC: + return -EINVAL; + case KVM_PGTABLE_PROT_DEVICE: + attr =3D MT_S2_FWB_DEVICE_nGnRE; + break; + case KVM_PGTABLE_PROT_NORMAL_NC: + attr =3D MT_S2_FWB_NORMAL_NC; + break; + default: + attr =3D MT_S2_FWB_NORMAL; + } + + flags |=3D FIELD_PREP(RMI_RTT_UNPROT_MAP_FLAGS_MEMATTR, attr); + + if (prot & KVM_PGTABLE_PROT_R) + flags |=3D FIELD_PREP(RMI_RTT_UNPROT_MAP_FLAGS_S2AP, RMI_S2AP_DIRECT_REA= D); + if (prot & KVM_PGTABLE_PROT_W) + flags |=3D FIELD_PREP(RMI_RTT_UNPROT_MAP_FLAGS_S2AP, RMI_S2AP_DIRECT_WRI= TE); + + flags |=3D RMI_ADDR_TYPE_SINGLE; + + while (ipa < ipa_top) { + unsigned long range_desc =3D addr_range_desc(phys, ipa_top - ipa, + RMI_OP_MEM_UNDELEGATED); + unsigned long out_top; + + ret =3D rmi_rtt_unprot_map(rd, ipa, ipa_top, flags, range_desc, + &out_top); + + if (RMI_RETURN_STATUS(ret) =3D=3D RMI_ERROR_RTT) { + /* Create missing RTTs and retry */ + int level =3D RMI_RETURN_INDEX(ret); + int req_level =3D find_map_level(realm, ipa, ipa_top); + + /* + * There already exists a mapping at the level. May be + * we are relaxing a permission for the given range ? + */ + if (level >=3D req_level) { + realm_unmap_shared_range(kvm, ipa, ipa_top, true); + continue; + } + + ret =3D realm_create_rtt_levels(realm, ipa, level, + req_level, + memcache); + if (ret) + return ret; + + ret =3D rmi_rtt_unprot_map(rd, ipa, ipa_top, flags, + range_desc, &out_top); + } + + if (ret && RMI_RETURN_STATUS(ret) !=3D RMI_ERROR_RTT) + return ret; + + phys +=3D out_top - ipa; + ipa =3D out_top; + } + + return 0; +} + +int realm_map_ipa(struct kvm *kvm, phys_addr_t ipa, + kvm_pfn_t pfn, unsigned long map_size, + enum kvm_pgtable_prot prot, + struct kvm_mmu_memory_cache *memcache) +{ + struct realm *realm =3D &kvm->arch.realm; + + ipa =3D ALIGN_DOWN(ipa, map_size); + if (!kvm_realm_is_private_address(realm, ipa)) { + return realm_map_non_secure(kvm, ipa, pfn, map_size, prot, + memcache); + } + + /* It's impossible to map protected pages read-only. */ + if (WARN_ON(!(prot & KVM_PGTABLE_PROT_W))) + return -EFAULT; + return realm_map_protected(kvm, ipa, pfn, map_size, memcache); +} + static int populate_region_cb(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn, struct page *src_page, void *opaque) { --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC5B23815DF; Wed, 15 Jul 2026 14:30:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125848; cv=none; b=Az7ZWW/lzmIymBYzMESkQ+r01GSxSxTkVF0uLQnJ97bQAL9RGSp/7KmdnSWtAyAZXFzDRHTDY5wlPe0SG6M3LmrA2f5NXSi3M3kA8qqAyuByFgdMQ8Ge3Vh+LeHtzxCz+GCmfzblIrxA9Z/3lardihqMFJKrxaTSl65KXsMabXE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125848; c=relaxed/simple; bh=JZym60zbrF+ZMsN57R7TWSgm37sQOomsgrW5gOlLZu4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=itPYFaTj7W5W8iS+kdsMYIRYjHVYNMGnE7EpOVJiuuDObWt9VsuZQm+dRiGTPZFfXRKjLxfGBSdtSsOSAeDe05I495fw1SD8AmTICslGSOlotz6UD5JkJuQqntKgAuM5rHbl+fLlZ0gADZcZs87USMHRLH8WvMrQnqB7gZQ4ugo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=bbwb03nN; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="bbwb03nN" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 454C41595; Wed, 15 Jul 2026 07:30:42 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 940823F93E; Wed, 15 Jul 2026 07:30:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125846; bh=JZym60zbrF+ZMsN57R7TWSgm37sQOomsgrW5gOlLZu4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bbwb03nNFjXUcW1IZnu9G+dlaX2iZxpyhQQRpzBDed6sVsVmuaR5pE/RC10v8ctD9 KOwdpvlhO/sQDdbjWIRdt4Q09o8SruJXDM5sJih9ItRBD+CS84/MDWL0AT0F1WEMlz ZkZgHQkUXGDN5hhjiNL2llvOYV+5qeVg2T92bODU= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 23/37] KVM: arm64: CCA: Handle realm vCPU load Date: Wed, 15 Jul 2026 15:28:25 +0100 Message-ID: <20260715142841.80544-24-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When loading a realm VCPU much of the work is handled by the RMM so only some of the actions are required. Rearrange kvm_arch_vcpu_load() slightly so we can bail out early for a realm guest. Signed-off-by: Steven Price --- arch/arm64/kvm/arm.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 1558bb12b1b1..4ad9462e9d47 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -707,7 +707,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) struct kvm_s2_mmu *mmu; int *last_ran; =20 - if (is_protected_kvm_enabled()) + if (is_protected_kvm_enabled() || kvm_is_realm(vcpu->kvm)) goto nommu; =20 if (vcpu_has_nv(vcpu)) @@ -751,12 +751,6 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) kvm_vgic_load(vcpu); kvm_vcpu_load_debug(vcpu); kvm_vcpu_load_fgt(vcpu); - if (has_vhe()) - kvm_vcpu_load_vhe(vcpu); - kvm_arch_vcpu_load_fp(vcpu); - kvm_vcpu_pmu_restore_guest(vcpu); - if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) - kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); =20 if (kvm_vcpu_should_clear_twe(vcpu)) vcpu->arch.hcr_el2 &=3D ~HCR_TWE; @@ -778,6 +772,17 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) &vcpu->arch.vgic_cpu.vgic_v3); } =20 + /* No additional state needs to be loaded on Realmed VMs */ + if (vcpu_is_rec(vcpu)) + return; + + if (has_vhe()) + kvm_vcpu_load_vhe(vcpu); + kvm_arch_vcpu_load_fp(vcpu); + kvm_vcpu_pmu_restore_guest(vcpu); + if (kvm_arm_is_pvtime_enabled(&vcpu->arch)) + kvm_make_request(KVM_REQ_RECORD_STEAL, vcpu); + if (!cpumask_test_cpu(cpu, vcpu->kvm->arch.supported_cpus)) vcpu_set_on_unsupported_cpu(vcpu); =20 --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 66B4E481A85; Wed, 15 Jul 2026 14:30:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125852; cv=none; b=YlkOkjpit8p1AXTmtNGjPzLPmJCvAOhFoCGLBkww9+0uWsC4HmxC8lbSjn7bjDSHTlL3k7ZsIKktk9h5gb5EhbIgACMRxmxyD9xjajWfCGkBkPip2DVj+4ZTsRSdLwdRWRbQHxy6cHYQCNqBQcU9hcQRT+wGV61L8oKSMTANFQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125852; c=relaxed/simple; bh=UZ1cXeVFfJIYr/MkjIsCfrnNWtsKIftqp2z8gXgFYYo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SN9Q6tG75JxApFn6beKopvqEGeVjICZSZ/zV13k+SRuF/UtPhOl4+mzcEYg+IkxDyh2PVm90td2XSoWlrgJvP4bVTDPzm3SQ5ESO89j9mdti/uwIhEx0r/ZmG6RmIxICtlK5EK0vLlaflivNUvrK37DfKEX4H0QKyMj7QVGMZuE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=o6EnmQZG; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="o6EnmQZG" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7A02B1576; Wed, 15 Jul 2026 07:30:46 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CC12D3F7B4; Wed, 15 Jul 2026 07:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125850; bh=UZ1cXeVFfJIYr/MkjIsCfrnNWtsKIftqp2z8gXgFYYo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o6EnmQZG2h/hdkpXxcWOgUoWhCE801UW7hgVZogcDSyZ1syCIsvkXeBDZIIC6gl// kmESLtaQmhPPAQypvngDvDNXpH+DY+svS3HiQnFE9byeOPWnPXsOtpYZn2G33YuUh8 rK8hSbpRZa+G0TgDCXG35Uc5ZWPjQs0suoZAhOwM= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 24/37] KVM: arm64: CCA: Validate register access for Realm VMs Date: Wed, 15 Jul 2026 15:28:26 +0100 Message-ID: <20260715142841.80544-25-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM only allows setting the GPRS (x0-x30) and PC for a realm guest. Check this in kvm_arm_set_reg() so that the VMM can receive a suitable error return if other registers are written to. The RMM makes similar restrictions for reading of the guest's registers (this is *confidential* compute after all), however we don't impose the restriction here. This allows the VMM to read (stale) values from the registers which might be useful to read back the initial values even if the RMM doesn't provide the latest version. For migration of a realm VM, a new interface will be needed so that the VMM can receive an (encrypted) blob of the VM's state. Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose Reviewed-by: Joey Gouly Signed-off-by: Steven Price --- Changes since v5: * Upper GPRS can be set as part of a HOST_CALL return, so fix up the test to allow them. --- arch/arm64/kvm/guest.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index b01d6622b872..3e970c4f6214 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -73,6 +73,25 @@ static u64 core_reg_offset_from_id(u64 id) return id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK | KVM_REG_ARM_CORE); } =20 +static bool kvm_realm_validate_core_reg(u64 off) +{ + /* + * Note that GPRs can only sometimes be controlled by the VMM. + * For PSCI only X0-X6 are used, higher registers are ignored (restored + * from the REC). + * For HOST_CALL all of X0-X30 are copied to the RsiHostCall structure. + * For emulated MMIO X0 is always used. + * PC can only be set before the realm is activated. + */ + switch (off) { + case KVM_REG_ARM_CORE_REG(regs.regs[0]) ... + KVM_REG_ARM_CORE_REG(regs.regs[30]): + case KVM_REG_ARM_CORE_REG(regs.pc): + return true; + } + return false; +} + static int core_reg_size_from_offset(const struct kvm_vcpu *vcpu, u64 off) { int size; @@ -716,12 +735,34 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const stru= ct kvm_one_reg *reg) return kvm_arm_sys_reg_get_reg(vcpu, reg); } =20 +/* + * The RMI ABI only enables setting some GPRs and PC. The selection of GPRs + * that are available depends on the Realm state and the reason for the la= st + * exit. All other registers are reset to architectural or otherwise defi= ned + * reset values by the RMM, except for a few configuration fields that + * correspond to Realm parameters. + */ +static bool validate_realm_set_reg(struct kvm_vcpu *vcpu, + const struct kvm_one_reg *reg) +{ + if ((reg->id & KVM_REG_ARM_COPROC_MASK) =3D=3D KVM_REG_ARM_CORE) { + u64 off =3D core_reg_offset_from_id(reg->id); + + return kvm_realm_validate_core_reg(off); + } + + return false; +} + int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) { /* We currently use nothing arch-specific in upper 32 bits */ if ((reg->id & ~KVM_REG_SIZE_MASK) >> 32 !=3D KVM_REG_ARM64 >> 32) return -EINVAL; =20 + if (kvm_is_realm(vcpu->kvm) && !validate_realm_set_reg(vcpu, reg)) + return -EINVAL; + switch (reg->id & KVM_REG_ARM_COPROC_MASK) { case KVM_REG_ARM_CORE: return set_core_reg(vcpu, reg); case KVM_REG_ARM_FW: --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E6BAE481FC4; Wed, 15 Jul 2026 14:30:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125857; cv=none; b=VQ4gcWtZ4uP/o4E+Hj3JqNqLzVaw/noBPf30h8IniPCqoFoi+UhgDweKFe7wFSYV/h6iCKeTp/KzZLauuf6r/odm7nOMxgTfVqdQDACjcPTnbvsR1U05a1qP+UTbpdeQt+87NShIkWR2GftQXnQzipn1atzyfdUQ1yWTPW+VS3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125857; c=relaxed/simple; bh=nJDhPGbO37qxidjuMaydIMpdO+0UJH4FdG/uUVJ/iQs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iSRhsBYBcGwooADCpqt9vqDYydz1wvDrLl+wzf3ifDQ2F5QEiLFYJmn0dzik7u3iIzoMH+750/g/GrgrAvKpmaDRhAztmP3ODnQsS+deT06Fj4jf/AFPpopoOoheMIfJSs3CWMLMHP9HRl0zxWsGwrrG3T2uGGEVuzpKaiwbGjQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=kkMgxFhc; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="kkMgxFhc" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 43C991691; Wed, 15 Jul 2026 07:30:51 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A06E3F7B4; Wed, 15 Jul 2026 07:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125855; bh=nJDhPGbO37qxidjuMaydIMpdO+0UJH4FdG/uUVJ/iQs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kkMgxFhcdIoGgJ9FLKytgljozN3opkd3fAsftszhs3pfxI+DwFaCexKmWPL9xmDGF 0mRynr7hhT1rbnV6f/kNsZ5pLsti0bFmXLV1/s6OgZ5Jy1LxblkMhirY5uxT2mBzGi BfWG7UPpdyORiRhcRPdpXUg+3KpffhHAZO3qKJqA= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 25/37] KVM: arm64: CCA: Handle Realm PSCI requests Date: Wed, 15 Jul 2026 15:28:27 +0100 Message-ID: <20260715142841.80544-26-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some PSCI commands cause a REC exit and the host has to call RMI_PSCI_COMPLETE to provide the status value to return to the guest. Co-developed-by: Suzuki K Poulose Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price --- Changes since v14: * Dropped the support for providing the target REC for a PSCI call (as per v2.0-bet2 spec). Changes since v13: * The ioctl KVM_ARM_VCPU_RMI_PSCI_COMPLETE has gone. The RMI call is made automatically just before entering the REC again. Changes since v12: * Change return code for non-realms to -ENXIO to better represent that the ioctl is invalid for non-realms (checkpatch is insistent that "ENOSYS means 'invalid syscall nr' and nothing else"). Changes since v11: * RMM->RMI renaming. Changes since v6: * Use vcpu_is_rec() rather than kvm_is_realm(vcpu->kvm). * Minor renaming/formatting fixes. --- arch/arm64/include/asm/kvm_rmi.h | 2 ++ arch/arm64/kvm/psci.c | 14 ++++++++++++ arch/arm64/kvm/rmi.c | 38 ++++++++++++++++++++++++++++++++ 3 files changed, 54 insertions(+) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 718c7128a3c3..a9bb9aabee5d 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -120,6 +120,8 @@ int realm_map_ipa(struct kvm *kvm, phys_addr_t ipa, enum kvm_pgtable_prot prot, struct kvm_mmu_memory_cache *memcache); =20 +int realm_psci_complete(struct kvm_vcpu *source, unsigned long status); + static inline bool kvm_realm_is_private_address(struct realm *realm, unsigned long addr) { diff --git a/arch/arm64/kvm/psci.c b/arch/arm64/kvm/psci.c index 3b5dbe9a0a0e..b0983ee416a2 100644 --- a/arch/arm64/kvm/psci.c +++ b/arch/arm64/kvm/psci.c @@ -142,6 +142,20 @@ static unsigned long kvm_psci_vcpu_affinity_info(struc= t kvm_vcpu *vcpu) /* Ignore other bits of target affinity */ target_affinity &=3D target_affinity_mask; =20 + if (vcpu_is_rec(vcpu)) { + struct kvm_vcpu *target_vcpu; + + /* RMM supports only zero affinity level */ + if (lowest_affinity_level !=3D 0) + return PSCI_RET_INVALID_PARAMS; + + target_vcpu =3D kvm_mpidr_to_vcpu(kvm, target_affinity); + if (!target_vcpu) + return PSCI_RET_INVALID_PARAMS; + + return PSCI_RET_SUCCESS; + } + /* * If one or more VCPU matching target affinity are running * then ON else OFF diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 31effae067c8..8fb6403893e8 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -3,6 +3,7 @@ * Copyright (C) 2023-2026 ARM Ltd. */ =20 +#include #include =20 #include @@ -119,6 +120,18 @@ static void free_rtt(phys_addr_t phys) kvm_account_pgtable_pages(phys_to_virt(phys), -1); } =20 +int realm_psci_complete(struct kvm_vcpu *source, unsigned long status) +{ + int ret; + + ret =3D rmi_psci_complete(virt_to_phys(source->arch.rec.rec_page), + status); + if (ret) + return -ENXIO; + + return 0; +} + static int realm_rtt_create(struct realm *realm, unsigned long addr, int level, @@ -1115,6 +1128,28 @@ static void kvm_complete_ripas_change(struct kvm_vcp= u *vcpu) rec->run->exit.ripas_base =3D base; } =20 +static void kvm_rec_complete_psci(struct kvm_vcpu *vcpu) +{ + struct rec_run *run =3D vcpu->arch.rec.run; + unsigned long status =3D PSCI_RET_DENIED; + unsigned long ret =3D vcpu_get_reg(vcpu, 0); + + switch (run->exit.gprs[0]) { + case PSCI_0_2_FN64_CPU_ON: { + if (ret !=3D PSCI_RET_SUCCESS && + ret !=3D PSCI_RET_ALREADY_ON) + status =3D PSCI_RET_DENIED; + else + status =3D PSCI_RET_SUCCESS; + break; + } + default: + return; + } + + realm_psci_complete(vcpu, status); +} + /* * kvm_rec_pre_enter - Complete operations before entering a REC * @@ -1139,6 +1174,9 @@ int kvm_rec_pre_enter(struct kvm_vcpu *vcpu) for (int i =3D 0; i < REC_RUN_GPRS; i++) rec->run->enter.gprs[i] =3D vcpu_get_reg(vcpu, i); break; + case RMI_EXIT_PSCI: + kvm_rec_complete_psci(vcpu); + break; case RMI_EXIT_RIPAS_CHANGE: kvm_complete_ripas_change(vcpu); break; --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 93A1238F249; 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arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="WdClv8Nn" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7ED2D1576; Wed, 15 Jul 2026 07:30:55 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DAA273F7B4; Wed, 15 Jul 2026 07:30:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125859; bh=2aEkh45BUa3FK3LhN0kNkj+5k/8j4Xl4y0clqTp86E4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WdClv8Nnewj7SDK99ddz4Y2bT+yeTAd1HYAfW+ATvuRDIXSL+RzB9ZxC6zFN382T3 I1+1Zx5hvN7S16QnFNy1kuiGFjKk5mzqtRUMIuLzNzww+3Eac1pvM83w8oqq2bZqs9 lpg/JL8au3NzURpfQrB76GZDUlMaWjnuC5gfuowI= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 26/37] KVM: arm64: WARN on injected undef exceptions Date: Wed, 15 Jul 2026 15:28:28 +0100 Message-ID: <20260715142841.80544-27-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RMM doesn't allow injection of a undefined exception into a realm guest. Add a WARN to catch if this ever happens. Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- Changes since v6: * if (x) WARN(1, ...) makes no sense, just WARN(x, ...)! --- arch/arm64/kvm/inject_fault.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c index 6492397b73d7..613f223bc7a3 100644 --- a/arch/arm64/kvm/inject_fault.c +++ b/arch/arm64/kvm/inject_fault.c @@ -327,6 +327,7 @@ void kvm_inject_size_fault(struct kvm_vcpu *vcpu) */ void kvm_inject_undefined(struct kvm_vcpu *vcpu) { + WARN(vcpu_is_rec(vcpu), "Unexpected undefined exception injection to REC"= ); if (vcpu_el1_is_32bit(vcpu)) inject_undef32(vcpu); else --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 61464481FD1; Wed, 15 Jul 2026 14:31:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125868; cv=none; b=GZUhaxVOgV4WXc8RVaJt9aaaDljrC8kDuVKV3TZCSJOK+mgO9TLRpFnrl7OiI+nPwx3rHekyC82chRJkqfa+n7r1Bvs1K/jjKq/6J33e59je0XgteFlu/bvWBbJ+nPF3g+7ArYZGkXZgGZWhJUg/K+KVCC/wi5y6UExyxXguBSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125868; c=relaxed/simple; bh=tgn8iDXNgu5mVAiBC+c6ImZ3Rk5yLqEv8Ic4zHNhfuI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=orTw0/EwqAsuBPHgLPNpGdXnalsy0LX/L5fMPrNj1Hda5CvudiLbb+w8aDya8oC6VxIyMv1NenDnTH6zjipTvJ+5t9M2iEjM2Occxnzs83+Ybcu5hj5azpAr9KlqX/sMK2eH6vMTcLtFtebTV+D0TRkxQh6w7roY5NU1xqXbPUM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pY3uiBwd; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pY3uiBwd" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF59615A1; Wed, 15 Jul 2026 07:30:59 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 28EA83F7B4; Wed, 15 Jul 2026 07:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125864; bh=tgn8iDXNgu5mVAiBC+c6ImZ3Rk5yLqEv8Ic4zHNhfuI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pY3uiBwduwz5KkvvYe2YfDc5v1QEM6FcojmNtmLTtOTMV3cFNw2y4y0azEUZamzQo 3xULvBDMQzPcp/81zFxALrSOvNF+LDRp0MkdyT7pBtX7pbqDVCSI0n/GQRxg21i+Js d8ybD/xbyb7m2/8ttm8Qkx6y3DS0hwlrycwTnqp8= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Joey Gouly , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 27/37] KVM: arm64: CCA: Allow userspace to inject aborts Date: Wed, 15 Jul 2026 15:28:29 +0100 Message-ID: <20260715142841.80544-28-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Joey Gouly Extend KVM_SET_VCPU_EVENTS to support realms, where KVM cannot set the system registers, and the RMM must perform it on next REC entry. Signed-off-by: Joey Gouly Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- Documentation/virt/kvm/api.rst | 2 ++ arch/arm64/kvm/guest.c | 24 ++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index e39d146b34a3..85bec9b4f021 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -1314,6 +1314,8 @@ User space may need to inject several types of events= to the guest. Set the pending SError exception state for this VCPU. It is not possible to 'cancel' an Serror that has been made pending. =20 +User space cannot inject SErrors into Realms. + If the guest performed an access to I/O memory which could not be handled = by userspace, for example because of missing instruction syndrome decode information or because there is no device mapped at the accessed IPA, then diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 3e970c4f6214..5469c9a97fad 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -827,6 +827,30 @@ int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, u64 esr =3D events->exception.serror_esr; int ret =3D 0; =20 + if (vcpu_is_rec(vcpu)) { + /* Cannot inject SError into a Realm. */ + if (serror_pending) + return -EINVAL; + + /* + * If a data abort is pending, set the flag and let the RMM + * inject an SEA when the REC is scheduled to be run. + */ + if (ext_dabt_pending) { + /* + * Can only inject SEA into a Realm if the previous exit + * was due to a data abort of an Unprotected IPA. + */ + if (!(vcpu->arch.rec.run->enter.flags & REC_ENTER_FLAG_EMULATED_MMIO)) + return -EINVAL; + + vcpu->arch.rec.run->enter.flags &=3D ~REC_ENTER_FLAG_EMULATED_MMIO; + vcpu->arch.rec.run->enter.flags |=3D REC_ENTER_FLAG_INJECT_SEA; + } + + return 0; + } + /* * Immediately commit the pending SEA to the vCPU's architectural * state which is necessary since we do not return a pending SEA --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9284B38D3F8; Wed, 15 Jul 2026 14:31:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125872; cv=none; b=Tyuvj9lRDHAVZb0wl3PVMKtQoNHcJOXb9xumcfmGql5vSXMLK/waiGdfzm8lLA4g5yb8VZFXuUleJm2wAUO2fGPh6yLPLo13SQ5koq8g4ErCUGeswF4C7XWHFbKaPH9CxTRZqeNqNw3ARc2erBBTGMqM3vPU82RyBGla2WS3fRU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125872; c=relaxed/simple; bh=dof2MvH5ZZdVUnaNbvRlQgoLjFLC9SgvdrrOrj7zQ/Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UDzXjkKjZF1B8vZwn2SpCFreVa7X1I4f79qtPUfjp1BYYZ1wzUEX0RFbwHtqs8sqdK+D2ezqcF0PYZhg+9nibQ8QmDGyR4IsNvUV8h/qvnC2GLZcW15cNCiun4/sgxONtQxzbu9EiCFJ3MC7Ye+6Kv6yYfdOvssofvKBlrxFY4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=o2jZ38OJ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="o2jZ38OJ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 077731BA8; Wed, 15 Jul 2026 07:31:04 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6AA253F7B4; Wed, 15 Jul 2026 07:31:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125868; bh=dof2MvH5ZZdVUnaNbvRlQgoLjFLC9SgvdrrOrj7zQ/Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=o2jZ38OJ48MTBmi0sJcCw1LnH3btREr/ObkwuJ8+cifSdVYW5zzoV3EjgOvXr2rcr mJ8SDezMSUUlDutNIoQfw1LeuMpJMpe5BIOHYrzuOasV8PoQomJuzvr+WeZxK5bkfw FzDNCrzzcNBj8FLBPjK5P/rN2lz8fCrLHC+dbAao= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Joey Gouly , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 28/37] KVM: arm64: CCA: Support RSI_HOST_CALL Date: Wed, 15 Jul 2026 15:28:30 +0100 Message-ID: <20260715142841.80544-29-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Joey Gouly Realm VMs can talk to the hypervisor using the RSI_HOST_CALL SMC. The RMM forwards this to the host and KVM handles them as regular hypercalls. Signed-off-by: Joey Gouly Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- Changes since v7: * Avoid turning a negative return from kvm_smccc_call_handler() into a error response to the guest. Instead propagate the error back to user space. Changes since v4: * Setting GPRS is now done by kvm_rec_enter() rather than rec_exit_host_call() (see previous patch - arm64: RME: Handle realm enter/exit). This fixes a bug where the registers set by user space were being ignored. --- arch/arm64/kvm/rmi-exit.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/kvm/rmi-exit.c b/arch/arm64/kvm/rmi-exit.c index c668cbfa971a..78d9189fd5ca 100644 --- a/arch/arm64/kvm/rmi-exit.c +++ b/arch/arm64/kvm/rmi-exit.c @@ -113,6 +113,19 @@ static int rec_exit_ripas_change(struct kvm_vcpu *vcpu) return -EFAULT; } =20 +static int rec_exit_host_call(struct kvm_vcpu *vcpu) +{ + int i; + struct realm_rec *rec =3D &vcpu->arch.rec; + + vcpu->stat.hvc_exit_stat++; + + for (i =3D 0; i < REC_RUN_GPRS; i++) + vcpu_set_reg(vcpu, i, rec->run->exit.gprs[i]); + + return kvm_smccc_call_handler(vcpu); +} + static void update_arch_timer_irq_lines(struct kvm_vcpu *vcpu) { struct realm_rec *rec =3D &vcpu->arch.rec; @@ -188,6 +201,8 @@ int handle_rec_exit(struct kvm_vcpu *vcpu, int rec_run_= ret) return rec_exit_psci(vcpu); case RMI_EXIT_RIPAS_CHANGE: return rec_exit_ripas_change(vcpu); + case RMI_EXIT_HOST_CALL: + return rec_exit_host_call(vcpu); } =20 kvm_pr_unimpl("Unsupported exit reason: %u\n", --=20 2.43.0 From nobody Fri Jul 17 04:59:46 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C8A8838D403; Wed, 15 Jul 2026 14:31:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125876; cv=none; b=LHZsUgiwkyiufvYPGqc4EN/P1TY6fW1UyM4Pqcduil7JXYMY4ow730xTYHf+cZnIReyzze9Ht/dhY2HGp4l7dBHlcXcYKkV37Nra3Sh0p587++AShZiNUK/c/PQOHmgo7woiSw3+zowz9vM9wb0sMvwgqOOh+DO823aJaHrbbvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125876; c=relaxed/simple; bh=5xUM0oOtKd9m3NaVfQB4WcOYjf14OgtuIZ8nBG5ODJ4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ajOoqRZb0WkNLpi+SWeowuEAFbIRWtZ48d0r5jC32RXqzV7Z5CDOE/hS9Pdp8WVLzKWmlkEdrsPELYS3T0cc9pTliSSLJiuNXD1kUeOcGLMh01vY6CQCJR0m3A6ZB4D9x4O2nNMo7t5AU3HEGIGsPti0Ud/+V+JyqPA8b8+XcbM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=V0UIg7Ri; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="V0UIg7Ri" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5944D1576; Wed, 15 Jul 2026 07:31:08 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 963F43F7B4; Wed, 15 Jul 2026 07:31:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125872; bh=5xUM0oOtKd9m3NaVfQB4WcOYjf14OgtuIZ8nBG5ODJ4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V0UIg7RicJYbfwbBFygke6dSHrm/S/IxA4/b4YvtmWahu8ekTcVxOAOPGiBh5Sbmy Rj6EIhaF6jaPnCIqvQ5ilx81PH26ij97JzgNNUar8/gtn4MLYeDOd6YKtcarDoDs4Q rXpCallJQbsijk/KqOiBqw2UzC9HK2Vx0IgIbU94= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Suzuki K Poulose , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 29/37] KVM: arm64: CCA: Allow checking SVE on VM instance Date: Wed, 15 Jul 2026 15:28:31 +0100 Message-ID: <20260715142841.80544-30-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Suzuki K Poulose Given we have different types of VMs supported, check the support for SVE for the given instance of the VM to accurately report the status. Signed-off-by: Suzuki K Poulose Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Joey Gouly --- Changes since v10: * RME->RMI renaming. * Adapt to move CAP check to kvm_realm_ext_allowed(). --- arch/arm64/include/asm/kvm_rmi.h | 2 ++ arch/arm64/kvm/arm.c | 2 ++ arch/arm64/kvm/rmi.c | 5 +++++ 3 files changed, 9 insertions(+) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index a9bb9aabee5d..7f0c059ac7cf 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -96,6 +96,8 @@ struct realm_rec { void kvm_init_rmi(void); u32 kvm_rmm_ipa_limit(void); =20 +bool kvm_rmi_supports_sve(void); + int kvm_init_realm(struct kvm *kvm); int kvm_activate_realm(struct kvm *kvm); void kvm_destroy_realm(struct kvm *kvm); diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 4ad9462e9d47..aa7617e72e22 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -151,6 +151,8 @@ static bool kvm_realm_ext_allowed(long ext) case KVM_CAP_ARM_RMI: case KVM_CAP_SYNC_MMU: return true; + case KVM_CAP_ARM_SVE: + return kvm_rmi_supports_sve(); } return false; } diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 8fb6403893e8..2310f2b608a7 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -25,6 +25,11 @@ static bool rmi_has_feature(int reg, unsigned long featu= re) return !!u64_get_bits(rmi_feat_reg(reg), feature); } =20 +bool kvm_rmi_supports_sve(void) +{ + return rmi_has_feature(0, RMI_FEATURE_REGISTER_0_SVE); +} + u32 kvm_rmm_ipa_limit(void) { return u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_S2SZ); --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 84D6648BD26; Wed, 15 Jul 2026 14:31:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125881; cv=none; b=iVVzrf4RembBwrDvgNIAKhQrY/TFWQRawq0pXWrrQUdTmI/2H/m0E1lpjyK9nFe/8KnwA3gHKXnw1H1/9BtBri2Jj4I2LBe3WvXcaUBQQNtImEDRmdyDmH/KRJ+pWpgHUpMA4BRHKqrob3EM+PMv8jEqVFgLqxGgMAFr6LhSiUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125881; c=relaxed/simple; bh=/DkC06ykICbYbu8lRH1puAEPBlPtvdphP1WP+AibYYM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hjqSvfw0t2HLRJ2oDEBRzMOUbWSoIczDuGHnf05EMssQGdjnnA1lNFzOSph/2QV/Ss2RYxlrOeexM9Ubt15qfOWT4KKKbYC2U0E84hXJ0b3aptAYA65M/k9bjUgD2Hd6ExJQwH9SPsDHMZbitJ60FScj4vdUIuwXMZL2Z2V4NUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Mkfra4+I; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Mkfra4+I" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EA18F15A1; Wed, 15 Jul 2026 07:31:12 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0459F3F7B4; Wed, 15 Jul 2026 07:31:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125877; bh=/DkC06ykICbYbu8lRH1puAEPBlPtvdphP1WP+AibYYM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Mkfra4+IcJ0yxokQd4mwR1MWgWfiDKuRjdn49nomVQc2bK/inpRfIaPDYkzt+wEGh 7B7RSCiauG7iw7RB6PQODvm29CUcIkOmXG4etFnbVhdGgBGjlq3jIuksREVyCNI+O9 tWqm6qMaCmwG1cPaXPwJN6sUlxr/7/BljXrsDKxs= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 30/37] KVM: arm64: CCA: Prevent Device mappings for realms Date: Wed, 15 Jul 2026 15:28:32 +0100 Message-ID: <20260715142841.80544-31-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Physical device assignment is not yet supported. RMM v2.0 does add the relevant APIs, but device assignment is a big topic so will be handled in a future patch series. For now prevent device mappings when the guest is a realm. Signed-off-by: Steven Price --- Changes from v6: * Fix the check in user_mem_abort() to prevent all pages that are not guest_memfd() from being mapped into the protected half of the IPA. Changes from v5: * Also prevent accesses in user_mem_abort() --- arch/arm64/kvm/mmu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c index 79119cb136b0..dc27f3dfb337 100644 --- a/arch/arm64/kvm/mmu.c +++ b/arch/arm64/kvm/mmu.c @@ -1261,6 +1261,10 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr= _t guest_ipa, if (is_protected_kvm_enabled()) return -EPERM; =20 + /* We don't support mapping special pages into a Realm */ + if (kvm_is_realm(kvm)) + return -EPERM; + size +=3D offset_in_page(guest_ipa); guest_ipa &=3D PAGE_MASK; =20 --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E99FD48B37F; Wed, 15 Jul 2026 14:31:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125887; cv=none; b=XESe3u1sD8REv2VzwNhJaK1AfkBcIoim6fyVe6B+BgR+8i3/v4RRkkxSyFVqqS/bG262CCc80XV86sCNA+mNt6+0TISgjlwFMLCiBHn46Ae0SFqHRkRQddFMihRXj81s3PhGBga6KF9J6tA5S1q+dxKwUeMlHivc0PzlcEgZ8qU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125887; c=relaxed/simple; bh=0MsM9pKBxJreAuCyKGFQTgLjjuhyGR3qTYLbWXvJXjU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sX8JheSQPv0OevTu7UB9im2Kzp+/EfVgnDDO4ljTmhFnjHhHE8IPIuU3Len9nWBX5sylaDHkTswX9pPW8P9QpAw7b6v6vAEu7TbQmwsR/KdStrfKb+Fd+lMyS98LJz8p+KMrge4YxE1iwFXrP1MYaM6xG1f2j8se2AcenjJzeKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Tz6qlmCI; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Tz6qlmCI" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8DF2B1691; Wed, 15 Jul 2026 07:31:17 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 992AB3F7B4; Wed, 15 Jul 2026 07:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125881; bh=0MsM9pKBxJreAuCyKGFQTgLjjuhyGR3qTYLbWXvJXjU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Tz6qlmCI+1/btC5Tib5mw3MJudEJYPNFQ6igymIhrJslwk9NMsbpXOwfs3Jygpc7K nVyoMlCIGeIG5YYSVGjDbz+MTqaq5m9rHsk+IwAUkWCk049xXgfb5fx+NU/21S8I/u mGAYSvyHq/ZLQ/y8tp6qQ1LMFIey6zk8npFywobk= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 31/37] KVM: arm64: CCA: Propagate breakpoint and watchpoint counts to userspace Date: Wed, 15 Jul 2026 15:28:33 +0100 Message-ID: <20260715142841.80544-32-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker The RMM describes the maximum number of BPs/WPs available to the guest in the Feature Register 0. Propagate those numbers into ID_AA64DFR0_EL1, which is visible to userspace. A VMM needs this information in order to set up realm parameters. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose Reviewed-by: Joey Gouly --- arch/arm64/include/asm/kvm_rmi.h | 2 ++ arch/arm64/kvm/rmi.c | 19 +++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 3 +++ 3 files changed, 24 insertions(+) diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 7f0c059ac7cf..3ec6525ae95f 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -96,6 +96,8 @@ struct realm_rec { void kvm_init_rmi(void); u32 kvm_rmm_ipa_limit(void); =20 +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); + bool kvm_rmi_supports_sve(void); =20 int kvm_init_realm(struct kvm *kvm); diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 2310f2b608a7..491097a57328 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -35,6 +35,25 @@ u32 kvm_rmm_ipa_limit(void) return u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_S2SZ); } =20 +u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) +{ + u32 bps =3D u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_NUM_BPS); + u32 wps =3D u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_NUM_WPS); + u32 ctx_cmps; + + /* Ensure CTX_CMPs is still valid */ + ctx_cmps =3D FIELD_GET(ID_AA64DFR0_EL1_CTX_CMPs, val); + ctx_cmps =3D min(bps, ctx_cmps); + + val &=3D ~(ID_AA64DFR0_EL1_BRPs_MASK | ID_AA64DFR0_EL1_WRPs_MASK | + ID_AA64DFR0_EL1_CTX_CMPs); + val |=3D FIELD_PREP(ID_AA64DFR0_EL1_BRPs_MASK, bps) | + FIELD_PREP(ID_AA64DFR0_EL1_WRPs_MASK, wps) | + FIELD_PREP(ID_AA64DFR0_EL1_CTX_CMPs, ctx_cmps); + + return val; +} + static int get_start_level(struct realm *realm) { return 4 - stage2_pgtable_levels(realm->ia_bits); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5d5c579d4579..e0fe9f2562bc 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2142,6 +2142,9 @@ static u64 sanitise_id_aa64dfr0_el1(const struct kvm_= vcpu *vcpu, u64 val) /* Hide BRBE from guests */ val &=3D ~ID_AA64DFR0_EL1_BRBE_MASK; =20 + if (vcpu_is_rec(vcpu)) + return kvm_realm_reset_id_aa64dfr0_el1(vcpu, val); + return val; } =20 --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2D7102222D0; Wed, 15 Jul 2026 14:31:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125891; cv=none; b=I96IZ20VxlKRNWXP7rFJSSY/pVD+s4FYrRQCbYYXBariikZ18sf2uae1odfoyvUsp3L347DV3X56fDLnAZyPJMCQfjbBG5xU7iQCBQlJsXmKTEkFB4IDdxesghBuQyi8hbTm7Ic70qf2bn5dADUBwZaT5YR65BSoFsuivKrJyUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125891; c=relaxed/simple; bh=bzMrd1BqoPkxp7vkmCHD+vARLfctGd6IuFpz4Uz0tUQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=NRwgZoFIRgSnI7ei13v7yK0V2wuCx+JYnSxrEZ5hdW+RRiCovaYHzhsiT5En5GYd1QswZzHM1MKK21zAhpPyEymStUe/WiPB2Ihs9venJ91wq2OKjbVHiQy+zp9haCbOaGiyKLCH4QbtOQGanOBTcwT6S3C5hxGjWYrtd6K8b6U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=tjCwL1Ne; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="tjCwL1Ne" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0574E1576; Wed, 15 Jul 2026 07:31:23 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 392E63F7B4; Wed, 15 Jul 2026 07:31:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125887; bh=bzMrd1BqoPkxp7vkmCHD+vARLfctGd6IuFpz4Uz0tUQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tjCwL1NewjLx7UjGlSY6+a0y1aq4ttXG8Ij+BMFCeWeArd0BrU7pjtjMU/MYJJfeW 8Z2LzLQUNeHIckbE3XSuWXo8VkiqAMUAh3zQPPVV45kIfoT0BJMMiwOsOBKhhjTuwO LDPgXNv1QvGfxlWBbnXU/wkoF6gIcJ5pMdPUPqt4= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 32/37] KVM: arm64: CCA: Set breakpoint parameters through SET_ONE_REG Date: Wed, 15 Jul 2026 15:28:34 +0100 Message-ID: <20260715142841.80544-33-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker Allow userspace to configure the number of breakpoints and watchpoints of a Realm VM through KVM_SET_ONE_REG ID_AA64DFR0_EL1. The KVM sys_reg handler checks the user value against the maximum value given by RMM (arm64_check_features() gets it from the read_sanitised_id_aa64dfr0_el1() reset handler). Userspace discovers that it can write these fields by issuing a KVM_ARM_GET_REG_WRITABLE_MASKS ioctl. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- arch/arm64/kvm/guest.c | 7 +++++++ arch/arm64/kvm/rmi.c | 3 +++ arch/arm64/kvm/sys_regs.c | 17 +++++++++++------ 3 files changed, 21 insertions(+), 6 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 5469c9a97fad..3ed563e85572 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -735,6 +735,8 @@ int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct= kvm_one_reg *reg) return kvm_arm_sys_reg_get_reg(vcpu, reg); } =20 +#define KVM_REG_ARM_ID_AA64DFR0_EL1 ARM64_SYS_REG(3, 0, 0, 5, 0) + /* * The RMI ABI only enables setting some GPRs and PC. The selection of GPRs * that are available depends on the Realm state and the reason for the la= st @@ -749,6 +751,11 @@ static bool validate_realm_set_reg(struct kvm_vcpu *vc= pu, u64 off =3D core_reg_offset_from_id(reg->id); =20 return kvm_realm_validate_core_reg(off); + } else { + switch (reg->id) { + case KVM_REG_ARM_ID_AA64DFR0_EL1: + return true; + } } =20 return false; diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 491097a57328..6850338e2f19 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -493,6 +493,7 @@ static int realm_create_rd(struct kvm *kvm) void *rd =3D NULL; phys_addr_t rd_phys, params_phys, top_delegated; size_t pgd_size =3D kvm_pgtable_stage2_pgd_size(kvm->arch.mmu.vtcr); + u64 dfr0 =3D kvm_read_vm_id_reg(kvm, SYS_ID_AA64DFR0_EL1); int r; =20 realm->ia_bits =3D VTCR_EL2_IPA(kvm->arch.mmu.vtcr); @@ -520,6 +521,8 @@ static int realm_create_rd(struct kvm *kvm) params->rtt_level_start =3D get_start_level(realm); params->rtt_num_start =3D pgd_size / PAGE_SIZE; params->rtt_base =3D kvm->arch.mmu.pgd_phys; + params->num_bps =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr0); + params->num_wps =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr0); params->hash_algo =3D RMI_HASH_SHA_256; =20 if (kvm->arch.arm_pmu) { diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e0fe9f2562bc..e47be8f8d259 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2174,6 +2174,9 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, { u8 debugver =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val); u8 pmuver =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val); + u8 bps =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, val); + u8 wps =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, val); + u8 ctx_cmps =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, val); =20 /* * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the @@ -2193,10 +2196,11 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcp= u, val &=3D ~ID_AA64DFR0_EL1_PMUVer_MASK; =20 /* - * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a - * nonzero minimum safe value. + * ID_AA64DFR0_EL1.DebugVer, BRPs and WRPs all have to be greater than + * zero. CTX_CMPs is never greater than BRPs. */ - if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP) + if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP || !bps || !wps || + ctx_cmps > bps) return -EINVAL; =20 if (ignore_feat_doublelock(vcpu, val)) { @@ -2429,10 +2433,11 @@ static int set_id_reg(struct kvm_vcpu *vcpu, const = struct sys_reg_desc *rd, mutex_lock(&vcpu->kvm->arch.config_lock); =20 /* - * Once the VM has started the ID registers are immutable. Reject any - * write that does not match the final register value. + * Once the VM has started or the Realm descriptor is created, the ID + * registers are immutable. Reject any write that does not match the + * final register value. */ - if (kvm_vm_has_ran_once(vcpu->kvm)) { + if (kvm_vm_has_ran_once(vcpu->kvm) || kvm_realm_is_created(vcpu->kvm)) { if (val !=3D read_id_reg(vcpu, rd)) ret =3D -EBUSY; else --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 50AD0492188; Wed, 15 Jul 2026 14:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125898; cv=none; b=rNzLqR+CWZ2KGzcJOKJK1zd0s4QdCQ19sSS50R2Cy7yT7S0Z2TMu3FjjLqOvfJQ4kBdHOwOnI5VhEuzoSzgAZFUoz4mggUUG/X71kZVT6XA3U7Cs11VusdzeHr6++Iz8d8PXTyxONyHgMEaC2COWkTTNkmXaqYmrtTO9Rt3z350= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125898; c=relaxed/simple; bh=ZYcCh7k1aw+SKkMmLc4T5K6rPKlUo5r+aLl26084mlI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EoQLBYI8Vczc0p244MDn5Q200JobzbEg2kF8CeAeY2o223QYqyL5VKXJazSKrIKI04UQiYoOlHnBUjcjLbQCWkvmdT0KPq0c6v8/BB3PkwIb7bBkvkCc7MRNtdr15ZeQrN7xPPrT2y2D0H91GQUR/MUzA1jtVbuPysbLrVXwTRU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=UD5+B8P8; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="UD5+B8P8" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B872715A1; Wed, 15 Jul 2026 07:31:27 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 928953F7B4; Wed, 15 Jul 2026 07:31:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125891; bh=ZYcCh7k1aw+SKkMmLc4T5K6rPKlUo5r+aLl26084mlI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UD5+B8P8WFmvn5xj5pLLSrxb8nrouH7oUsuNW6on20tpsJ6LtvZN1ni5e1XkPksME fpoHT/cIWwJLIJcsqwqHY+HI9YYRgL9poYPITPsCzsOlD77Anx6sqLzOjMGvbgF5vQ 571IY/bNLXqvCVdlo2rACV2ZXo8APLmNfyuWmY5U= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 33/37] KVM: arm64: CCA: Propagate max SVE vector length from the RMM Date: Wed, 15 Jul 2026 15:28:35 +0100 Message-ID: <20260715142841.80544-34-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker RMM provides the maximum vector length it supports for a guest in its feature register. Make it visible to the rest of KVM and to userspace via KVM_REG_ARM64_SVE_VLS. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Reviewed-by: Gavin Shan Reviewed-by: Suzuki K Poulose --- arch/arm64/include/asm/kvm_host.h | 2 +- arch/arm64/include/asm/kvm_rmi.h | 1 + arch/arm64/kvm/guest.c | 2 +- arch/arm64/kvm/reset.c | 12 ++++++++++-- arch/arm64/kvm/rmi.c | 6 ++++++ 5 files changed, 19 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 993ead6e6449..3542b32433b7 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -78,9 +78,9 @@ enum kvm_mode kvm_get_mode(void); static inline enum kvm_mode kvm_get_mode(void) { return KVM_MODE_NONE; }; #endif =20 -extern unsigned int __ro_after_init kvm_sve_max_vl; extern unsigned int __ro_after_init kvm_host_sve_max_vl; int __init kvm_arm_init_sve(void); +unsigned int kvm_sve_get_max_vl(struct kvm *kvm); =20 u32 __attribute_const__ kvm_target_cpu(void); void kvm_reset_vcpu(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/include/asm/kvm_rmi.h b/arch/arm64/include/asm/kvm_= rmi.h index 3ec6525ae95f..420e99fca07e 100644 --- a/arch/arm64/include/asm/kvm_rmi.h +++ b/arch/arm64/include/asm/kvm_rmi.h @@ -95,6 +95,7 @@ struct realm_rec { =20 void kvm_init_rmi(void); u32 kvm_rmm_ipa_limit(void); +unsigned int kvm_realm_sve_max_vl(void); =20 u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val); =20 diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 3ed563e85572..f48fc0d5a249 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -375,7 +375,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (vq_present(vqs, vq)) max_vq =3D vq; =20 - if (max_vq > sve_vq_from_vl(kvm_sve_max_vl)) + if (max_vq > sve_vq_from_vl(kvm_sve_get_max_vl(vcpu->kvm))) return -EINVAL; =20 /* diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index c18cdca7d125..7b8681a602d4 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -46,7 +46,7 @@ unsigned int __ro_after_init kvm_host_sve_max_vl; #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ PSR_AA32_I_BIT | PSR_AA32_F_BIT) =20 -unsigned int __ro_after_init kvm_sve_max_vl; +static unsigned int __ro_after_init kvm_sve_max_vl; =20 int __init kvm_arm_init_sve(void) { @@ -76,9 +76,17 @@ int __init kvm_arm_init_sve(void) return 0; } =20 +unsigned int kvm_sve_get_max_vl(struct kvm *kvm) +{ + if (kvm_is_realm(kvm)) + return kvm_realm_sve_max_vl(); + else + return kvm_sve_max_vl; +} + static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) { - vcpu->arch.sve_max_vl =3D kvm_sve_max_vl; + vcpu->arch.sve_max_vl =3D kvm_sve_get_max_vl(vcpu->kvm); =20 /* * Userspace can still customize the vector lengths by writing diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 6850338e2f19..cc618608f128 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -35,6 +35,12 @@ u32 kvm_rmm_ipa_limit(void) return u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_S2SZ); } =20 +unsigned int kvm_realm_sve_max_vl(void) +{ + return sve_vl_from_vq(u64_get_bits(rmi_feat_reg(0), + RMI_FEATURE_REGISTER_0_SVE_VL) + 1); +} + u64 kvm_realm_reset_id_aa64dfr0_el1(const struct kvm_vcpu *vcpu, u64 val) { u32 bps =3D u64_get_bits(rmi_feat_reg(0), RMI_FEATURE_REGISTER_0_NUM_BPS); --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 48F5E48C3F2; Wed, 15 Jul 2026 14:31:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125899; cv=none; b=dQUlAISmLivW8oRpz9AN0kBprziT2jG0rVj0r/2K6jaalUiCznCoR7rsSfd8n9tycDSzvYUCTyp9lHspORjBM9uCUAVdsFVmcoN4MiQa4r/Fxp3FUaDqEEkbsbvndgDjvG2uRHpLulyJQulgCYTSTLyoPoSlh52VKMEjaCUx9ek= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125899; c=relaxed/simple; bh=75s4kczD+dOim03oKcXS3tFt0Hj0gRBWP1mDhFZaKv4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sQsxxSYE2p5WXRHMQJunwA4/QhQZTSQcMO7KA6tJN3EVXhw9aKNLB7BhdhFzoQjcBQGYO2mkOa4xDBCfGT23TwfP4oHlKG3nHPqM3XAJlWu9JeLk8hiQrj39XGWBelpuEj8Pxr2b2O5xEhEsNa402F3d//KyYpNnF3bIhOs+6F4= ARC-Authentication-Results: i=1; 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ljCXfhJBU0qVumMsidJciB7PkCPOSuN2jrjkN6dcegv0uY+8+XDnfL8G+xxtrByAD +FgSJHz/XvL8wioAFDBdscnD7/sXU3X12W/jwqptiJMnq8+zUNF1VxcpP5mjgNIeYY FAZmYjpoWxavAEcnMg1Kohhg+fcDo9ZDLs0Th2F8= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 34/37] KVM: arm64: CCA: Configure max SVE vector length for a Realm Date: Wed, 15 Jul 2026 15:28:36 +0100 Message-ID: <20260715142841.80544-35-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker Obtain the max vector length configured by userspace on the vCPUs, and write it into the Realm parameters. By default the vCPU is configured with the max vector length reported by RMM, and userspace can reduce it with a write to KVM_REG_ARM64_SVE_VLS. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price --- Changes since v6: * Rename max_vl/realm_max_vl to vl/last_vl - there is nothing "maximum" about them, we're just checking that all realms have the same vector length --- arch/arm64/kvm/guest.c | 3 ++- arch/arm64/kvm/rmi.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index f48fc0d5a249..452cf5d3152e 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -361,7 +361,7 @@ static int set_sve_vls(struct kvm_vcpu *vcpu, const str= uct kvm_one_reg *reg) if (!vcpu_has_sve(vcpu)) return -ENOENT; =20 - if (kvm_arm_vcpu_sve_finalized(vcpu)) + if (kvm_arm_vcpu_sve_finalized(vcpu) || kvm_realm_is_created(vcpu->kvm)) return -EPERM; /* too late! */ =20 if (WARN_ON(vcpu->arch.sve_state)) @@ -754,6 +754,7 @@ static bool validate_realm_set_reg(struct kvm_vcpu *vcp= u, } else { switch (reg->id) { case KVM_REG_ARM_ID_AA64DFR0_EL1: + case KVM_REG_ARM64_SVE_VLS: return true; } } diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index cc618608f128..3f1c6351b71a 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -492,6 +492,39 @@ static void realm_unmap_shared_range(struct kvm *kvm, start, end); } =20 +static int realm_init_sve_param(struct kvm *kvm, struct realm_params *para= ms) +{ + unsigned long i; + struct kvm_vcpu *vcpu; + int vl, last_vl =3D -1; + + if (!kvm_has_sve(kvm)) + return 0; + + /* + * Get the preferred SVE configuration, set by userspace with the + * KVM_ARM_VCPU_SVE feature and KVM_REG_ARM64_SVE_VLS pseudo-register. + */ + kvm_for_each_vcpu(i, vcpu, kvm) { + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return -EINVAL; + + vl =3D vcpu->arch.sve_max_vl; + + /* We need all vCPUs to have the same SVE config */ + if (last_vl >=3D 0 && last_vl !=3D vl) + return -EINVAL; + + last_vl =3D vl; + } + + if (last_vl > 0) { + params->sve_vl =3D sve_vq_from_vl(last_vl) - 1; + params->flags0 |=3D RMI_REALM_PARAM_FLAG_SVE; + } + return 0; +} + static int realm_create_rd(struct kvm *kvm) { struct realm *realm =3D &kvm->arch.realm; @@ -539,6 +572,10 @@ static int realm_create_rd(struct kvm *kvm) if (kvm_lpa2_is_enabled()) params->flags0 |=3D RMI_REALM_PARAM_FLAG_LPA2; =20 + r =3D realm_init_sve_param(kvm, params); + if (r) + goto out_undelegate_tables; + params_phys =3D virt_to_phys(params); =20 if (rmi_realm_create(rd_phys, params_phys, realm->sro)) { --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E634A39184A; Wed, 15 Jul 2026 14:31:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125904; cv=none; b=L6criOewNEGg9AcMoNhZrWy7711dYe3IW7HQrWw6Q3y3yEJhTsDlSBdywE4Lrc6sU/HbLLAAqzkBhc6sA/1rOehmwTZ/vh60Ewq2HsujsgVouu65x5TddfIVCj5wAVuOfx8XYS4XkvzscmYWoAM0Zv2k0ukblmKrifwqvEZLDjo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125904; c=relaxed/simple; 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Wed, 15 Jul 2026 07:31:37 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE7573F7B4; Wed, 15 Jul 2026 07:31:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125901; bh=ZHXmGLH5TzpE00LEqay722W7AHFsS1ZBbuLYGDuFBAc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QYlHt8fBSqvoIFxcS6i1AC/I0WgIcQuCDengsZhEdhxlBnI1iFgf8U82bN61e0Kst Q4Y0sKtmpoacPuwRwBs3lEgE4byHDntWAThAxu2+UMk9yU9txVHRTOYBqNyRdpvY2t tff+a2NJf+RvjzwDhgewDGBPZbd6JiOgBAy+bBdg= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 35/37] KVM: arm64: CCA: Provide register list for unfinalized RECs Date: Wed, 15 Jul 2026 15:28:37 +0100 Message-ID: <20260715142841.80544-36-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker KVM_GET_REG_LIST should not be called before SVE is finalized. The ioctl handler currently returns -EPERM in this case. But because it uses kvm_arm_vcpu_is_finalized(), it now also rejects the call for unfinalized REC even though finalizing the REC can only be done late, after Realm descriptor creation. Move the check to copy_sve_reg_indices(). One adverse side effect of this change is that a KVM_GET_REG_LIST call that only probes for the array size will now succeed even if SVE is not finalized, but that seems harmless since the following KVM_GET_REG_LIST with the full array will fail. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price Reviewed-by: Gavin Shan --- arch/arm64/kvm/arm.c | 4 ---- arch/arm64/kvm/guest.c | 10 +++++----- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index aa7617e72e22..3862db30779f 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -1966,10 +1966,6 @@ long kvm_arch_vcpu_ioctl(struct file *filp, if (unlikely(!kvm_vcpu_initialized(vcpu))) break; =20 - r =3D -EPERM; - if (!kvm_arm_vcpu_is_finalized(vcpu)) - break; - r =3D -EFAULT; if (copy_from_user(®_list, user_list, sizeof(reg_list))) break; diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 452cf5d3152e..128fec56993a 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -617,8 +617,8 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) if (!vcpu_has_sve(vcpu)) return 0; =20 - /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return 1; /* KVM_REG_ARM64_SVE_VLS */ =20 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) + 1; /* KVM_REG_ARM64_SVE_VLS */ @@ -635,9 +635,6 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, if (!vcpu_has_sve(vcpu)) return 0; =20 - /* Policed by KVM_GET_REG_LIST: */ - WARN_ON(!kvm_arm_vcpu_sve_finalized(vcpu)); - /* * Enumerate this first, so that userspace can save/restore in * the order reported by KVM_GET_REG_LIST: @@ -647,6 +644,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, return -EFAULT; ++num_regs; =20 + if (!kvm_arm_vcpu_sve_finalized(vcpu)) + return num_regs; + for (i =3D 0; i < slices; i++) { for (n =3D 0; n < SVE_NUM_ZREGS; n++) { reg =3D KVM_REG_ARM64_SVE_ZREG(n, i); --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 94E494963C1; Wed, 15 Jul 2026 14:31:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125910; cv=none; b=dP4iCgBUV/peDaUzKhfSwb53F4I8TpsJubnRrxpNEhQzDaGF9/uZ5lGo9thknnn6tsHVktpWLIzRyuv9gyEWSWtDqk3NHNYWuuY0Ve7HuQs6y8EBkhT/Iu9vJE62TGc8TkhnTIMhtzdDxnVgtSxJr9B1gYJGwNmT9Q4kBaydGZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784125910; c=relaxed/simple; bh=R2faogoYaXkfqGHnF6vJJOqEqJmwTNS9i4WmOVnJpXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=b78mfoE16CUU1Jc8gH3w8HEBoOmMitMkruv3KRNNHWpUxORw6LzL9MwOtrBGz1N4X8dpfdDRyMFcLuWFGBWXQjDtWJHt7T7zGKRMCXnIWso/WgxB/CDBE201L7hg2ga4QAJp5W49urtHCnLT/dQy3rBUs8b8FIAu4P92+8I3+t8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=QdZarbfS; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="QdZarbfS" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B7B3915A1; Wed, 15 Jul 2026 07:31:41 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A83563F7B4; Wed, 15 Jul 2026 07:31:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125905; bh=R2faogoYaXkfqGHnF6vJJOqEqJmwTNS9i4WmOVnJpXU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QdZarbfSdc5lkye8g/rO8oqfaXwf8ScDp8caHxqwKFZ8INWULaG+6xkKtRgeak9pI Yiqf1IJP517QX6gci4s1cPvqpZK0n4+k+2sm/sZy8D79U4OEUQEhv8qsNkQxpTqh1B YnkZsMZBIkGGmBgzEDLsPAE9/ns1U2mahYMlgGHs= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Jean-Philippe Brucker , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi , Steven Price Subject: [PATCH v15 36/37] KVM: arm64: CCA: Provide an accurate register list Date: Wed, 15 Jul 2026 15:28:38 +0100 Message-ID: <20260715142841.80544-37-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jean-Philippe Brucker Userspace can set a few registers with KVM_SET_ONE_REG (9 GP registers at runtime, and 3 system registers during initialization). Update the register list returned by KVM_GET_REG_LIST. Signed-off-by: Jean-Philippe Brucker Signed-off-by: Steven Price --- Changes since v11: * Reworked due to upstream changes. Changes since v8: * Minor type changes following review. Changes since v7: * Reworked on upstream changes. --- arch/arm64/kvm/guest.c | 6 ++++++ arch/arm64/kvm/hypercalls.c | 4 ++-- arch/arm64/kvm/sys_regs.c | 27 +++++++++++++++++++++------ 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 128fec56993a..5e495dd39e39 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -620,6 +620,9 @@ static unsigned long num_sve_regs(const struct kvm_vcpu= *vcpu) if (!kvm_arm_vcpu_sve_finalized(vcpu)) return 1; /* KVM_REG_ARM64_SVE_VLS */ =20 + if (kvm_is_realm(vcpu->kvm)) + return 1; /* KVM_REG_ARM64_SVE_VLS */ + return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) + 1; /* KVM_REG_ARM64_SVE_VLS */ } @@ -647,6 +650,9 @@ static int copy_sve_reg_indices(const struct kvm_vcpu *= vcpu, if (!kvm_arm_vcpu_sve_finalized(vcpu)) return num_regs; =20 + if (kvm_is_realm(vcpu->kvm)) + return num_regs; + for (i =3D 0; i < slices; i++) { for (n =3D 0; n < SVE_NUM_ZREGS; n++) { reg =3D KVM_REG_ARM64_SVE_ZREG(n, i); diff --git a/arch/arm64/kvm/hypercalls.c b/arch/arm64/kvm/hypercalls.c index b11b8821c9fb..82278ccb19ae 100644 --- a/arch/arm64/kvm/hypercalls.c +++ b/arch/arm64/kvm/hypercalls.c @@ -414,14 +414,14 @@ void kvm_arm_teardown_hypercalls(struct kvm *kvm) =20 int kvm_arm_get_fw_num_regs(struct kvm_vcpu *vcpu) { - return ARRAY_SIZE(kvm_arm_fw_reg_ids); + return kvm_is_realm(vcpu->kvm) ? 0 : ARRAY_SIZE(kvm_arm_fw_reg_ids); } =20 int kvm_arm_copy_fw_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindice= s) { int i; =20 - for (i =3D 0; i < ARRAY_SIZE(kvm_arm_fw_reg_ids); i++) { + for (i =3D 0; i < kvm_arm_get_fw_num_regs(vcpu); i++) { if (put_user(kvm_arm_fw_reg_ids[i], uindices++)) return -EFAULT; } diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index e47be8f8d259..6d805160d70e 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -5540,18 +5540,18 @@ int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, = const struct kvm_one_reg *reg sys_reg_descs, ARRAY_SIZE(sys_reg_descs)); } =20 -static unsigned int num_demux_regs(void) +static inline unsigned int num_demux_regs(struct kvm_vcpu *vcpu) { - return CSSELR_MAX; + return kvm_is_realm(vcpu->kvm) ? 0 : CSSELR_MAX; } =20 -static int write_demux_regids(u64 __user *uindices) +static int write_demux_regids(struct kvm_vcpu *vcpu, u64 __user *uindices) { u64 val =3D KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX; unsigned int i; =20 val |=3D KVM_REG_ARM_DEMUX_ID_CCSIDR; - for (i =3D 0; i < CSSELR_MAX; i++) { + for (i =3D 0; i < num_demux_regs(vcpu); i++) { if (put_user(val | i, uindices)) return -EFAULT; uindices++; @@ -5595,11 +5595,26 @@ static bool copy_reg_to_user(const struct sys_reg_d= esc *reg, u64 __user **uind) return true; } =20 +static inline bool kvm_realm_sys_reg_hidden_user(const struct kvm_vcpu *vc= pu, + u64 reg) +{ + switch (reg) { + case SYS_ID_AA64DFR0_EL1: + case SYS_PMCR_EL0: + return false; + } + return true; +} + static int walk_one_sys_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, u64 __user **uind, unsigned int *total) { + if (vcpu_is_rec(vcpu) && + kvm_realm_sys_reg_hidden_user(vcpu, reg_to_encoding(rd))) + return 0; + /* * Ignore registers we trap but don't save, * and for which no custom user accessor is provided. @@ -5637,7 +5652,7 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 _= _user *uind) =20 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu) { - return num_demux_regs() + return num_demux_regs(vcpu) + walk_sys_regs(vcpu, (u64 __user *)NULL); } =20 @@ -5650,7 +5665,7 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcp= u, u64 __user *uindices) return err; uindices +=3D err; =20 - return write_demux_regids(uindices); + return write_demux_regids(vcpu, uindices); } =20 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \ --=20 2.43.0 From nobody Fri Jul 17 04:59:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 19F204A2E01; Wed, 15 Jul 2026 14:31:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="AR2vGpGk" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4133D1576; Wed, 15 Jul 2026 07:31:46 -0700 (PDT) Received: from e122027.cambridge.arm.com (e122027.cambridge.arm.com [10.1.25.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4B4FA3F7B4; Wed, 15 Jul 2026 07:31:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784125910; bh=hTHvGHo3aq13/0hCdni+YB/1LbAGuEZAjUd+4tZoURQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AR2vGpGk/pJKe3cSknWcS3UCEVyGMxAWtRMINXoVYuQ5KnoUiu3HircLCLB7+QqRS l3NnR1yUEHGBt1G8I6z0uTusataDJtdw1V5AnjVcCS7dcysd+dq64vL73OVK3VSJOu RelST7tzou4LH3wGD49r4zLAwVpDqy0yuTwKEPTQ= From: Steven Price To: kvm@vger.kernel.org, kvmarm@lists.linux.dev Cc: Steven Price , Catalin Marinas , Marc Zyngier , Will Deacon , James Morse , Oliver Upton , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Gouly , Alexandru Elisei , Christoffer Dall , Fuad Tabba , linux-coco@lists.linux.dev, Ganapatrao Kulkarni , Gavin Shan , Shanker Donthineni , Alper Gun , "Aneesh Kumar K . V" , Emi Kisanuki , Vishal Annapurve , WeiLin.Chang@arm.com, Lorenzo Pieralisi Subject: [PATCH v15 37/37] KVM: arm64: CCA: Enable realms to be created Date: Wed, 15 Jul 2026 15:28:39 +0100 Message-ID: <20260715142841.80544-38-steven.price@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715142841.80544-1-steven.price@arm.com> References: <20260715142841.80544-1-steven.price@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All the pieces are now in place, so enable kvm_rmi_is_available when the RMM is detected. Signed-off-by: Steven Price --- arch/arm64/kvm/rmi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/rmi.c b/arch/arm64/kvm/rmi.c index 3f1c6351b71a..06cc85fb5092 100644 --- a/arch/arm64/kvm/rmi.c +++ b/arch/arm64/kvm/rmi.c @@ -1518,5 +1518,6 @@ void kvm_init_rmi(void) if (rmm_check_features()) return; =20 - /* Future patch will enable static branch kvm_rmi_is_available */ + kvm_info("Realm guests supported\n"); + static_branch_enable(&kvm_rmi_is_available); } --=20 2.43.0