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Wed, 15 Jul 2026 04:01:23 -0700 (PDT) From: Hrushiraj Gandhi To: srini@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH 1/2] dt-bindings: nvmem: rockchip-efuse: add rockchip,efuse-write-enable property Date: Wed, 15 Jul 2026 16:31:06 +0530 Message-ID: <20260715110107.409204-2-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260715110107.409204-1-hrushirajg23@gmail.com> References: <20260715110107.409204-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an optional boolean property to explicitly opt in to write (OTP programming) support. eFuse bits are one-time-programmable and permanently set once written; write support must therefore not be enabled by default on arbitrary boards. Boards that intend to use software-initiated eFuse programming (e.g. factory key provisioning) must declare this property and must ensure the required VQPS programming supply (1.8V to 1.98V per RK3399 TRM) is present and correctly sequenced during writes. Signed-off-by: Hrushiraj Gandhi --- .../devicetree/bindings/nvmem/rockchip-efuse.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.yaml b/= Documentation/devicetree/bindings/nvmem/rockchip-efuse.yaml index b80fd8d1ae5b..8a7195245c84 100644 --- a/Documentation/devicetree/bindings/nvmem/rockchip-efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/rockchip-efuse.yaml @@ -46,6 +46,17 @@ properties: this property is defined. $ref: /schemas/types.yaml#/definitions/uint32 =20 + rockchip,efuse-write-enable: + type: boolean + description: + Enable write (programming) support for this eFuse block. eFuse bits + are one-time-programmable; setting a bit is permanent and cannot be + undone. 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Wed, 15 Jul 2026 04:01:29 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:6882:91b7:8e79:7958]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-6681fbd8c5esm59066d50.3.2026.07.15.04.01.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 04:01:29 -0700 (PDT) From: Hrushiraj Gandhi To: srini@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, heiko@sntech.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH 2/2] nvmem: rockchip-efuse: add write support for RK3399 Date: Wed, 15 Jul 2026 16:31:07 +0530 Message-ID: <20260715110107.409204-3-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260715110107.409204-1-hrushirajg23@gmail.com> References: <20260715110107.409204-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Implement rockchip_rk3399_efuse_write() using the Array Program Mode (A_PGM) as described in the RK3399 TRM. Each bit is programmed individually by asserting STROBE for 15us with the target bit address set in the EFUSE_CTRL register. Introduce struct rockchip_efuse_soc_data to hold both reg_read and reg_write callbacks per SoC, replacing the bare function pointer previously stored in of_device_id.data. Move nvmem_config to the probe stack so read_only can be set per-device based on whether a write callback is provided. Signed-off-by: Hrushiraj Gandhi --- drivers/nvmem/rockchip-efuse.c | 152 +++++++++++++++++++++++++++------ 1 file changed, 127 insertions(+), 25 deletions(-) diff --git a/drivers/nvmem/rockchip-efuse.c b/drivers/nvmem/rockchip-efuse.c index 013e67136f3b..19eb61380ea4 100644 --- a/drivers/nvmem/rockchip-efuse.c +++ b/drivers/nvmem/rockchip-efuse.c @@ -37,12 +37,16 @@ #define RK3399_NBYTES 4 #define RK3399_STROBSFTSEL BIT(9) #define RK3399_RSB BIT(7) +#define RK3399_PS BIT(4) #define RK3399_PD BIT(5) #define RK3399_PGENB BIT(3) #define RK3399_LOAD BIT(2) #define RK3399_STROBE BIT(1) #define RK3399_CSB BIT(0) +#define RK3399_PGM_TIME_US 15 + #define REG_EFUSE_CTRL 0x0000 #define REG_EFUSE_DOUT 0x0004 =20 @@ -52,6 +56,16 @@ struct rockchip_efuse_chip { struct clk *clk; }; =20 +/** + * struct rockchip_efuse_soc_data - per-SoC efuse callbacks + * @reg_read: mandatory read callback + * @reg_write: optional write callback; NULL means read-only + */ +struct rockchip_efuse_soc_data { + int (*reg_read)(void *ctx, unsigned int offset, void *val, size_t bytes); + int (*reg_write)(void *ctx, unsigned int offset, void *val, size_t bytes); +}; + static int rockchip_rk3288_efuse_read(void *context, unsigned int offset, void *val, size_t bytes) { @@ -177,6 +191,7 @@ static int rockchip_rk3399_efuse_read(void *context, un= signed int offset, writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB, efuse->base + REG_EFUSE_CTRL); udelay(1); + while (addr_len--) { writel(readl(efuse->base + REG_EFUSE_CTRL) | RK3399_STROBE | ((addr_start++ & RK3399_A_MASK) << RK3399_A_SHIFT), @@ -203,48 +218,120 @@ static int rockchip_rk3399_efuse_read(void *context,= unsigned int offset, return 0; } =20 -static struct nvmem_config econfig =3D { - .name =3D "rockchip-efuse", - .add_legacy_fixed_of_cells =3D true, - .type =3D NVMEM_TYPE_OTP, - .stride =3D 1, - .word_size =3D 1, - .read_only =3D true, +/** + * rockchip_rk3399_efuse_write - program fuse bits on RK3399 (A_PGM mode) + * @context: pointer to rockchip_efuse_chip + * @offset: byte offset in the efuse space + * @val: data to write (only set bits are programmed; OTP cannot clear) + * @bytes: number of bytes + * + * Each bit is programmed individually using a hardware-timed STROBE pulse. + * The caller must ensure VQPS (1.8V~1.98V) is present during the write. + * Per TRM Section 21.6, only one bit is programmed per STROBE cycle. + */ +static int rockchip_rk3399_efuse_write(void *context, unsigned int offset, + void *val, size_t bytes) +{ + struct rockchip_efuse_chip *efuse =3D context; + u8 *buf =3D val; + int ret; + + ret =3D clk_prepare_enable(efuse->clk); + if (ret < 0) { + dev_err(efuse->dev, "failed to prepare/enable efuse clk\n"); + return ret; + } + + while (bytes--) { + u8 byte =3D *buf++; + int bit; + + for (bit =3D 0; bit < 8; bit++) { + u32 addr, ctrl; + + if (!(byte & BIT(bit))) + continue; + + addr =3D offset * 8 + bit; + + /* + * A_PGM mode (TRM table 23-3): + * CSB=3DL, PGENB=3DL, PS=3DH, PD=3DL, LOAD=3DL, RSB=3DL, + * STROBSFTSEL=3DH (software controls STROBE) + * STROBE is asserted separately below. + */ + ctrl =3D RK3399_STROBSFTSEL | RK3399_PS | + ((addr & RK3399_A_MASK) << RK3399_A_SHIFT); + + writel(ctrl, efuse->base + REG_EFUSE_CTRL); + udelay(1); + + writel(ctrl | RK3399_STROBE, efuse->base + REG_EFUSE_CTRL); + udelay(RK3399_PGM_TIME_US); + + writel(ctrl, efuse->base + REG_EFUSE_CTRL); + udelay(1); + } + + offset++; + } + + /* Return to standby mode: PD=3DH, CSB=3DH */ + writel(RK3399_PD | RK3399_CSB, efuse->base + REG_EFUSE_CTRL); + + clk_disable_unprepare(efuse->clk); + + return 0; +} + +static const struct rockchip_efuse_soc_data rk3288_efuse_data =3D { + .reg_read =3D rockchip_rk3288_efuse_read, +}; + +static const struct rockchip_efuse_soc_data rk3328_efuse_data =3D { + .reg_read =3D rockchip_rk3328_efuse_read, +}; + +static const struct rockchip_efuse_soc_data rk3399_efuse_data =3D { + .reg_read =3D rockchip_rk3399_efuse_read, + .reg_write =3D rockchip_rk3399_efuse_write, }; =20 static const struct of_device_id rockchip_efuse_match[] =3D { /* deprecated but kept around for dts binding compatibility */ { .compatible =3D "rockchip,rockchip-efuse", - .data =3D (void *)&rockchip_rk3288_efuse_read, + .data =3D &rk3288_efuse_data, }, { .compatible =3D "rockchip,rk3066a-efuse", - .data =3D (void *)&rockchip_rk3288_efuse_read, + .data =3D &rk3288_efuse_data, }, { .compatible =3D "rockchip,rk3188-efuse", - .data =3D (void *)&rockchip_rk3288_efuse_read, + .data =3D &rk3288_efuse_data, }, { .compatible =3D "rockchip,rk3228-efuse", - .data =3D (void *)&rockchip_rk3288_efuse_read, + .data =3D &rk3288_efuse_data, }, { .compatible =3D "rockchip,rk3288-efuse", - .data =3D (void *)&rockchip_rk3288_efuse_read, + .data =3D &rk3288_efuse_data, }, { .compatible =3D "rockchip,rk3368-efuse", - .data =3D (void *)&rockchip_rk3288_efuse_read, + .data =3D &rk3288_efuse_data, }, { .compatible =3D "rockchip,rk3328-efuse", - .data =3D (void *)&rockchip_rk3328_efuse_read, + .data =3D &rk3328_efuse_data, }, { .compatible =3D "rockchip,rk3399-efuse", - .data =3D (void *)&rockchip_rk3399_efuse_read, + .data =3D &rk3399_efuse_data, }, { /* sentinel */}, }; @@ -252,20 +339,26 @@ MODULE_DEVICE_TABLE(of, rockchip_efuse_match); =20 static int rockchip_efuse_probe(struct platform_device *pdev) { - struct resource *res; - struct nvmem_device *nvmem; + const struct rockchip_efuse_soc_data *soc_data; struct rockchip_efuse_chip *efuse; - const void *data; + struct nvmem_device *nvmem; + struct nvmem_config econfig =3D { + .name =3D "rockchip-efuse", + .add_legacy_fixed_of_cells =3D true, + .type =3D NVMEM_TYPE_OTP, + .stride =3D 1, + .word_size =3D 1, + }; + struct resource *res; struct device *dev =3D &pdev->dev; =20 - data =3D of_device_get_match_data(dev); - if (!data) { + soc_data =3D of_device_get_match_data(dev); + if (!soc_data) { dev_err(dev, "failed to get match data\n"); return -EINVAL; } =20 - efuse =3D devm_kzalloc(dev, sizeof(struct rockchip_efuse_chip), - GFP_KERNEL); + efuse =3D devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL); if (!efuse) return -ENOMEM; =20 @@ -278,12 +371,20 @@ static int rockchip_efuse_probe(struct platform_devic= e *pdev) return PTR_ERR(efuse->clk); =20 efuse->dev =3D dev; + if (of_property_read_u32(dev->of_node, "rockchip,efuse-size", &econfig.size)) econfig.size =3D resource_size(res); - econfig.reg_read =3D data; - econfig.priv =3D efuse; - econfig.dev =3D efuse->dev; + + econfig.reg_read =3D soc_data->reg_read; + if (soc_data->reg_write && + of_property_read_bool(dev->of_node, "rockchip,efuse-write-enable")) + econfig.reg_write =3D soc_data->reg_write; + + econfig.read_only =3D !econfig.reg_write; + econfig.priv =3D efuse; + econfig.dev =3D dev; + nvmem =3D devm_nvmem_register(dev, &econfig); =20 return PTR_ERR_OR_ZERO(nvmem); @@ -300,3 +401,4 @@ static struct platform_driver rockchip_efuse_driver =3D= { module_platform_driver(rockchip_efuse_driver); MODULE_DESCRIPTION("rockchip_efuse driver"); MODULE_LICENSE("GPL v2"); + --=20 2.47.3