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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:13 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Conor Dooley , Alexandre Torgue , Christophe Parant , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 01/16] dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board Date: Wed, 15 Jul 2026 08:20:18 +0200 Message-ID: <20260715062201.3599458-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for Engicam MicroGEA-STM32MP257-RMM board based on the Engicam MicroGEA-STM32MP257 SoM (System-on-Module). The use of an enum for a single element is justified by the future addition of other boards based on the same SoM. Signed-off-by: Dario Binacchi Acked-by: Conor Dooley --- (no changes since v2) Changes in v2: - Add Acked-by of Conor Dooley for patch 0/1 "dt-bindings: arm: stm32: support Engicam MicroGEA-STM32MP257-RMM board" Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index c6af3a46364f..c5ce81e3ce45 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -203,6 +203,13 @@ properties: - st,stm32mp257f-ev1 - const: st,stm32mp257 =20 + - description: Engicam MicroGEA STM32MP257 SoM based Boards + items: + - enum: + - engicam,microgea-stm32mp257-rmm + - const: engicam,microgea-stm32mp257 + - const: st,stm32mp257 + - description: ST STM32MP235 based Boards items: - enum: --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ed1-f52.google.com (mail-ed1-f52.google.com [209.85.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEF5131DDBF for ; Wed, 15 Jul 2026 06:22:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096539; cv=none; b=hKQzh6DbzFALxi2ysmuKmHDILvrgWWmSndHwrM5Q3WeWuZu4NzoeDmUC/q7rn55y8Kz/ucDNzN25cvOJLS1kfQ3z7viUVyg/obAZWffL0iAv/N3fO5ofM38KsDW6MoSwhAl8C+VfUJvY+cZvGqZ92ozp/RJznRvNsiGN+ihvqhY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096539; c=relaxed/simple; bh=r4oEtWAGk+0lG2cjCCS/On9c5o0ItK6TwayM08X4LmQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qF6wTS7DD9hLKvsIkoE+Hg925hLwKgpAVWZF40jgKuGKmm5cziWQC7urWmSmHFnkBEec5j+WcDuSOTPl6ICvvy1BmAbE1YE7N8ovy0nRw3zK5HWg6We0dmBC8oq9EFKG1pI3RG/SCizMGTxkBvHKiE3JOZwpJxR2d7XN5ChTcDM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=fQ4T0ZMb; arc=none smtp.client-ip=209.85.208.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fQ4T0ZMb" Received: by mail-ed1-f52.google.com with SMTP id 4fb4d7f45d1cf-698ab9aae16so138977a12.3 for ; Tue, 14 Jul 2026 23:22:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1784096536; x=1784701336; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=G5wRK8UQUntkfKxBkcuhYJT69Pdd0Q05Ua1EKGESaNA=; b=fQ4T0ZMbscHo9jcNZ+EGT5/VN+tVa4+Y5DPCwgNG9A5e2eQFjon/8m2O+MCvqIXzKH 5Ta3Uwj6jePejvfGf4LPpgOjo396x44xG06XQVdJVS7pVum3hPkZe+kJnteFGjvAPcYV Bk379G/JJlsGOqy4YHsOl/mkNByR9PLk5MRHQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784096536; x=1784701336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=G5wRK8UQUntkfKxBkcuhYJT69Pdd0Q05Ua1EKGESaNA=; b=Hx7sz0faROVmfXVyaXb4JMDYdg2cw7zgVLxxzjDk3tPx/ger+PKYHR2n49pIrihwhq kTlk7uOpE/zTjqvjYBUY1fX4Uhl+/24JuTBkK9E2ggVLVzZitnfa+5VH9Y0ICHy2W1pt G3sSGPYKOITFl12Igp2qlQBfol4q3bsMm86YTcSxHq6NySafbPL4iB3xgi4ZNoDBLJXX h0u1M+zARp7g+B/NMyipl7v0egIxCJ4caFl1SElUtAC4i261k+jJ+C1gz6VRD9OZ3iEl 7EpWfCSuOsrU2GPEEH++LBHz9sGj68pPbsTmJWrGwlyN3vwdil5YzmaKZkmnzOgXmr/K tQTA== X-Gm-Message-State: AOJu0YzIyPanzDPwkArI9Ho4hrcPa7KvVDLDMfCd19TA+cBf9QoftVPG EczOBTgvTl/0bYSk/klU6lZ8WSj2U4hzCHPlfw3IRULtSneuoQgW9x4wwUXg6PgtLdPb6LwG89H wxzG6Esk= X-Gm-Gg: AfdE7cmbCm1DzF4GRZRMT2UljHqHOnaZKOfQdfYTjMRMixcGe17fe4Ilaj4g0DBrZ2Q rRzOT9joQsqvQph8R5cikYazGBPyjwZhm4cwwhaPvbBDt+ryMTCUN6Bv3WUywO4owUSiZkLfjyu FG8yEdHbnRzfv+H3wDRGSH39XnpO00dkbJd6yADL+nlAEZY9QfdsDIFX2JyLuaCYxBwLRV03gMr QuYll4YVMlh1fhsG0aSPoxSpSFC9wDiIwUDRMChs+JBBQnCVkmm7wv66ziDLXZ6nbOGmlfqNySs st84SXNtrqV9XZamfIUwpCQdvu/oVfnnLasitmGKLoOaxh4PZiwPf74P6ywu7/ues7JjXymHYGs DpvXHckvYBsiJtC+afL7tkAws0b72zwURtg8EBROvKBIrQNnTUhm5Dqgx37Gcbfy43+28Cn0VdU qwXD9D3E4Iqr+akscqw8fnX78H9O+jzCJy7ctLb91eZKmrj3HEuG+IagAtoHixK0rtMuFXSTQ7r TpCL6kqsNJT X-Received: by 2002:a17:907:8b99:b0:c16:3187:997c with SMTP id a640c23a62f3a-c163187a0e0mr757455766b.1.1784096536252; Tue, 14 Jul 2026 23:22:16 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:15 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 02/16] arm64: dts: st: add power-domains to sdmmc1 on stm32mp231 Date: Wed, 15 Jul 2026 08:20:19 +0200 Message-ID: <20260715062201.3599458-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sdmmc1 node was introduced early in the SoC bring-up before power domains were systematically mapped. Add the missing power-domains property to align it with the rest of the peripheral nodes. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Added in version 5. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp231.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/s= t/stm32mp231.dtsi index 9e1d240888ff..0feb8943efae 100644 --- a/arch/arm64/boot/dts/st/stm32mp231.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi @@ -727,6 +727,7 @@ sdmmc1: mmc@48220000 { cap-mmc-highspeed; max-frequency =3D <120000000>; access-controllers =3D <&rifsc 76>; + power-domains =3D <&cluster_pd>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f46.google.com (mail-ej1-f46.google.com [209.85.218.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 524B13264DD for ; Wed, 15 Jul 2026 06:22:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096541; cv=none; b=Z2z5WP5u480S8PPzVPN5RH0k+yw0A1qHQmmg8cAL60tiEUmxpn5+BkKpbfa9DxC7qmYKZweP1vWoUG8o986Lp2RDiil5bGdB0IwQfBpRDqL4zSkPnbp5m6e23RXnXXafJ06i+i+JcPMyPPdJO+QQvRDRm+g/uNM36thGvct6j2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096541; c=relaxed/simple; bh=SRq4aV3Vv1KtanwaZu/HUbm5QTW8rISjxiq71Wm2JKY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fEgWv2amMJ0YfhAo0EW9laMpE09TW4J9hyJTbP6gXQ7JiZodk9qO+JlPGVm80QzKoUb5bcKxAxZq3qRv9uyQE+998DsZB+69yBXS+kpcB552Eh80/mwZUg3XMDJzCRaPzD7US5LMsn0fRLEJedpkDys3MViNG5guAmEEeesJy78= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=QCub6Qf+; arc=none smtp.client-ip=209.85.218.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="QCub6Qf+" Received: by mail-ej1-f46.google.com with SMTP id a640c23a62f3a-c15ba3a2b4bso585692666b.1 for ; Tue, 14 Jul 2026 23:22:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1784096538; x=1784701338; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=kjf+9zwLvFnbMj2uY67jnA57NYs5qvgfofKcphxJQbw=; b=QCub6Qf+MgAgUN8YEkiJsAGCdSbQOERO9GT8YsSf1WFstWVlPeDSr1d85CeKaFAvlY KzFIE9BU4ap43PjAPXPjobmNzFj4ENp2gvdCjdR1uP3FtEmdpfnWwptoEed7By23Epl2 HSWVrlqnWDHC0j947kJ4O4S5CiCsS/E/X/3CI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784096538; x=1784701338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=kjf+9zwLvFnbMj2uY67jnA57NYs5qvgfofKcphxJQbw=; b=DK4BMO1w2Z9PIRKH58vc57qkjE9LP6RGwdTQsnXpHhG0a/jKhSzD3S7Xl3zl3da8PZ W8nka0xWVN6Ko1tX3eu0RoO/uC5KtQwD56/tSw1MVMYKjhzpGZmnLqc9esHjidiP2Bxq Oqsz2ZageKxBZXxA5bXVKMZkrdg8WIUuqodMLFpoqY19XIDNKfPHU8Ma9o2ZJKfPQlIE wteNRmc/ROndTyd0Mc00JxjAZiHBOBCBiyiFHTYzWtBhazcixJWRMTD9TDQsk5q7TcOo iuK0vt2d3rEFCt2veSTAdCR6R7vw6O+jiRTKxyaDZXIyLU8yCILcQf0xzbj5dIcWqITy mXZQ== X-Gm-Message-State: AOJu0YyULYnBCPZ0hwWX2gLljXkpg6c4tXpXEn3f44hwtTPoR1JMSf22 WCA0hYy+m6Krex70OXg0/PabS85ZIukYhLSpqqkIKgE4qY0E/CUlg+JAEcVkmAQkp1VDohtejUX lXiruLLY= X-Gm-Gg: AfdE7clclw+OS+T4Yu0ah5Y6phq/2Ynwv1dU0NvS7oLAZncTebE6bKL5LAnit85F92E 0vfkqAPTJzRHyWDOk+NcuoB8kXWDKSpTgN/+bAwM1sXDz0Ys7luiOpvGcMHGQhQtosY1YlkI3YT Qwjhb32BfWnNwJEI5rcKajmNr7ZfB/sfEVmbma8kONMv3jrALZCpxxLSwqnRMflUJu/ueyeqsS8 QbpjCF3pFyYdTB7rdzQCEEseVbPHHNjOQH8QZgntLlfNW3bvcY4Xn/sQnIklhDEaX0C2poED+1U 6CQ+m/W2RsTYBi68EzA5unt/x5YORDj7iECcKwOIAVE3ahV+Fv9KOE6b/ZbtV/qvkdP9Sqbv8rt bvEcyHXBTIfIExS8RIBUk5+mGLwYQ13SXi55NdMMViVK1JlHZ0H3a7P7STIOZW4L5lIyV1CtI1r xwLRBM9rA6bmN7K0HXLoRC58DJ5SxTR+hcZJyL0JIRhUHxhyMwuzQjlw81LtG/rbNT6v901xCGz xX5alI8q6Cs8mmXPwUJvNw= X-Received: by 2002:a17:907:7292:b0:c15:ee0d:9a32 with SMTP id a640c23a62f3a-c1661680353mr381793666b.21.1784096538053; Tue, 14 Jul 2026 23:22:18 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:17 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 03/16] arm64: dts: st: add power-domains to sdmmc1 on stm32mp251 Date: Wed, 15 Jul 2026 08:20:20 +0200 Message-ID: <20260715062201.3599458-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The sdmmc1 node was introduced early in the SoC bring-up before power domains were systematically mapped. Add the missing power-domains property to align it with the rest of the peripheral nodes. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Added in version 5. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 9c63fdb5a885..ae36d703532c 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1664,6 +1664,7 @@ sdmmc1: mmc@48220000 { cap-mmc-highspeed; max-frequency =3D <120000000>; access-controllers =3D <&rifsc 76>; + power-domains =3D <&CLUSTER_PD>; status =3D "disabled"; }; =20 --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22E1532AAAB for ; Wed, 15 Jul 2026 06:22:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096543; cv=none; b=EQ+X8LmomAUBjUR+yxAlZr5covn3+sZz7smbHWH5Rd/NEB0bRLoPnt7n1DaqAsmSWDqsaZvHXFtIFlWd3sMn4UiNAoepVMypl8Sr0meMdKkaFola0lrFZNVpNw6O3UFTzb/jeYsz16jsRHzVZK8Ckq5qWxD8XsiR1R49zSIiHyw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096543; c=relaxed/simple; bh=9IgDtyv6yAMUkWsg7RNaWcItxtFHo8kakpm/KHcWfnA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QmKMplRcQeJnB1JfzK+kyGDRwg1rpZUXNH0Cp7KwF5DM+BqwJ565PLa6CUaPGUEBCphgHAbwKJjvGg34IcSJqaeogcqooc96EA3LQN9XxPmUTuQMevsVmEhbf7UNNHYxkk8PXrTFKfw2yOkUwnnUe50rYTCUT20rJNIVoIuh4Ms= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=fWZCAdMT; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fWZCAdMT" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-69c20ba892eso432471a12.1 for ; Tue, 14 Jul 2026 23:22:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1784096540; x=1784701340; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=fAmctwTyX9ptfNTsOcFrY+BzuI2WSByIHEJFFIRpN/Y=; b=fWZCAdMTqsgP86Xig/vy/2+qiTD0J8yDEJZPjnDKijqmDDiS5XWimcyw95d8OpJEMa zd5MqmZwAD0KLc0pJ9OuFR4wklWa2qY+rmhkLYLCocq3zWXBDnnIwhEveNgSdKdV5kPn 2ixFxqQEeMqGnf1R4F5zmFGjLxxk4/zcBUsRQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784096540; x=1784701340; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=fAmctwTyX9ptfNTsOcFrY+BzuI2WSByIHEJFFIRpN/Y=; b=XoVMh4tiFz9WrGXS3QI8roulxVu5chYzFDo9HTQsDQIsngaUeHimD8ldy85imqNN+V LNJWL9FCV+J7kEPjAHD9uNsogahvYSV2ltocikjy5spZoFBYQ4q3FZkZwhBFrgDtPAZb NF98DqeQF662PPVpMXFGKlW2WOB8R/7K59Jj2zAkTmsDaHFufz77e81OzKzD8MrTjuTY wHnQgLhrHCbglbKw5b3S4Fttyi/0tBBhT00UNes9+TkhZD2U6J9XeyK6kF0gh1F3NADG 48JJImcqUFNXLFK9OPK3fh934FRzuWEjnesGUGbGT6G0GfI6W4oiciN7IS7PoSP8gD/K YBKw== X-Gm-Message-State: AOJu0YzU28Tw4H9LQ0dKfQDPtWHVMmmLyAoIkjp2BtJV2vNPSUfdVATS u65hNd1XVqxkAx6t6E0SmzDkZp4i9mXwlAlYlIROOtH9Ll+6hsfElmjo0DdeWaEDQd7WbO7VlM8 1sRL77pQ= X-Gm-Gg: AfdE7cmq0KPRI4ER7iVqARVmeC2MmLo0hFPBtoje+muLPxE2oeHXjty8dzoXNj5/tdd mEWey5WjksGmXZzZXrAyz8SXtHr5kU2nJs58MklqJkR5KGO3Z+WhUiZnDSXgyA1I2jY9bt+fhvn U/OulR0pdD3FikAJQZUvO5IkBcdfR0hC2HRPHB0U2eKsAc+Ky2jb9ODaZ8BY+0MNiY5lZew74/z I2VU7/SQvCapozw0jgVnc3TTgGgnNZ2F0yJLOIel7dDAf304LRmJwrgqm5fJZ+8VbXZXAc5xARB /Kx99J0Vlh45CqlbHip4XTXJbJDFaXJx/9Iuii6NsrNwZwdyoq5/qhq4XK7z+zgDLJRwyGgLohy AMmGrdrIpyLe98XTieqF6RzM3pAyMnUmMuqaCdCmPUTTYNBVgmj6imi8aaq1500ec7Q793kuPJ2 L8r28FUzw+wLjZtUHzuXaGJ6IZ+ZUx3ycXbTvJVsxZ2AFc5UsOF115zrnrQYd7Q/yhj7O6i3zoh K3x0/LlUN5J X-Received: by 2002:a17:907:3d49:b0:c16:7d95:9f48 with SMTP id a640c23a62f3a-c167da4e50fmr40843966b.14.1784096539997; Tue, 14 Jul 2026 23:22:19 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:19 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 04/16] arm64: dts: st: add SDMMC2 support on stm32mp25 Date: Wed, 15 Jul 2026 08:20:21 +0200 Message-ID: <20260715062201.3599458-5-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SDMMC2 controller supports SD cards, eMMC memories and SDIO devices. Signed-off-by: Dario Binacchi --- (no changes since v3) Changes in v3: - Add power-domains property. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp251.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index ae36d703532c..44938c036e30 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1668,6 +1668,22 @@ sdmmc1: mmc@48220000 { status =3D "disabled"; }; =20 + sdmmc2: mmc@48230000 { + compatible =3D "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + arm,primecell-periphid =3D <0x00353180>; + reg =3D <0x48230000 0x400>, <0x44230800 0x8>; + interrupts =3D ; + clocks =3D <&rcc CK_KER_SDMMC2>; + clock-names =3D "apb_pclk"; + resets =3D <&rcc SDMMC2_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency =3D <120000000>; + access-controllers =3D <&rifsc 77>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet1: ethernet@482c0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482c0000 0x4000>; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:21 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 05/16] arm64: dts: st: add CAN1 support on stm32mp25 Date: Wed, 15 Jul 2026 08:20:22 +0200 Message-ID: <20260715062201.3599458-6-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The controller is compliant with ISO 11898-1: 2015 (CAN protocol specification version 2.0 part A, B) and CAN FD protocol specification version 1.0. Signed-off-by: Dario Binacchi --- (no changes since v2) Changes in v2: - Add resets property to dts CAN node. Suggested by Sashiko. arch/arm64/boot/dts/st/stm32mp253.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/s= t/stm32mp253.dtsi index eeceb086252b..7e82f01fdc10 100644 --- a/arch/arm64/boot/dts/st/stm32mp253.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi @@ -43,6 +43,22 @@ &optee { }; =20 &rifsc { + m_can1: can@402d0000 { + compatible =3D "bosch,m_can"; + reg =3D <0x402d0000 0x400>, <0x40310000 0xd50>; + reg-names =3D "m_can", "message_ram"; + interrupts =3D , + ; + interrupt-names =3D "int0", "int1"; + clocks =3D <&rcc CK_BUS_FDCAN>, <&rcc CK_KER_FDCAN>; + clock-names =3D "hclk", "cclk"; + resets =3D <&rcc FDCAN_R>; + bosch,mram-cfg =3D <0x0 0 0 32 0 0 2 2>; + access-controllers =3D <&rifsc 56>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + ethernet2: ethernet@482d0000 { compatible =3D "st,stm32mp25-dwmac", "snps,dwmac-5.20"; reg =3D <0x482d0000 0x4000>; --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10ABD331202 for ; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:23 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 06/16] arm64: dts: st: add i2c1 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:23 +0200 Message-ID: <20260715062201.3599458-7-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the i2c1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 456ece7f8ebc..db485b9ed904 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -203,6 +203,25 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2c1_pins_a: i2c1-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3063F3164C7 for ; Wed, 15 Jul 2026 06:22:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096549; cv=none; b=uU8b7B984WO/Td1bn3FlFW3BW32sHAECfH98C4MAG/mzv8VfZ3Ck6V0EoAutwSiS1Lc00l1DXWv3aA1iJgat/WKcULT76K2gz9GSNDqtHHHnoxvhRrbgGzvIV3pKLa5kQPdZdJZGxrqnvdPWIJEHztuZjpZL1ZHMxTOt8+BEo94= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096549; c=relaxed/simple; bh=G0RotCdUQw1WugxF+88UN4SxQ5ZKhA/qabP0Le2jF1o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QZwJgmf69fDFQOLw9KS8eA7U31LyBZGnP7k4X40G56S//TcmoTFN0LNAxOL38Sn/RgEQx4oAIvfwGopztQyrV47NUXu324G1J26T1HOJPxqIYfYW/z60UwHvXvHX2YUc8o1Oh2ze7S6Vmioyohg7DtCy4FhEAacygDDFYDRrHWA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=Dg3v1xUD; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="Dg3v1xUD" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-c1601d552a8so525800466b.2 for ; Tue, 14 Jul 2026 23:22:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1784096546; x=1784701346; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=10sYi/tVtIvvMUUKo7OG02Z+QG9MfHpevI/v5pXPRvs=; b=Dg3v1xUDGGc0Qpg7Sum4bbQnuLHrcXBwnLJ+yFHRvVjtfzKXWgaihpTwWS7ncW/ErP jrShBZlaCwglfNvAXPAA78BVk8KtIn7EXU5KuXtoheiGkX/YHPVwrTrVk+lLh1AqsOam g3ZRfavdNZ+nMmVkh3B9ixjLsOw+6f9dMpfz4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784096546; x=1784701346; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=10sYi/tVtIvvMUUKo7OG02Z+QG9MfHpevI/v5pXPRvs=; b=lUBLB7q2wT7bC4tpNsaopIMzrcW/4ZEh2QGMCHbWgbd9rM8Mkf9ioTN/3A0J0bPtGt KNaL5F78zZWpFMgY14SNDmaKs97lTgzAdk6sgQzZiY32F2wsax3KYfxxRxEJu5Cd4rUq 1nJ7n1cl2GujlxM55/h0QXjsreodbAjgfhvNE44znqxsneMLE4vfpYVB0baE9Dzvplx1 jytXtgq+GY/O3RDezLw/MFqAql3k55EuWfINUhUl7SiGI+RR+9XDycMbvjBmP4oEDBJ+ fDxdegvKwQFmY+40elgiVHKcywCLNyQB4riehXpomVWL4RCtZSgUbrN+t5vLw630QtWP IL3Q== X-Gm-Message-State: AOJu0Yz52sy5nGhxs09LAPWDvpKYzfe39RW6URL6HEGj1+ho2ChrW8u9 I5arNsWhlAQVzHFSIQgu39QsJwV9CMY7fhRFgYWitnsOMIJOAAxQhtoaGvqcCGHbIYy9q8NDyft ECCuadQo= X-Gm-Gg: AfdE7cnsCPcUy+Zo7a3mmRiUX6D89H0KYJs/6fFzT+cF8guEzWLBBt/GBWDif0haxMp k8Ll2957f+mJSHdjCVVA5tkBFSU2GjREli5gmwp71dRuwcy9TcT2n29+PZVfD5ApLGSlTTZsDUR T3i1kEa2QBuYdbY3LmU7saTFJNpU9PLMTnHkEEwmRzocT6i2dmTBhyjvoV5ondU9soySC1x7NR6 2BoVQv1mUUNNJ7M2Il4nQs7mp76LigQikHqEhbaZV3WQ6Ey6rYgQhNIZTGSK0gnl6WLK0nMPpTl nenINpFw8ML3A7qmHhiglWxa47bYk1Kb30n3i6+8TP4PpttZH7rJ4V0FA0R3hbcuP1w9HWUpOpz 65ShCLXnAMeIaRvCtKxciaPhkZK058z9Ld98y5JqZ3WBf42/1nmhx8Y65tEwfQX0LOrBqPiasWU T5jlJCYfyJxCdSZVBGpmzweh05qzCMimGpxEvb37CKhjWFRduqfKQ+TL50jJuZ0akVQgIQnjp0B AVgXQmzowGO X-Received: by 2002:a17:907:6d02:b0:c16:12ff:dc93 with SMTP id a640c23a62f3a-c16679d7da0mr313911766b.18.1784096546357; Tue, 14 Jul 2026 23:22:26 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:25 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 07/16] arm64: dts: st: add ltdc pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:24 +0200 Message-ID: <20260715062201.3599458-8-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the LTDC pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Increase slew-rate to <1> to support the 27 MHz pixel clock and prevent timing violations. Suggested by Sashiko arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index db485b9ed904..50f454630cf2 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -260,6 +260,77 @@ pins { }; }; =20 + /omit-if-no-ref/ + ltdc_pins_a: ltdc-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + }; + + /omit-if-no-ref/ + ltdc_sleep_pins_a: ltdc-sleep-0 { + pins { + pinmux =3D , /* LCD_CLK */ + , /* LCD_HSYNC */ + , /* LCD_VSYNC */ + , /* LCD_DE */ + , /* LCD_R0 */ + , /* LCD_R1 */ + , /* LCD_R2 */ + , /* LCD_R3 */ + , /* LCD_R4 */ + , /* LCD_R5 */ + , /* LCD_R6 */ + , /* LCD_R7 */ + , /* LCD_G0 */ + , /* LCD_G1 */ + , /* LCD_G2 */ + , /* LCD_G3 */ + , /* LCD_G4 */ + , /* LCD_G5 */ + , /* LCD_G6 */ + , /* LCD_G7 */ + , /* LCD_B0 */ + , /* LCD_B1 */ + , /* LCD_B2 */ + , /* LCD_B3 */ + , /* LCD_B4 */ + , /* LCD_B5 */ + , /* LCD_B6 */ + ; /* LCD_B7 */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 52ADA331202 for ; Wed, 15 Jul 2026 06:22:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:27 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 08/16] arm64: dts: st: add can1 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:25 +0200 Message-ID: <20260715062201.3599458-9-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the can1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 50f454630cf2..6482dd47e977 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -331,6 +331,28 @@ pins { }; }; =20 + /omit-if-no-ref/ + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux =3D ; /* CAN1_TX */ + slew-rate =3D <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux =3D ; /* CAN1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can1_sleep_pins_a: m-can1-sleep-0 { + pins { + pinmux =3D , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + /omit-if-no-ref/ ospi_port1_clk_pins_a: ospi-port1-clk-0 { pins { --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ed1-f46.google.com (mail-ed1-f46.google.com [209.85.208.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88DCA337BAC for ; Wed, 15 Jul 2026 06:22:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096554; cv=none; b=HbJMD1vtWTf8b9WyTvkqGdmY4tMkF0uDnjGchNY5NPPP98/vc9zRZO0XKODi8Us6eKX8BRo9+G0aT0rI9f6MwevBNmY5MhmqgH3S4DB4OIzFGcSvWBzngdT0Hu//voUnwa/A14J+tzsUtumj9edlGNfD/WZR154A2l1DtyD/niM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096554; c=relaxed/simple; bh=QGlJqg03ZdMuDaIsMrA23hhc5s89rjWq4ym3XRlGfDY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ealM1mY/YAytooPVMdorhNAuCr8M2FQoa+BsFQYG/mqF2LF+a+ZB8QYalKSj+RgPDrqX7VGeOWr1KZw1266Qk8DOqPAIMl/AusNv60gcWZzJDSke8jRx66tqKmdHpb4Q2ro8GBnr0NA8coGhzpqj7dumL92OZN3ovovPum3xPCU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=bjLuXSet; arc=none smtp.client-ip=209.85.208.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="bjLuXSet" Received: by mail-ed1-f46.google.com with SMTP id 4fb4d7f45d1cf-69a5ecbbfb2so2890500a12.2 for ; Tue, 14 Jul 2026 23:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1784096551; x=1784701351; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Y9eicy7qFkVmMZW611/qMDh6GaEBG59Bdrl7IT5yIvE=; b=bjLuXSetGv7LWUeXH+GOp5rKXdFfDpocrD/oLjoNWUe1zWSfXLdGTv03xT8ewB1mn4 BDoaJsxb4w2oWKGF6GhA8NUOMQF7djyekEmrPRd3P1YCw6URPma1zeY/1bDHTSCPkODV l2hFFpYagl/MySD43JCJ8WnvLbNisTkeACSQ4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784096551; x=1784701351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Y9eicy7qFkVmMZW611/qMDh6GaEBG59Bdrl7IT5yIvE=; b=IqXgM8W7+NL1H69XuP3gJCEDc9b8e0bfcAIqKvYLDoZviZYdxjAYUoy1oFa2495LEW Sq/V37GyJYn3B0wv/PsjKfCqRCJz3w7VYd3/eK32MXd/CHMSI1C+wUipguUstZG1sAit 8ZdoW9YCMsAbKK8aBtdzyrhZDWSGnqHmxdT3XGLZLfnb3AlmUiJ2fvoRy7uaKahWyQN+ oUuj3hwsOyIrNIc8ewIvcAkbCHtQMmt5LF/M1Jmh66MiWrGNcE6FOJjszAXItFR6QT2Q o60TPMm18E9vibu8qLBTNlNElD14y5i7Vy5d4GTUTGZYa4IduX/po/4ply2GX8Gk++Mz 3K+Q== X-Gm-Message-State: AOJu0YyGO257hLji3S/s/mVlwM4ED9UXfZtZqdrGePeKiPwrJ6qgMc0m 4hzEYXGMaWfWKmjulRA5X/mFncMBuTOG1Lz1p2oBuOjRny7C/aNhA4Px5JOaVMJN6xRllpVTbuZ PeAl+xac= X-Gm-Gg: AfdE7cm5RCU6RYjhgreWX1XSMEWB2asSfC5z3EiahwYq0+xeYxdEEnfdqpE035wjvql 1Oephcx70+yAvfBUFwN9bjhm6KOE9Wg3TmL1an3cqydfHrNv3ry4k5KacXHnxUIGlrDKsoSNOfv DKxKjmskuR5eqojCJgY3HprzyCQ7KVC7unBfXEz1pCy09Yymv1j8/TyfiC7YLtd1Pw0UYHQG43B go/e13fcoADWJZeO8w9E773f4m+U2j+DIFNYiwxmtaBu+6TA0hYrcm3xyOq9dXY3yEsO/esIpmi uZSakOW5KYtaGkPT+ose8KY0fOO7QAwSmCTvoyG/fRrSM1nc71IqJiAlGHKGO5e70IZOD9c0ue7 JB6+xL44nrw453wWYfFI8OCNT2HKPgrqv9WfqtzUfPT9nQULYU0jleyvJ0rNBciQXSyRADyXr38 9SB0dSz5I/CYBhhHQiZBenGXHF2bHHChb4SN94g2U6vM6ywhq/g3Ys0DWM3zLS7Sq6TAI5QwgHH ELoxrZtNmo7 X-Received: by 2002:a17:907:97d5:b0:c12:b2dc:4834 with SMTP id a640c23a62f3a-c161ea6d217mr823641266b.57.1784096550856; Tue, 14 Jul 2026 23:22:30 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:30 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 09/16] arm64: dts: st: add pwm2/pwm4 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:26 +0200 Message-ID: <20260715062201.3599458-10-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the pwm2 and pwm4 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 6482dd47e977..695c9d771853 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -433,6 +433,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm2_pins_a: pwm2-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm2_sleep_pins_a: pwm2-sleep-0 { + pins { + pinmux =3D ; /* TIM2_CH1 */ + }; + }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { @@ -450,6 +467,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm4_pins_a: pwm4-0 { + pins { + pinmux =3D ; /* TIM4_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux =3D ; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:32 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Olivier Moysan , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 10/16] arm64: dts: st: add sai1 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:27 +0200 Message-ID: <20260715062201.3599458-11-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the sai1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi Reviewed-by: Olivier Moysan --- Changes in v7: - Add Reviewed-by tag of Olivier Moysan arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 695c9d771853..002fbc724b9d 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -520,6 +520,51 @@ pins { }; }; =20 + /omit-if-no-ref/ + sai1a_pins_a: sai1a-0 { + pins1 { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + ; /* SAI1_SCK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SAI1_MCLK_A */ + bias-disable; + drive-push-pull; + slew-rate =3D <2>; + }; + }; + + /omit-if-no-ref/ + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux =3D , /* SAI1_SD_A */ + , /* SAI1_FS_A */ + , /* SAI1_SCK_A */ + ; /* SAI1_MCLK_A */ + }; + }; + + /omit-if-no-ref/ + sai1b_pins_a: sai1b-0 { + pins { + pinmux =3D ; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:34 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 11/16] arm64: dts: st: add sdmmc2 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:28 +0200 Message-ID: <20260715062201.3599458-12-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the sdmmc2 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Change SDMMC2_CK pin bias from pull-up to bias-disable to avoid signal integrity issues on the clock line. Suggested by Sashiko arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 80 +++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 002fbc724b9d..c816a6aece47 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -622,6 +622,86 @@ pins { }; }; =20 + /omit-if-no-ref/ + sdmmc2_b4_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-disable; + }; + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D06CF33D4E4 for ; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:36 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 12/16] arm64: dts: st: add spi1 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:29 +0200 Message-ID: <20260715062201.3599458-13-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the spi1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index c816a6aece47..4e570e2e5157 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -702,6 +702,30 @@ pins { }; }; =20 + /omit-if-no-ref/ + spi1_pins_a: spi1-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + ; /* SPI1_MOSI */ + drive-push-pull; + bias-disable; + slew-rate =3D <1>; + }; + pins2 { + pinmux =3D ; /* SPI1_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi1_sleep_pins_a: spi1-sleep-0 { + pins1 { + pinmux =3D , /* SPI1_SCK */ + , /* SPI1_MOSI */ + ; /* SPI1_MISO */ + }; + }; + /omit-if-no-ref/ spi3_pins_a: spi3-0 { pins1 { --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1823D33E355 for ; Wed, 15 Jul 2026 06:22:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096562; cv=none; b=TjPpCSobjxlld2B9zeb0wpm76VcjT2V9lq4Cz+fEviqE2CrRQZn9RJli8lUA+5EnhxJz1zyMntGL7XPOJZa77kQozQedchz+6SCYEvdsHTjrtZFFP0SWozdEHOkRzficuNOv/gBqW7hMFlbrtbYbHhXTx87f1y0shszb6HbuKuk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784096562; c=relaxed/simple; bh=aj2uH9b/bfRzOkvrPYZ2176FA4QkmEK3VTNxofNEdQg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CJM7tGc0oJ2VPAT/tOybq1fQBMp5a8wuajlIpbGPWOHQl8IGe1VdpLiKHU03L4Pg8qbBXlasZJKnyMSJaTYvUZvA4GUArmfALV5xK2IWzySRvZD64WWkf+Ny462UX1wFLzFxTLTv4Fo5zOdCbdtAkq9kmpjm/ZhV6pABW4ORDPc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b=fFd59GFV; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fFd59GFV" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-69532288224so9178850a12.0 for ; Tue, 14 Jul 2026 23:22:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1784096559; x=1784701359; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=W4P3RDq+QoFIrungFJ6qmguRlrjE9G4sn4ESNQyuys8=; b=fFd59GFVromca/V+eGbTqgfO98vWVxUfZPWIXxgCw9w9EF2k0o++U2lriqojFAeAsj gvGNuYkjsGTx4oQJ/IcxEVauH9beHsrwes9lf3FGUps+W7UphHa+8C6m2ZMXOmc7LH/h pxcGl4S9uS490gFhk8g4MvF42atNyBOaGVzFE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784096559; x=1784701359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=W4P3RDq+QoFIrungFJ6qmguRlrjE9G4sn4ESNQyuys8=; b=aUK+6epukbBH+3kp2u53eyKH6KsZQMD67GHHAp4+r3T0iSmrw67njQfUf/w9Slg8+5 WroUPwAF/E4SOQ4ifm2FU2mwce+Wou0r7kWWelW/IwEotfh/wlxKe5Tq9kUcirnWuWBW iPHE6Pvm4XgtLvzRr6b3V8q0TS8HrZ6rL0N1vSyZ8pmoTFnrtcduXN8X9EmZbKtStV6W +ZIABjH6CSTSF6OeagprhG5rXXhD8zHTf/6L0zSKtDcUDpU1cteABwhwPL/Qmg6Kl7fb oDQWj3QAhKEGhubaZgDmB34esGJr1azHMQlfNdtOWXg6bkzF6SWWx5hW8YMuItZ1dP4D ggCA== X-Gm-Message-State: AOJu0Yw0FCirXJ7w4TaOsdXUjhgxz1ibhNs76r1Ad4PxMLaNyfJzpHsp Ula6C63gqsBlsIQg0a9SrerHsKwSK9EZyVDAewbX4v2zK3Jliz+Uf7uuw9TP8GQCd2ophHrjA/H 15XttuMw= X-Gm-Gg: AfdE7cn1r1LUrstGWUte5BlJ5HiVx4k7TMWpP8p4ovNwn0mlbhpKotX85upQKC1hOub mLK0kZhIg+RH+eEI/ZvD1vh0NKfy7tPA6MI7JzywuqQTunwCAToAlqIRnFU+qR0FRDJCnq7SnP2 gdkD2oJnVxvInbaRmrKX7Ojz20yA6Z8dmX8Mzlp5rkBTihLSQPdrtZlyup7zLnQoIkYZAu+dEmE lzzN+azF9VGROizd7Z7Gllf2EI3q8iIozGKeUkzF05qLE8zg9BDU4fMZIeI4h7ZxaVAiz8xxcvr no/xW7SeIoGECQEQc6A+TF8yTKioMUB+GLgPgFHEhSaWJuOZbn/OpIbqkhJ46Tda8VS6QXrC51F LIoe3UoVRxEC4fAE0uauyw5JnF/gH1Rs1GSr7tATPecyTCy5/VpatLQmQ4Hy6OnfLezXwZE3tvv yxeoKsC1EQHlUaexkoZb75zUWChAzDJdG6TXnoxq0FntKcbl3B5lXje8ny/FFloyU2NxCkFBCgP m4OW0OozCOLYpvkypmpU+s= X-Received: by 2002:a17:907:7242:b0:c15:b68a:5e16 with SMTP id a640c23a62f3a-c1667b4f80cmr304878366b.60.1784096559477; Tue, 14 Jul 2026 23:22:39 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.. ([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:38 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 13/16] arm64: dts: st: add usart1 pins for stm32mp25 Date: Wed, 15 Jul 2026 08:20:30 +0200 Message-ID: <20260715062201.3599458-14-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the usart1 pins used on MicroGEA-STM32MP257-RMM board. Signed-off-by: Dario Binacchi --- (no changes since v1) arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 4e570e2e5157..d515e44832d7 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -766,6 +766,39 @@ pins { }; }; =20 + /omit-if-no-ref/ + usart1_pins_b: usart1-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux =3D ; /* USART1_TX */ + }; + pins2 { + pinmux =3D ; /* USART1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux =3D , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4040E340A4D for ; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:41 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 14/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM Date: Wed, 15 Jul 2026 08:20:31 +0200 Message-ID: <20260715062201.3599458-15-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support Engicam MicroGEA-STM32MP257 SoM with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM The SoM also provides an Ethernet MAC, but Ethernet support is not enabled at this stage due to a known silicon limitation documented in [1]. This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC errors"), where CRC errors may occur in ETH1 RMII direct mode when directly connected to I/Os. The workaround requires use of the Ethernet switch (ETHSW), which introduces additional DT bindings and topology complexity. This is intended to be addressed in a separate patch series. [1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-devi= ce-errata-stmicroelectronics.pdf Signed-off-by: Dario Binacchi --- (no changes since v4) Changes in v4: - Drop inclusion of stm32mp25xf.dtsi, we are using stm32mp257d. Changes in v3: - Fix a typo in the URL .../dts/st/stm32mp257-engicam-microgea.dtsi | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch= /arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi new file mode 100644 index 000000000000..5b4287e86def --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include "stm32mp257.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257 SoM"; + compatible =3D "engicam,microgea-stm32mp257", "st,stm32mp257"; + + memory@80000000 { + device_type =3D "memory"; + reg =3D <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + scmi_vddcore: regulator@b { + reg =3D ; + regulator-name =3D "vddcore"; + }; + scmi_v1v8: regulator@e { + reg =3D ; + regulator-name =3D "v1v8"; + }; + scmi_v3v3: regulator@10 { + reg =3D ; + regulator-name =3D "v3v3"; + }; + scmi_vdd3v3_usb: regulator@14 { + reg =3D ; + regulator-name =3D "vdd3v3_usb"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width =3D <8>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio2>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; --=20 2.43.0 From nobody Sat Jul 25 18:01:02 2026 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 91A7133E355 for ; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:43 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RESEND PATCH v7 15/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257-RMM board Date: Wed, 15 Jul 2026 08:20:32 +0200 Message-ID: <20260715062201.3599458-16-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support for Engicam MicroGEA-STM32MP257-RMM board with: - 8 GB eMMC Flash - 2 GB LPDDR4 DRAM - CAN - LEDs - LCD panel with touchscreen - Micro SD card connector - Audio codec - Buzzer Signed-off-by: Dario Binacchi --- (no changes since v5) Changes in v5: - Fix touchscreen resolution to 480x854 - Fix SPI1 CS0 polarity to GPIO_ACTIVE_LOW Changes in v2: - Drop the clocks property from the sai1 node in stm32mp257-engicam-microge= a-rmm.dts to avoid overriding the peripheral bus clock reference defined in the base SoC device tree. Suggested by Sashiko. - Reference the existing labeled nodes directly at the root level using &sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of redefining the entire node structure and redeclaring the labels. Suggeste= d by Sashiko. - Drop the #clock-cells property from sai1a and remove the reference to sai= 1a from the clocks array in sai1b, relying strictly on the st,sync property to ha= ndle internal synchronization. arch/arm64/boot/dts/st/Makefile | 1 + .../st/stm32mp257-engicam-microgea-rmm.dts | 319 ++++++++++++++++++ 2 files changed, 320 insertions(+) create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.= dts diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makef= ile index 63908113ae36..386eca593c54 100644 --- a/arch/arm64/boot/dts/st/Makefile +++ b/arch/arm64/boot/dts/st/Makefile @@ -2,5 +2,6 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp215f-dk.dtb \ stm32mp235f-dk.dtb \ + stm32mp257-engicam-microgea-rmm.dtb \ stm32mp257f-dk.dtb \ stm32mp257f-ev1.dtb diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts b/a= rch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts new file mode 100644 index 000000000000..3aea0c2f6651 --- /dev/null +++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts @@ -0,0 +1,319 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2026 Amarula Solutions, Dario Binacchi + * Copyright (C) 2026 Engicam srl + */ + +/dts-v1/; + +#include +#include +#include + +#include "stm32mp257-engicam-microgea.dtsi" + +/ { + model =3D "Engicam MicroGEA STM32MP257D RMM Board"; + compatible =3D "engicam,microgea-stm32mp257-rmm", + "engicam,microgea-stm32mp257", "st,stm32mp257"; + + aliases { + mmc0 =3D &sdmmc1; + mmc1 =3D &sdmmc2; + serial0 =3D &usart2; + serial1 =3D &usart1; + }; + + backlight: backlight { + compatible =3D "pwm-backlight"; + brightness-levels =3D <0 100>; + num-interpolated-steps =3D <100>; + default-brightness-level =3D <85>; + pwms =3D <&pwm2 0 100000 0>; + }; + + buzzer { + compatible =3D "pwm-beeper"; + pwms =3D <&pwm4 0 1000000 0>; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + framebuffer { + compatible =3D "simple-framebuffer"; + clocks =3D <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>; + lcd-supply =3D <®_3v3>; + status =3D "disabled"; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpioh 2 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + + led-1 { + gpios =3D <&gpioh 6 GPIO_ACTIVE_HIGH>; + default-state =3D "off"; + status =3D "okay"; + }; + }; + + mclk: clock-mclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_3v3: regulator-3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + reg_ext_pwr: regulator-ext-pwr { + compatible =3D "regulator-fixed"; + regulator-name =3D "ext-pwr"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpiog 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sound { + compatible =3D "audio-graph-card"; + label =3D "STM32MP25-RMM"; + widgets =3D "Headphone", "Headphone Jack", + "Microphone", "Microphone Jack"; + routing =3D "Headphone Jack", "HP_OUT", + "MIC_IN", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + dais =3D <&sai1a_port &sai1b_port>; + status =3D "okay"; + }; +}; + +&arm_wdt { + timeout-sec =3D <32>; + status =3D "okay"; +}; + +&i2c1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c1_pins_a>; + pinctrl-1 =3D <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + touchscreen@38 { + compatible =3D "edt,edt-ft5306"; + reg =3D <0x38>; + interrupt-parent =3D <&gpiob>; + interrupts =3D <0 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpiod 1 GPIO_ACTIVE_LOW>; + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <854>; + }; +}; + +&i2c2 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c2_pins_a>; + pinctrl-1 =3D <&i2c2_sleep_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + sgtl5000: codec@a { + compatible =3D "fsl,sgtl5000"; + reg =3D <0x0a>; + #sound-dai-cells =3D <0>; + clocks =3D <&mclk>; + + VDDA-supply =3D <®_3v3>; + VDDIO-supply =3D <®_3v3>; + VDDD-supply =3D <®_1v8>; + + sgtl5000_port: port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + sgtl5000_tx_endpoint: endpoint@0 { + reg =3D <0>; + remote-endpoint =3D <&sai1a_endpoint>; + frame-master =3D <&sgtl5000_tx_endpoint>; + bitclock-master =3D <&sgtl5000_tx_endpoint>; + }; + + sgtl5000_rx_endpoint: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&sai1b_endpoint>; + frame-master =3D <&sgtl5000_rx_endpoint>; + bitclock-master =3D <&sgtl5000_rx_endpoint>; + }; + }; + }; +}; + +<dc { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <<dc_pins_a>; + pinctrl-1 =3D <<dc_sleep_pins_a>; + status =3D "okay"; + + port { + ltdc_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; +}; + +&m_can1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&m_can1_pins_a>; + pinctrl-1 =3D <&m_can1_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&sai1a_pins_a>, <&sai1b_pins_a>; + pinctrl-1 =3D <&sai1a_sleep_pins_a>, <&sai1b_sleep_pins_a>; + status =3D "okay"; +}; + +&sai1a { + dma-names =3D "tx"; + status =3D "okay"; + + sai1a_port: port { + sai1a_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_tx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +&sai1b { + dma-names =3D "rx"; + st,sync =3D <&sai1a 2>; + clocks =3D <&rcc CK_KER_SAI1>; + clock-names =3D "sai_ck"; + status =3D "okay"; + + sai1b_port: port { + sai1b_endpoint: endpoint { + remote-endpoint =3D <&sgtl5000_rx_endpoint>; + dai-format =3D "i2s"; + mclk-fs =3D <512>; + }; + }; +}; + +/* MicroSD */ +&sdmmc1 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc1_b4_pins_a>; + pinctrl-1 =3D <&sdmmc1_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + disable-wp; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&scmi_v3v3>; + vqmmc-supply =3D <&scmi_vddio1>; + no-1-8-v; + status =3D "okay"; +}; + +&spi1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&spi1_pins_a>; + pinctrl-1 =3D <&spi1_sleep_pins_a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpioh 8 GPIO_ACTIVE_LOW>, <&gpioh 3 GPIO_ACTIVE_HIGH>; + status =3D "okay"; + + display: display@0 { + compatible =3D "rocktech,rk050hr345-ct106a", "ilitek,ili9806e"; + reg =3D <0>; + vdd-supply =3D <®_3v3>; + spi-max-frequency =3D <10000000>; + reset-gpios =3D <&gpiob 6 GPIO_ACTIVE_LOW>; + backlight =3D <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint =3D <<dc_out>; + }; + }; + }; +}; + +&timers2 { + status =3D "okay"; + + pwm2: pwm { + pinctrl-0 =3D <&pwm2_pins_a>; + pinctrl-1 =3D <&pwm2_sleep_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; +}; + +&timers4 { + status =3D "okay"; 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([2.196.41.101]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15d0c3cf1esm1028820366b.44.2026.07.14.23.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 23:22:45 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: michael@amarulasolutions.com, francesco.utel@engicam.com, domenico.acri@engicam.com, linux-amarula@amarulasolutions.com, Dario Binacchi , Arnd Bergmann , Bjorn Andersson , Dmitry Baryshkov , Eric Biggers , Geert Uytterhoeven , Krzysztof Kozlowski , Luca Weiss , Michal Simek , Sven Peter Subject: [RESEND PATCH v7 16/16] arm64: defconfig: enable configs for Engicam MicroGEA-STM32MP257-RMM Date: Wed, 15 Jul 2026 08:20:33 +0200 Message-ID: <20260715062201.3599458-17-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> References: <20260715062201.3599458-1-dario.binacchi@amarulasolutions.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable I2C (touchscreen and audio codec), SPI (display configuration), DRM panel and SAI (audio) configurations required to support the Engicam MicroGEA-STM32MP257-RMM board Signed-off-by: Dario Binacchi --- Changes in v7: - Switch CONFIG_I2C_STM32F7 and CONFIG_SPI_STM32 to modules. Changes in v6: - Update toto match the current upstream defconfig after merge window changes (no functional changes). Changes in v3: - Drop patch "arm64: defconfig: cleanup the defconfig" - Rebased after dropping patch "arm64: defconfig: cleanup the defconfig" arch/arm64/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 654a102cb5bc..99cd81b684ea 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -633,6 +633,7 @@ CONFIG_I2C_RK3X=3Dy CONFIG_I2C_RZV2M=3Dm CONFIG_I2C_S3C2410=3Dy CONFIG_I2C_SH_MOBILE=3Dy +CONFIG_I2C_STM32F7=3Dm CONFIG_I2C_TEGRA=3Dy CONFIG_I2C_UNIPHIER_F=3Dy CONFIG_I2C_XILINX=3Dm @@ -670,6 +671,7 @@ CONFIG_SPI_QUP=3Dy CONFIG_SPI_QCOM_GENI=3Dm CONFIG_SPI_S3C64XX=3Dy CONFIG_SPI_SH_MSIOF=3Dm +CONFIG_SPI_STM32=3Dm CONFIG_SPI_STM32_OSPI=3Dm CONFIG_SPI_SUN6I=3Dy CONFIG_SPI_TEGRA210_QUAD=3Dm @@ -1011,6 +1013,7 @@ CONFIG_DRM_PANEL_LVDS=3Dm CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm +CONFIG_DRM_PANEL_ILITEK_ILI9806E_SPI=3Dm CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm CONFIG_DRM_PANEL_KHADAS_TS050=3Dm CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm @@ -1113,6 +1116,7 @@ CONFIG_SND_SOC_ROCKCHIP_SPDIF=3Dm CONFIG_SND_SOC_ROCKCHIP_RT5645=3Dm CONFIG_SND_SOC_RK3399_GRU_SOUND=3Dm CONFIG_SND_SOC_SAMSUNG=3Dm +CONFIG_SND_SOC_STM32_SAI=3Dm CONFIG_SND_SUN8I_CODEC=3Dm CONFIG_SND_SUN8I_CODEC_ANALOG=3Dm CONFIG_SND_SUN50I_CODEC_ANALOG=3Dm --=20 2.43.0