From nobody Sat Jul 25 18:01:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 465633B47F3 for ; Wed, 15 Jul 2026 05:34:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093678; cv=none; b=Qcf4R2NEeBVPKaffbzY4F20z9wmM22TdgvILOCYrstn3byabwLgMjP2rB4ZGqTFJX7PvUDprmLpeVLmOH/9suGdHeJUFkzl9E9WFXfFcXEEOxXS4DjgsMBD3EB3UnMlX1asuT3GaAG7dxgRsG3smaXHTWL1IKB82BYUOXaUhjZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093678; c=relaxed/simple; bh=mF5BRgQuHu/yR1NXlAdo4m6cZY21TPxbdISvRvl9Lmk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CoeQrwumE+s+LlL/Hvjezv2jU/ZfeQPETu/37CSEDGbL8ON6GxSo6AOjtIp9/3/nvx2cV0Hd8iEhmmpnTxQ6NuwVfGswtqWtfrePJeQSGAA+oZm86arWI9b3aROZ/RHhBeIybCBtIKg3qKBO/51SZ6PTOfgvyDuDkm78pxZbZhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=pTZX4po8; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="pTZX4po8" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 583A81477; Tue, 14 Jul 2026 22:34:31 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B082C3F915; Tue, 14 Jul 2026 22:34:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093675; bh=mF5BRgQuHu/yR1NXlAdo4m6cZY21TPxbdISvRvl9Lmk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pTZX4po81HuHAmi//UY5p/Ukhb6eQpLf9m2KT/WmRwuvUrVF6EkBv6qvuFAbitcUI Qew8OLdXi34BsXesqsWy8PaFa6v/kwbC2oNuCOQc0eoNZ09ZJFbzK4J5AeiYl33b9f OOgUE6LeADK/gd9d5IYRhJ2iNQwm79O9J2IBTZ4o= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 1/6] arm64: cputype: Add Cortex-A520AE definitions Date: Wed, 15 Jul 2026 11:04:03 +0530 Message-ID: <20260715053408.1950475-2-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cputype definitions for Cortex-A520AE. The definition can be found in Cortex-A520AE TRM, https://developer.arm.com/documentation/107726/0001/ as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Reviewed-by: Gavin Shan --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index 1b9f0cda1336..e41fae46426b 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -82,6 +82,7 @@ #define ARM_CPU_PART_CORTEX_X1 0xD44 #define ARM_CPU_PART_CORTEX_A510 0xD46 #define ARM_CPU_PART_CORTEX_A520 0xD80 +#define ARM_CPU_PART_CORTEX_A520AE 0xD88 #define ARM_CPU_PART_CORTEX_A710 0xD47 #define ARM_CPU_PART_CORTEX_A715 0xD4D #define ARM_CPU_PART_CORTEX_X2 0xD48 @@ -176,6 +177,7 @@ #define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X1) #define MIDR_CORTEX_A510 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A510) #define MIDR_CORTEX_A520 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A520) +#define MIDR_CORTEX_A520AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CO= RTEX_A520AE) #define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A710) #define MIDR_CORTEX_A715 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORT= EX_A715) #define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX= _X2) --=20 2.43.0 From nobody Sat Jul 25 18:01:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C320839CCFC for ; Wed, 15 Jul 2026 05:34:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093681; cv=none; b=o3KC74uzfUHQ2BdpEEmLELnNTNGKBHqpUAmzuMKHOCoI8qH2IJWBVjVnh1EFsh5c7mjCcXjL2r+GVUahMxoSyoOmy8VvPSoDQGknKzIvSeZscPcGxGZoEuoQ68IDeNSceiIpu9tuMghmRxBeS7mkcIKE7c4KcsTGbO12ONIE3lw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093681; c=relaxed/simple; bh=gINZxYcplFipihH4ocqFNLt64lkzxW9gXxxIFLNrvSI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Prk3Jlp9MshlVF9aMR0aEhwC2vUQ4K+s4v4m8OFh81QT3d8ek17lsYQX9YBs+c+T1j5VcaG2SzKK7FXuacNOMnzms233kUF4FULT8lchSLlUKpBw9cS9endsOZPuWe1WFJWcgA0PwF2m6VTnztLNAsHLrqkGPd0Ask0JuN0zMQs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=LjSoZ2gD; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="LjSoZ2gD" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A5551339; Tue, 14 Jul 2026 22:34:34 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 06BCB3F915; Tue, 14 Jul 2026 22:34:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093678; bh=gINZxYcplFipihH4ocqFNLt64lkzxW9gXxxIFLNrvSI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LjSoZ2gDiaRu6A+09uuu0d+etps/RH3XcF295mOxKPENftsUiYbl7CKBEE5dNLlzN nU6Yee77O6PAFd93OpP+F/djIbjJmmRMFuVAIE+KAHQYQ+2k2YtpjySQHBaCp5gNOj WUEKFdOezrJ/saBXBXinAKwKswln3yJZj4lRp/54= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 2/6] arm64: cputype: Add C1-Nano definitions Date: Wed, 15 Jul 2026 11:04:04 +0530 Message-ID: <20260715053408.1950475-3-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add cputype definitions for C1-Nano. The definition can be found in C1-Nano TRM, https://developer.arm.com/documentation/107753/0002 as part of MIDR_EL1 bit descriptions. This is going to be used in the bbml3 support list. Reviewed-by: Anshuman Khandual Signed-off-by: Linu Cherian Reviewed-by: Gavin Shan --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cput= ype.h index e41fae46426b..1fa29616e586 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -100,6 +100,7 @@ #define ARM_CPU_PART_CORTEX_A720AE 0xD89 #define ARM_CPU_PART_C1_ULTRA 0xD8C #define ARM_CPU_PART_NEOVERSE_N3 0xD8E +#define ARM_CPU_PART_C1_NANO 0xD8A #define ARM_CPU_PART_C1_PRO 0xD8B #define ARM_CPU_PART_C1_PREMIUM 0xD90 =20 @@ -195,6 +196,7 @@ #define MIDR_CORTEX_A720AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CO= RTEX_A720AE) #define MIDR_C1_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_ULTR= A) #define MIDR_NEOVERSE_N3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOV= ERSE_N3) +#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO) #define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO) #define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PR= EMIUM) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_T= HUNDERX) --=20 2.43.0 From nobody Sat Jul 25 18:01:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D42C03B47DD for ; Wed, 15 Jul 2026 05:34:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093684; cv=none; b=AIwFYvjBtwK5HVKhT593xBBdlOQwBD2B+uV455p1tm3XosPD9ZUBDEhm6tK6aHYOdMvvszLfaOjFw3E6HpItzx9c0qhwerQHZ3FxXyA/pmFz2dYPfJ364nkr0qObnlDHTG+faaeB4A6ANVX3u7tCghOUuUMy5sNf2VFSeT/jilw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093684; c=relaxed/simple; bh=N7dBfVaI7343acB0SSAtsxc3PMX1dKExbRDxnREghp8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=F73qAxnaMprTB1//LSIOshjT7bA6cx+wtcziJk8D12Ptd1ctcOPuAtaCS+aGn/UvTcRazmCAU3Ws6P/WM58FZBpRwMQ2L3BoaO7ccxk//PgT64PlVMdzQOnCKFvTYAH7MwouY9NBkidhsgQLKqk+dm/BJpnm9nKtOBhVs/Ev3p8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=bl0S0hqs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="bl0S0hqs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EB0AD339; Tue, 14 Jul 2026 22:34:37 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 51B653F915; Tue, 14 Jul 2026 22:34:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093682; bh=N7dBfVaI7343acB0SSAtsxc3PMX1dKExbRDxnREghp8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bl0S0hqs9IXXWEHjjCVDLxRM8UWFJU6CjYBItjLLAwKtip/UTC3HUWo4NWPBawb2h 0zybto25wB65R7tUiRHUdLwroi6BFRLXKE8OxlvLti+p2l5I1GgpHwgFGHBeME8Zje ehoR1W3FEdx4hAaMh3xS4VpsOyzxY+tN3tDJi6QE= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 3/6] arm64: cpufeature: Extend bbml2_noabort support list Date: Wed, 15 Jul 2026 11:04:05 +0530 Message-ID: <20260715053408.1950475-4-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add below cpus to the midr list, which supports BBML2_NOABORT. Cortex A520(AE) Cortex A715 Cortex A720(AE) Cortex A725 Neoverse N3 C1-Nano C1-Pro C1-Ultra C1-Premium C1-Ultra and C1-Premium both suffer from erratum 3683289, where Break-Before-Make must be followed to avoid a livelock. For both CPUs, the erratum is fixed from r1p1. Hence we do not enable BBML2_NOABORT for CPU revisions <=3D r1p0. The relevant SDENs are: * C1-Ultra: https://developer.arm.com/documentation/111077/9-00/ * C1-Premium: https://developer.arm.com/documentation/111078/9-00/ Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual Reviewed-by: Gavin Shan --- Documentation/arch/arm64/silicon-errata.rst | 4 ++++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ 2 files changed, 14 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index 014aa1c215a1..57c778446936 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -242,10 +242,14 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_41184= 14 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | C1-Premium | #3683289 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | C1-Premium | #4193780 | ARM64_ERRATUM_41184= 14 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | C1-Pro | #4193714 | ARM64_ERRATUM_41937= 14 | +----------------+-----------------+-----------------+--------------------= ---------+ +| ARM | C1-Ultra | #3683289 | N/A = | ++----------------+-----------------+-----------------+--------------------= ---------+ | ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_41184= 14 | +----------------+-----------------+-----------------+--------------------= ---------+ | ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CP= RE_ERRATA| diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9a22df0c5120..1b804b6c4fe0 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2152,6 +2152,16 @@ bool cpu_supports_bbml2_noabort(void) MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), MIDR_ALL_VERSIONS(MIDR_AMPERE1), MIDR_ALL_VERSIONS(MIDR_AMPERE1A), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A715), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A725), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3), + MIDR_ALL_VERSIONS(MIDR_C1_NANO), + MIDR_ALL_VERSIONS(MIDR_C1_PRO), + /* Erratum 3683289 fixed in r1p1 */ + MIDR_REV_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf), + MIDR_REV_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf), {} }; =20 --=20 2.43.0 From nobody Sat Jul 25 18:01:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 248A5381B1F for ; Wed, 15 Jul 2026 05:34:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093687; cv=none; b=NMRCDNvIEovK0bSBjvVphcHuY5sTn9w14n2Y6H6oFCUb1ZEN2VPWWv62JJajJvTDBx8OjNFThvROguXw7sT6un296GYBDv8FlvhWXyK/3r9peQpI5xxYQFeSkqsJvTfmZi7OIwzH4ve6t4+SY6dA1g4u00knhQz7/nBEgH06+6g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093687; c=relaxed/simple; bh=nxgV4VVUbFhBk+TSn4RlaqR9wD5zcYBXwUNgBXrhO6c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rxu0iTwfQOcLgY7vN17CFw5SNL3vI84sJyS7Wruh+e4qZc2nnc2aWr+fDnVPJRxfH5EMekqls+TCrCA3B0w9qwDP9fZVJvSw9zGI4tfxv+aJNBHLHtB4VK45GY4SS9vHUapD8Z7iE/yALV57KXB09bETIztFK3WyqPfedVDuE+0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=lxmjtZV/; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="lxmjtZV/" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4A9C0339; Tue, 14 Jul 2026 22:34:41 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9BF4F3F915; Tue, 14 Jul 2026 22:34:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093685; bh=nxgV4VVUbFhBk+TSn4RlaqR9wD5zcYBXwUNgBXrhO6c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lxmjtZV/C65aumSvmajIJK5/sM7r5TRB0kEGQbMsY+jG+DOrcAUeWRYgVmDN3O2e0 K51weK32F8bIozpvYHiaZ2tS/Oos1mv936uBDjmWNbhMOlyH6Dhv90r7xnJP+YdxTP 0bB33lhe+jSbaK/+IHKnJCqo/BKLqnYV6oHi+XG0= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 4/6] arm64: sysreg: Add BBM_3 Date: Wed, 15 Jul 2026 11:04:06 +0530 Message-ID: <20260715053408.1950475-5-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add BBM_3 definition for ID_AA64MMFR2_EL1 register. Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual Reviewed-by: Gavin Shan --- arch/arm64/tools/sysreg | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 7cb61aca3797..e070ada06196 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2259,6 +2259,7 @@ UnsignedEnum 55:52 BBM 0b0000 0 0b0001 1 0b0010 2 + 0b0011 3 EndEnum UnsignedEnum 51:48 TTL 0b0000 NI --=20 2.43.0 From nobody Sat Jul 25 18:01:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 6C8F53B3BF2 for ; Wed, 15 Jul 2026 05:34:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093691; cv=none; b=RbGas+l3WCAfWUcE8heKiiFKavcn1gehOCG2FSxgRU09CGU78hA0J/pgAH5Ck4+ITBBe9BqUKNwnsBcL/9vfPmGc9tSoAVabXdpQyaw2UY5C9BTI+/7weUeis9c1fjpbpQTZ3YeV+4xdSUIqGAGFceoxj+oQ3cPjiZWKD/6wPNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093691; c=relaxed/simple; bh=qzpdh4dmQAtZw7czSZiVU9NEwArvhlUoc+qr2J76Mzs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ev2YvYtK8BC8twLz0TL05znI/NYimkh1mPnW6V9tqceIj4qw9psdelgZB6caS7mU5an7VVEeE6H+UXK1820OrIvq78revDVT/n81QuuLFWiwnnyc3zozaOpLmXrcSzZxZIuH9S7PMlPxGiGDaoRNPc2X0ZlFMrhH3BA7uUUb7IM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=soAz5fUR; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="soAz5fUR" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9AABC1477; Tue, 14 Jul 2026 22:34:44 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F08433F915; Tue, 14 Jul 2026 22:34:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093688; bh=qzpdh4dmQAtZw7czSZiVU9NEwArvhlUoc+qr2J76Mzs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=soAz5fURo7adtrvXEH8eFSr6DJ+nRQ6+xecl6XWZfSLQZwRm/JaPpWyIPDNkYNeHA MMY6P+DdQ8dKWYf61OF44mnSx/G4KLdlN+uM40uljPLfGxsNMBLuepWKb0jOdppGRH V5/36N/cPX9eGTW8RlVz5X27IlV3peRE0EOczqcY= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 5/6] arm64: cpufeature: Rename BBML2_NOABORT as BBML3 Date: Wed, 15 Jul 2026 11:04:07 +0530 Message-ID: <20260715053408.1950475-6-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - As bbml2_noabort is functionally equivalent to bbml3, rename cpu/system_supports_bbml2_noabort to cpu/system_supports_bbml3. The ARM64 capability name is also renamed accordingly. - As BBML2_NOABORT or the equivalent BBML3 is the kernel requirement for setting up linear map with block/contpte mappings and not BBML2, replace all bbml2 references with bbml3. FEAT_BBML3, is introduced as part of 2025 Architecture Extensions. https://developer.arm.com/documentation/109697/2026_03/2025-Architecture-Ex= tensions No functional changes are introduced with this patch. Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual Reviewed-by: Gavin Shan --- arch/arm64/include/asm/cpufeature.h | 6 ++-- arch/arm64/kernel/cpufeature.c | 30 +++++------------ arch/arm64/mm/contpte.c | 21 +++++------- arch/arm64/mm/mmu.c | 52 ++++++++++++++--------------- arch/arm64/mm/proc.S | 4 +-- arch/arm64/tools/cpucaps | 2 +- 6 files changed, 49 insertions(+), 66 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index a57870fa96db..d90040fb9de6 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -878,11 +878,11 @@ static inline bool system_supports_pmuv3(void) return cpus_have_final_cap(ARM64_HAS_PMUV3); } =20 -bool cpu_supports_bbml2_noabort(void); +bool cpu_supports_bbml3(void); =20 -static inline bool system_supports_bbml2_noabort(void) +static inline bool system_supports_bbml3(void) { - return alternative_has_cap_unlikely(ARM64_HAS_BBML2_NOABORT); + return alternative_has_cap_unlikely(ARM64_HAS_BBML3); } =20 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 1b804b6c4fe0..25a705e02618 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2131,21 +2131,10 @@ static bool hvhe_possible(const struct arm64_cpu_ca= pabilities *entry, return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); } =20 -bool cpu_supports_bbml2_noabort(void) +bool cpu_supports_bbml3(void) { - /* - * We want to allow usage of BBML2 in as wide a range of kernel contexts - * as possible. This list is therefore an allow-list of known-good - * implementations that both support BBML2 and additionally, fulfill the - * extra constraint of never generating TLB conflict aborts when using - * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain - * kernel contexts difficult to prove safe against recursive aborts). - * - * Note that implementations can only be considered "known-good" if their - * implementors attest to the fact that the implementation never raises - * TLB conflict aborts for BBML2 mapping granularity changes. - */ - static const struct midr_range supports_bbml2_noabort_list[] =3D { + /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ + static const struct midr_range supports_bbml3_list[] =3D { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), @@ -2165,8 +2154,7 @@ bool cpu_supports_bbml2_noabort(void) {} }; =20 - /* Does our cpu guarantee to never raise TLB conflict aborts? */ - if (!is_midr_in_range_list(supports_bbml2_noabort_list)) + if (!is_midr_in_range_list(supports_bbml3_list)) return false; =20 /* @@ -2177,9 +2165,9 @@ bool cpu_supports_bbml2_noabort(void) return true; } =20 -static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, i= nt scope) +static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) { - return cpu_supports_bbml2_noabort(); + return cpu_supports_bbml3(); } =20 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) @@ -3072,10 +3060,10 @@ static const struct arm64_cpu_capabilities arm64_fe= atures[] =3D { ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) }, { - .desc =3D "BBM Level 2 without TLB conflict abort", - .capability =3D ARM64_HAS_BBML2_NOABORT, + .desc =3D "BBM Level 3", + .capability =3D ARM64_HAS_BBML3, .type =3D ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, - .matches =3D has_bbml2_noabort, + .matches =3D has_bbml3, }, { .desc =3D "52-bit Virtual Addressing for KVM (LPA2)", diff --git a/arch/arm64/mm/contpte.c b/arch/arm64/mm/contpte.c index 2de12656b4d8..0acab179fc1a 100644 --- a/arch/arm64/mm/contpte.c +++ b/arch/arm64/mm/contpte.c @@ -89,7 +89,7 @@ static void contpte_convert(struct mm_struct *mm, unsigne= d long addr, } =20 /* - * On eliding the __tlb_flush_range() under BBML2+noabort: + * On eliding the __tlb_flush_range() under BBML3: * * NOTE: Instead of using N=3D16 as the contiguous block length, we use * N=3D4 for clarity. @@ -135,7 +135,7 @@ static void contpte_convert(struct mm_struct *mm, unsig= ned long addr, * contiguous TLB entry, which is a micro-optimisation opportunity, * but does not affect correctness. * - * In the BBML2 case, the change is avoiding the intermediate tlbi+dsb. + * In the BBML3 case, the change is avoiding the intermediate tlbi+dsb. * This means a few things, but notably other PEs will still "see" any * stale cached TLB entries. This could lead to a "contiguous bit * misprogramming" issue until the final tlbi+dsb of the changed page, @@ -158,21 +158,16 @@ static void contpte_convert(struct mm_struct *mm, uns= igned long addr, * are present, and a write is made to this address, do we fault or * is the write permitted (via amalgamation)? * - * The relevant Arm ARM DDI 0487L.a requirements are RNGLXZ and RJQQTC, - * and together state that when BBML1 or BBML2 are implemented, either - * a TLB conflict abort is raised (which we expressly forbid), or will - * "produce an OA, access permissions, and memory attributes that are - * consistent with any of the programmed translation table values". - * - * That is to say, will either raise a TLB conflict, or produce one of - * the cached TLB entries, but never amalgamate. + * With BBML3 implemented, no TLB conflict abort is raised and the OA, + * access permissions and memory attributes produced is one of the cached + * TLB entries, but never amalgamate. * * Thus, as the page tables are only considered "consistent" after * the final tlbi+dsb (which evicts both the single stale (RW,n) TLB * entry as well as the new contiguous (RO,c) TLB entry), omitting the * initial tlbi+dsb is correct. * - * It is also important to note that at the end of the BBML2 folding + * It is also important to note that at the end of the BBML3 folding * case, we are still left with potentially all N TLB entries still * cached (the N-1 non-contiguous ptes, and the single contiguous * block). However, over time, natural TLB pressure will cause the @@ -214,7 +209,7 @@ static void contpte_convert(struct mm_struct *mm, unsig= ned long addr, * * |____| <--- tlbi + dsb * - * For BBML2, we again remove the intermediate tlbi+dsb. Here, there + * For BBML3, we again remove the intermediate tlbi+dsb. Here, there * are no issues, as the final tlbi+dsb covering the changed page is * guaranteed to remove the original large contiguous (RW,c) TLB entry, * as well as the intermediate (RW,n) TLB entry; the next access will @@ -224,7 +219,7 @@ static void contpte_convert(struct mm_struct *mm, unsig= ned long addr, * regardless. */ =20 - if (!system_supports_bbml2_noabort()) + if (!system_supports_bbml3()) __flush_tlb_range(&vma, start_addr, addr, PAGE_SIZE, 3, TLBF_NOWALKCACHE); =20 diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index a25d8beacc83..7d17b002fb6f 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -779,18 +779,18 @@ static int split_kernel_leaf_mapping_locked(unsigned = long addr) =20 static inline bool force_pte_mapping(void) { - const bool bbml2 =3D system_capabilities_finalized() ? - system_supports_bbml2_noabort() : cpu_supports_bbml2_noabort(); + const bool bbml3 =3D system_capabilities_finalized() ? + system_supports_bbml3() : cpu_supports_bbml3(); =20 if (debug_pagealloc_enabled()) return true; - if (bbml2) + if (bbml3) return false; return rodata_full || arm64_kfence_can_set_direct_map() || is_realm_world= (); } =20 static DEFINE_MUTEX(pgtable_split_lock); -static bool linear_map_requires_bbml2; +static bool linear_map_requires_bbml3; =20 int split_kernel_leaf_mapping(unsigned long start, unsigned long end) { @@ -803,15 +803,15 @@ int split_kernel_leaf_mapping(unsigned long start, un= signed long end) * always pte-mapped), we must not go any further because taking the * mutex below may sleep. Do not call force_pte_mapping() here because * it could return a confusing result if called from a secondary cpu - * prior to finalizing caps. Instead, linear_map_requires_bbml2 gives us + * prior to finalizing caps. Instead, linear_map_requires_bbml3 gives us * what we need. */ - if (!linear_map_requires_bbml2 || is_kfence_address((void *)start)) + if (!linear_map_requires_bbml3 || is_kfence_address((void *)start)) return 0; =20 - if (!system_supports_bbml2_noabort()) { + if (!system_supports_bbml3()) { /* - * !BBML2_NOABORT systems should not be trying to change + * BBML3 systems should not be trying to change * permissions on anything that is not pte-mapped in the first * place. Just return early and let the permission change code * raise a warning if not already pte-mapped. @@ -828,7 +828,7 @@ int split_kernel_leaf_mapping(unsigned long start, unsi= gned long end) =20 /* * Boot-time: Started secondary cpus but don't know if they - * support BBML2_NOABORT yet. Can't allow splitting in this + * support BBML3 yet. Can't allow splitting in this * window in case they don't. */ if (WARN_ON(num_online_cpus() > 1)) @@ -934,11 +934,11 @@ static int range_split_to_ptes(unsigned long start, u= nsigned long end, gfp_t gfp return ret; } =20 -u32 idmap_kpti_bbml2_flag; +u32 idmap_kpti_bbml3_flag; =20 -static void __init init_idmap_kpti_bbml2_flag(void) +static void __init init_idmap_kpti_bbml3_flag(void) { - WRITE_ONCE(idmap_kpti_bbml2_flag, 1); + WRITE_ONCE(idmap_kpti_bbml3_flag, 1); /* Must be visible to other CPUs before stop_machine() is called. */ smp_mb(); } @@ -947,7 +947,7 @@ static int __init linear_map_split_to_ptes(void *__unus= ed) { /* * Repainting the linear map must be done by CPU0 (the boot CPU) because - * that's the only CPU that we know supports BBML2. The other CPUs will + * that's the only CPU that we know supports BBML3. The other CPUs will * be held in a waiting area with the idmap active. */ if (!smp_processor_id()) { @@ -960,7 +960,7 @@ static int __init linear_map_split_to_ptes(void *__unus= ed) /* * Wait for all secondary CPUs to be put into the waiting area. */ - smp_cond_load_acquire(&idmap_kpti_bbml2_flag, VAL =3D=3D num_online_cpus= ()); + smp_cond_load_acquire(&idmap_kpti_bbml3_flag, VAL =3D=3D num_online_cpus= ()); =20 /* * Walk all of the linear map [lstart, lend), except the kernel @@ -979,7 +979,7 @@ static int __init linear_map_split_to_ptes(void *__unus= ed) * Relies on dsb in flush_tlb_kernel_range() to avoid reordering * before any page table split operations. */ - WRITE_ONCE(idmap_kpti_bbml2_flag, 0); + WRITE_ONCE(idmap_kpti_bbml3_flag, 0); } else { typedef void (wait_split_fn)(void); extern wait_split_fn wait_linear_map_split_to_ptes; @@ -988,7 +988,7 @@ static int __init linear_map_split_to_ptes(void *__unus= ed) wait_fn =3D (void *)__pa_symbol(wait_linear_map_split_to_ptes); =20 /* - * At least one secondary CPU doesn't support BBML2 so cannot + * At least one secondary CPU doesn't support BBML3 so cannot * tolerate the size of the live mappings changing. So have the * secondary CPUs wait for the boot CPU to make the changes * with the idmap active and init_mm inactive. @@ -1003,8 +1003,8 @@ static int __init linear_map_split_to_ptes(void *__un= used) =20 void __init linear_map_maybe_split_to_ptes(void) { - if (linear_map_requires_bbml2 && !system_supports_bbml2_noabort()) { - init_idmap_kpti_bbml2_flag(); + if (linear_map_requires_bbml3 && !system_supports_bbml3()) { + init_idmap_kpti_bbml3_flag(); stop_machine(linear_map_split_to_ptes, NULL, cpu_online_mask); } } @@ -1127,7 +1127,7 @@ bool arch_kfence_init_pool(void) mutex_unlock(&pgtable_split_lock); =20 /* - * Since the system supports bbml2_noabort, tlb invalidation is not + * Since the system supports bbml3, tlb invalidation is not * required here; the pgtable mappings have been split to pte but larger * entries may safely linger in the TLB. */ @@ -1166,7 +1166,7 @@ static void __init map_mem(void) =20 arm64_kfence_map_pool(); =20 - linear_map_requires_bbml2 =3D !force_pte_mapping() && can_set_direct_map(= ); + linear_map_requires_bbml3 =3D !force_pte_mapping() && can_set_direct_map(= ); =20 if (force_pte_mapping()) flags |=3D NO_BLOCK_MAPPINGS | NO_CONT_MAPPINGS; @@ -1333,7 +1333,7 @@ void __init kpti_install_ng_mappings(void) if (arm64_use_ng_mappings) return; =20 - init_idmap_kpti_bbml2_flag(); + init_idmap_kpti_bbml3_flag(); stop_machine(__kpti_install_ng_mappings, NULL, cpu_online_mask); } =20 @@ -1394,7 +1394,7 @@ void __pi_map_range(phys_addr_t *pte, u64 start, u64 = end, phys_addr_t pa, u64 va_offset); =20 static u8 idmap_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __r= o_after_init, - kpti_bbml2_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_= after_init; + kpti_bbml3_ptes[IDMAP_LEVELS - 1][PAGE_SIZE] __aligned(PAGE_SIZE) __ro_= after_init; =20 static void __init create_idmap(void) { @@ -1406,17 +1406,17 @@ static void __init create_idmap(void) IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); =20 - if (linear_map_requires_bbml2 || + if (linear_map_requires_bbml3 || (IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && !arm64_use_ng_mappings)) { - phys_addr_t pa =3D __pa_symbol(&idmap_kpti_bbml2_flag); + phys_addr_t pa =3D __pa_symbol(&idmap_kpti_bbml3_flag); =20 /* * The KPTI G-to-nG conversion code needs a read-write mapping * of its synchronization flag in the ID map. This is also used * when splitting the linear map to ptes if a secondary CPU - * doesn't support bbml2. + * doesn't support bbml3. */ - ptep =3D __pa_symbol(kpti_bbml2_ptes); + ptep =3D __pa_symbol(kpti_bbml3_ptes); __pi_map_range(&ptep, pa, pa + sizeof(u32), pa, PAGE_KERNEL, IDMAP_ROOT_LEVEL, (pte_t *)idmap_pg_dir, false, __phys_to_virt(ptep) - ptep); diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 22866b49be37..f4e4e71a0ea8 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -287,7 +287,7 @@ SYM_TYPED_FUNC_START(idmap_kpti_install_ng_mappings) =20 mov x5, x3 // preserve temp_pte arg mrs swapper_ttb, ttbr1_el1 - adr_l flag_ptr, idmap_kpti_bbml2_flag + adr_l flag_ptr, idmap_kpti_bbml3_flag =20 cbnz cpu, __idmap_kpti_secondary =20 @@ -445,7 +445,7 @@ SYM_TYPED_FUNC_START(wait_linear_map_split_to_ptes) flag_ptr .req x4 =20 mrs swapper_ttb, ttbr1_el1 - adr_l flag_ptr, idmap_kpti_bbml2_flag + adr_l flag_ptr, idmap_kpti_bbml3_flag __idmap_cpu_set_reserved_ttbr1 x16, x17 =20 scondary_cpu_wait: diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 9b85a84f6fd4..c05371365d14 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -14,6 +14,7 @@ HAS_ADDRESS_AUTH_ARCH_QARMA5 HAS_ADDRESS_AUTH_IMP_DEF HAS_AMU_EXTN HAS_ARMv8_4_TTL +HAS_BBML3 HAS_CACHE_DIC HAS_CACHE_IDC HAS_CNP @@ -51,7 +52,6 @@ HAS_LS64_V HAS_LSUI HAS_MOPS HAS_NESTED_VIRT -HAS_BBML2_NOABORT HAS_PAN HAS_PMUV3 HAS_S1PIE --=20 2.43.0 From nobody Sat Jul 25 18:01:40 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B32C93B38AB for ; Wed, 15 Jul 2026 05:34:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093695; cv=none; b=VD3Tx2FEXB68cTxwWYTCSXX14uTB1qbPb30+SRsjZ7kaDj6BMLF1xhVS21eXZhfyz2AfIE7UwbPzf8cOD0xXdVL5jdjKhbXyB0A5R8oXdfMkbnBpoX+iGgbQpuHKfDM6jUYcnZUbNY25bcxAw20sBRai/lnXrYUqgZWMU5Xo4EY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784093695; c=relaxed/simple; bh=xvWUwM25jkFsnNcI43QGqVVl3Rwv1/DjKc78I+lBWqM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OnqZlQtgIcevLCPFfy+ovQYfgDXM0i7+6nnCgFdoAFQzE8ptBJ+mrpWGgb4K2veFRnPQCXbunGEfOkMr2WcwvLlwvB0/rliuCX8GSZuFdwfYNchnsenR1J3HR0FhfWhmJoJjmMRXkJR8EVquC5eSKpMMn9GOtoCfsGppML/ZmRw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=G6wCkvGs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="G6wCkvGs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6B109339; Tue, 14 Jul 2026 22:34:48 -0700 (PDT) Received: from a079125.blr.arm.com (a079125.arm.com [10.164.21.43]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 470B03F915; Tue, 14 Jul 2026 22:34:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784093692; bh=xvWUwM25jkFsnNcI43QGqVVl3Rwv1/DjKc78I+lBWqM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=G6wCkvGskLePoHKA/n5nuizoDjgIdhGsDiSi3elStoMYQC4zdex8jP1EUeY+hP31m rsG3ez2hhDTlfLx2R3dkI5F0z8/ftZMguLrkAmRQuXKzhjTE9hyjVEvv61G5jRtSc4 qCo7QfHply7l6I7LieH2S16Taxc2vrr3MgB6COVo= From: Linu Cherian To: Catalin Marinas , Will Deacon , Ryan Roberts , Kevin Brodsky , Anshuman Khandual , Suzuki K Poulose , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Linu Cherian Subject: [PATCH v3 6/6] arm64: cpufeature: Detect BBML3 based on ID_AA64MMFR2_EL1.BBM Date: Wed, 15 Jul 2026 11:04:08 +0530 Message-ID: <20260715053408.1950475-7-linu.cherian@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260715053408.1950475-1-linu.cherian@arm.com> References: <20260715053408.1950475-1-linu.cherian@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add ID_AA64MMFR2_EL1.BBM based BBML3 feature detection in cpu_supports_bbml3() so that cpus with the feature would not have to be added into MIDR based supports_bbml3_list. Signed-off-by: Linu Cherian Reviewed-by: Anshuman Khandual Reviewed-by: Gavin Shan --- arch/arm64/kernel/cpufeature.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 25a705e02618..b58fdcb35406 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2133,6 +2133,12 @@ static bool hvhe_possible(const struct arm64_cpu_cap= abilities *entry, =20 bool cpu_supports_bbml3(void) { + u64 mmfr2; + + mmfr2 =3D __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1); + if (SYS_FIELD_GET(ID_AA64MMFR2_EL1, BBM, mmfr2) >=3D ID_AA64MMFR2_EL1_BBM= _3) + return true; + /* CPUs that support BBML3 but dont advertise through MMFR2 ID */ static const struct midr_range supports_bbml3_list[] =3D { MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), @@ -2154,15 +2160,10 @@ bool cpu_supports_bbml3(void) {} }; =20 - if (!is_midr_in_range_list(supports_bbml3_list)) - return false; - - /* - * We currently ignore the ID_AA64MMFR2_EL1 register, and only care - * about whether the MIDR check passes. - */ + if (is_midr_in_range_list(supports_bbml3_list)) + return true; =20 - return true; + return false; } =20 static bool has_bbml3(const struct arm64_cpu_capabilities *caps, int scope) --=20 2.43.0