From nobody Sat Jul 25 18:06:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B2509331A57; Wed, 15 Jul 2026 07:07:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099253; cv=none; b=Alw16erw07ft6Z71oKtSgyA9psnci2QrXJyh7jn7fJKRdlHM4/W1rjCxTYKuppBHq/Nx6ldHyfeypz7malqvKWHnklRz1eDmdEXITPZSWVBJbEaUvespAPqNhZ7l6jcQRouuKqa93LDBQaAWGZQKrlzI8qc4vh/cwZ0hS2wsmXI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099253; c=relaxed/simple; bh=kwSTb1nva9AqjRKglnBgdgDIqGsu9278QfIcqtMqZWQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eZNoT9xKuuBTh7nd1+6POB9z2AI0IaPfdKEiD3GSCa4xKeXYTG5U/eCN/wbVNWiVwsPEzPTNcyPQ2bqAGF3vmVde6HHlnZ9T/MD7cFgUvTx17CSwvnxzLTnylWpLT+wLCdCI0mXLQ34o7aHnjzASmLbZXOLgvC+08tbf8MfH/Hk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=YC5etZrh; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="YC5etZrh" Received: by smtp.kernel.org (Postfix) with ESMTPS id 173B2C2BCB7; Wed, 15 Jul 2026 07:07:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784099252; bh=kwSTb1nva9AqjRKglnBgdgDIqGsu9278QfIcqtMqZWQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=YC5etZrhi2xD4mYXYs6XuaVFPf/YnSXIMu22KfR3BoSn8/Ur9jOdZGZR29FDjrYz6 AT2xCwzI2/MpcYbyw9Y2XRM7dTSxFsaMKptr8VUd9+EKsoqpbYe1qwGILkI6H2Uwxb ngd1cYwAFqe/OMZ6YPYP2cprn8fQurkfZj9Cm5JyJQAMeoisf649155TnCeh69LOkb 3BHelL0Rm1w+xaRzU1hASZitz0IikZMxoktXaheG0u0YHb2uAN9a1UhaMD+EIabW7y XCyXpvr0XRzSQiWTHwRQjlNyA/tpheVb5NcIju50uvgmTzf0w6CBQgd73svtHqsxsa it5Yj4l3UxI6w== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB6EFC44501; Wed, 15 Jul 2026 07:07:31 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Wed, 15 Jul 2026 03:06:54 -0400 Subject: [PATCH v2 1/3] dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add SM8475 QMP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-sm8475-bup-usbss-v2-1-2d8def39b190@proton.me> References: <20260715-sm8475-bup-usbss-v2-0-2d8def39b190@proton.me> In-Reply-To: <20260715-sm8475-bup-usbss-v2-0-2d8def39b190@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784099250; l=1009; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=QlalgE8PWhdVYi02z66OWZNjDEJrjwh3NQS1V1WaGAA=; b=haiZVjCw4UMBIhhGef/d6rYQcIN7xtQNJYyQBDGCMzWTSkX0t+Pfa2AFhaa88DHjjmcO8/7LP bpF+CLIGhzkBP0diV2HaR7/ft6UFUW9fACwNa5qUw/A3xAvC5Dtu7z5 X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia SM8450 init sequence for this PHY varies significantly and can't be used in SM8475. Add bindings for the PHY found in this SoC. Signed-off-by: Esteban Urrutia Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml index 4eff92343ce4..b9d0de25f43c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml @@ -37,6 +37,7 @@ properties: - qcom,sm8250-qmp-usb3-dp-phy - qcom,sm8350-qmp-usb3-dp-phy - qcom,sm8450-qmp-usb3-dp-phy + - qcom,sm8475-qmp-usb3-dp-phy - qcom,sm8550-qmp-usb3-dp-phy - qcom,sm8650-qmp-usb3-dp-phy - qcom,sm8750-qmp-usb3-dp-phy --=20 2.55.0 From nobody Sat Jul 25 18:06:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A80D1331EAE; Wed, 15 Jul 2026 07:07:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099254; cv=none; b=Qoqal70P6wzPSN1ut4veMtM2TJ1wFuarHdL0KwLjS/GbGKqfA+e3bMbyfqe0qqgjzoIQzkvgdNfeQB6TSW+oMr+hK8qfsaKvKkEY+SRf8bYOKkmrIHz6kw8xGRf+2/0tKz0wbwDr5JJww52H20XN3pUZrjzw7Mhvn0UWc9Y233g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099254; c=relaxed/simple; bh=FDpYnwRtmcbV17Q4xx73jxmEu1o34piLsbK8kMgW2H8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oKHiwNpfZLbbKuXwWb0drctqJY7y/xj0OHM2joCtAhp4BEgchfCdTSNvYaIZzrEQgx52dtyguyeZwINHGv46iPjUZFunydcImQnf6zOHfkzNAypbwxw2cROQfaBO4FrpgJ/Uz/mhTC/GIKSfac/7LvDd2MLirWcyOCFEbR5xh14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V2ORq5Om; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V2ORq5Om" Received: by smtp.kernel.org (Postfix) with ESMTPS id 30082C2BCC7; Wed, 15 Jul 2026 07:07:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784099252; bh=FDpYnwRtmcbV17Q4xx73jxmEu1o34piLsbK8kMgW2H8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=V2ORq5OmROZq/MutKakFVnnOOgVd+eYkBVdEQtvG2IzQ4QH7AmK+CNgMdw0ffngFP DBlHWWQ7KDF4vznX/Gdd1B5+DxCl99Fk6hdOjqpbF5ylUrK9SDMNS/VHSZSHcyNXiJ F8CelbaNU1NRdsHqpAJIZS6CtsU713KUeHFNX+AxlAnVsRYeEmA5dYuOb/W+ZLPItp Z9ti4lP1FImOHpzgMMrXhbpwZ0hQzZFxqXB9eJt+Z1mszUszICgXkfn53WjAs9lepH bN+XKCtQN+G4+pXoXrB1iOTxGYIg7tymPJu+v+Ay4l839aO92+6S4yE5drbwTbOgwe ly+143NWqxjVw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02BCFC4450F; Wed, 15 Jul 2026 07:07:32 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Wed, 15 Jul 2026 03:06:55 -0400 Subject: [PATCH v2 2/3] phy: qcom: qmp-combo: Specify PLL version in qmp_v6_dp_serdes_tbl structs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-sm8475-bup-usbss-v2-2-2d8def39b190@proton.me> References: <20260715-sm8475-bup-usbss-v2-0-2d8def39b190@proton.me> In-Reply-To: <20260715-sm8475-bup-usbss-v2-0-2d8def39b190@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784099250; l=9527; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=xM+iYx47hDJsnpSr2d5T8wt7Tbc8+U5gc/fVbCObSpg=; b=dpSwwbXivqqU+bDPWgA3zyKaYt0JIRtkKAGQsEXRLCG76OsgoZoeF6Eb2oIXq+g1WvDIFT4N9 REGyOXwOORcCYDqkpgV5yuf4WHCNl7orZtQGDt2w9q0Jo2e9XSdCqbd X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia Two versions of PLLs for v6 PHYs exist: v1 and v1.1. These tables only cover v1.1 PLLs. For serdes, the difference between v1 and v1.1 PLLs is the value written to the BG_TIMER register. This register is set to 0x0e for v1 PLLs and 0x0a for v1.1 PLLs. As reference, SM8550 and SM8650 SoCs use v1.1 PLLs. For RBR/HBR/HBR2/HBR3, most values change. Make this distinction clear to avoid confusion when adding support for SoCs making use of v1 PLLs. Signed-off-by: Esteban Urrutia --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 90 +++++++++++++++------------= ---- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 9bd666ac2c49..36361ac02855 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1337,7 +1337,7 @@ static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx= _tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), @@ -1471,7 +1471,7 @@ static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_tx= _tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET, 0x10), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), @@ -1483,7 +1483,7 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes= _tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), @@ -1495,7 +1495,7 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes= _tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), @@ -1507,7 +1507,7 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes= _tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), @@ -2442,19 +2442,19 @@ static const struct qmp_phy_cfg sar2130p_usb3dpphy_= cfg =3D { .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v5_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, @@ -2852,19 +2852,19 @@ static const struct qmp_phy_cfg sm8550_usb3dpphy_cf= g =3D { .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v5_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, @@ -2897,19 +2897,19 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cf= g =3D { .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v6_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, @@ -2942,19 +2942,19 @@ static const struct qmp_phy_cfg sm8750_usb3dpphy_cf= g =3D { .pcs_usb_tbl =3D sm8750_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v6_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, --=20 2.55.0 From nobody Sat Jul 25 18:06:53 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B25EA331EBB; Wed, 15 Jul 2026 07:07:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784099253; cv=none; b=bS4/kq7MEB98jAHQhRDdHz8/WCbKf3c1WBNKLedqWe8st1pumlkcdIaXYaLxbAOEH48RAntV0YaVRwUG2fLySONBacyHp9wOthF4k612TagRDz7PBx2KmOHPQFlTMIugMjVaohFIgl2QePutF6eYTs4amyhpS5X3jXoG0uNoewc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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b=twRpdbStknLgIi9QTGMLNHdqWAY7uxzyfVXn7JQw1OzjKNe6aun2Mw1vRa6o3so1I IbQbtUDLO3mZmAofNyLjkxokZcaSNW/FQ/aaMrt1dTI7//O/yxXP0oDhW9va5UAZsg DJIQifukUPpOy+uNFwiRRojw1zwWUv7hMjR+pQUyNChzXwX3KXUvuswpxVSZWeVDUc kifAtgs294dDpuZXTFcEukKN94rL2HF/dd4AnevIB0IVGHoIzBmCgj/Yj1Ro6USLZy MVDGFlTVBtM+/WOJHDwxChkhkBjfm6S+FqYNCECHjNsj0gLpBgSxebnEyaOE3a6ftn bShwBEGQOgERA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D944C4450C; Wed, 15 Jul 2026 07:07:32 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Wed, 15 Jul 2026 03:06:56 -0400 Subject: [PATCH v2 3/3] phy: qcom: qmp-combo: Add SM8475 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-sm8475-bup-usbss-v2-3-2d8def39b190@proton.me> References: <20260715-sm8475-bup-usbss-v2-0-2d8def39b190@proton.me> In-Reply-To: <20260715-sm8475-bup-usbss-v2-0-2d8def39b190@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784099250; l=10839; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=BURT4AAw0Xx8A6vxbxhEi8B5tPnumv/tHBWqVQYyXp8=; b=U7vcYax2zZkDVJo41e5CKkOA2kXsTlEsX4aIK3BNxCW9risBpg5A5F7KYS4LwZrVK8FnZ39nv 5glvaDECqATAOJlJ+pfu7mV6GdYoFtzlveHt5UZixK+wa2F1rW3vKYt X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia Has been tested with the following capabilities: - USB Type-C at 10Gb/s - DP Alt Mode, using HBR2 - USB Type-C at 480Mb/s + DP Alt Mode, using HBR2 RX and PCS USB tables had to be added, while serdes, TX and PCS tables were reused from other SoCs. Since SM8475 uses a v1 PLL, add and use v1 PLL tables as well. Signed-off-by: Esteban Urrutia --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 169 ++++++++++++++++++++++++++= ++++ 1 file changed, 169 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 36361ac02855..6028752aaac1 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1063,6 +1063,55 @@ static const struct qmp_phy_init_tbl sm8350_usb3_pcs= _usb_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), }; =20 +static const struct qmp_phy_init_tbl sm8475_usb3_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_phy_init_tbl sm8475_usb3_pcs_usb_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), +}; + static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), @@ -1337,6 +1386,29 @@ static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_t= x_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), }; =20 +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), +}; + static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), @@ -1471,6 +1543,54 @@ static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_t= x_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET, 0x10), }; =20 +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_rbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr2[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x2e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x21), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr3[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), +}; + static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), @@ -2838,6 +2958,51 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg= =3D { .has_pwrdn_delay =3D true, }; =20 +static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg =3D { + .offsets =3D &qmp_combo_offsets_v3, + + .serdes_tbl =3D sar2130p_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sar2130p_usb3_serdes_tbl), + .tx_tbl =3D sm8550_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8550_usb3_tx_tbl), + .rx_tbl =3D sm8475_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8475_usb3_rx_tbl), + .pcs_tbl =3D sm8550_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_tbl), + .pcs_usb_tbl =3D sm8475_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8475_usb3_pcs_usb_tbl), + + .dp_serdes_tbl =3D qmp_v6_dp_v1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl), + .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), + + .serdes_tbl_rbr =3D qmp_v6_dp_v1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr3), + + .swing_hbr_rbr =3D &qmp_dp_v5_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 =3D &qmp_dp_v5_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v5_pre_emphasis_hbr3_hbr2, + + .dp_aux_init =3D qmp_v4_dp_aux_init, + .configure_dp_tx =3D qmp_v4_configure_dp_tx, + .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, + .configure_dp_phy =3D qmp_v4_configure_dp_phy, + + .regs =3D qmp_v6_usb3phy_regs_layout, + .reset_list =3D msm8996_usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), +}; + static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg =3D { .offsets =3D &qmp_combo_offsets_v3, =20 @@ -5001,6 +5166,10 @@ static const struct of_device_id qmp_combo_of_match_= table[] =3D { .compatible =3D "qcom,sm8450-qmp-usb3-dp-phy", .data =3D &sm8350_usb3dpphy_cfg, }, + { + .compatible =3D "qcom,sm8475-qmp-usb3-dp-phy", + .data =3D &sm8475_usb3dpphy_cfg, + }, { .compatible =3D "qcom,sm8550-qmp-usb3-dp-phy", .data =3D &sm8550_usb3dpphy_cfg, --=20 2.55.0