From nobody Sat Jul 25 18:08:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71D0A3128C6; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097547; cv=none; b=CCLh4AVJfIbwEq07qavF/pdGvCIzKrZt6S6xLZ4ak4Nh9ftKCLRMW2PPBdfXXrvvIA0nQy8aLplkSdyhjSq9sMjBgGdfgf/88TX3h+dML4Kbd3PBvgp1UPmhFbLi3hZfkKu9D1e0OgNUPA7ueSAMgurPh5MwzMuITAjOLjuqZhs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097547; c=relaxed/simple; bh=M0RTFSLiMdB54hWo7CvBKBA6KLRs2mkAXPGv9anQlng=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=W2txtVLdikOAtKbuCk4HD5OQRsGreHQ817YVGkfKfLjZXVS4lovN+3mz10+XDb0xc3gY3IuwE/5odb+sZFBxb+HP7GXh0ID1XhsMqwcjgrnhbeBXq5PzHw/QVQPRWZyZhXl3VNEkxU0KqzBm7eghDqpL0WFXe/M3mSoJTFpJvC4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qJSONXgf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qJSONXgf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 31535C2BCB9; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784097547; bh=M0RTFSLiMdB54hWo7CvBKBA6KLRs2mkAXPGv9anQlng=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=qJSONXgfXbNlP07tVpFRBvOk07ykv/vCPJ6/ekZRVep77WO+WxNEodW9U4irgfAN7 X9j8AXEowKoJ9ewfgIA7szAJ7mbhdllqyir5kntB/6ZzKQYX8IxA2cMuVPtb7sUfGR CCDEwLl7OWcsXBVqoQCfI+vpc1rSgrOn8/illHWwSvGHX0HpswaPCAW2Fh0eZY9R6H cgHOdBKClxrxF41vtkDOljwwmPii6EK96hEq49bmSzSDDAOa+rKVPhCKFKE+0rQGXt pNj0owRYRHIOpJSBT4NdhVOthXAitkpsGsUH23RlcXGROR3dnxtvlR/sXhisJnmmKn e2QImjjB43s9g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0763FC44508; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Wed, 15 Jul 2026 02:37:46 -0400 Subject: [PATCH v2 1/3] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-sm8475-bup-pcie-v2-1-48bd91a19abf@proton.me> References: <20260715-sm8475-bup-pcie-v2-0-48bd91a19abf@proton.me> In-Reply-To: <20260715-sm8475-bup-pcie-v2-0-48bd91a19abf@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784097545; l=1376; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=bLFIXxi0mjZfBPT4pjXHMUjEF5YF+fmxsIeBl21k8TQ=; b=4S6iTuTNBIWEcmltrDDzXdRp+F20EuVr2wpwnU32oM/Ftv7u8FHqHd2YAQmX6UmIZQx81MSQF jTTJEIqnC48BGyWMkAONFDoQEbMSRYoiC/Y1VgRCYRhmyLeZH7nHQy5 X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia SM8450 init sequence for this PHY varies significantly and can't be reused in SM8475. Add bindings for the PHY found in this SoC. Signed-off-by: Esteban Urrutia Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 = ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 108cf9dc86ea..8850d5ebac03 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -43,6 +43,7 @@ properties: - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy @@ -175,6 +176,7 @@ allOf: - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy --=20 2.55.0 From nobody Sat Jul 25 18:08:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71C85225413; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097547; cv=none; b=JQX5QWdWCMVo4KUNjhdzFXF6MkIUt3F1HqPYePN0XbF/c6chgplXj8eO9TtzgC2kVLazwizUEEUuG3QS1FKMCB5bFkN8MKc37kVycZGBFjYq88dc1f6MLZz+t+R7kbgFeFwjwnzYuM1ndhn/7vxQkcQQBPdL3Ifxk9wBlOWTNfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097547; c=relaxed/simple; bh=ZliAQFFvr5pZ/nRwHOArDixoFaosYB2/I8lhndxTcO4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=eM2wHBKQLxIVAqDX+i4KHDGIMoTnAmFPolpUdIvoLLIS2fa3/1/59Sf6LQandvl0Dnz6P945AmvLiatFb9S26fDqNxQglPxe6wHPUj3iFcicGOB6IUkkmW+D8AH20pe1Ng84Z6rVtplP3RETgSWqHvaCAK7sx8XjyNuxECumxNI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=XuBLs7o4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="XuBLs7o4" Received: by smtp.kernel.org (Postfix) with ESMTPS id 3D8E9C2BCF7; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784097547; bh=ZliAQFFvr5pZ/nRwHOArDixoFaosYB2/I8lhndxTcO4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=XuBLs7o4CL23nn1O1knTTwUrQNedp41ImJhFYeBSKYo/MEj6MsKAWpTvTU12dQeGg ES1hcJ/9f6DYy7AAaIhoFqXzbVbz3Of885UsjDgHDAYN/JOE7bQ7kzvj8oT4s0uLBY masHnbdCe4kdb6MLWq5gRrTuVG0ySp7iCeVFZ0qoh9RVZqn4rTakqNA7+LrS1yuEWL jtZO7o8N+yyUu9XeaeB09pma+fc7z/62Fzxd+epeFup9+PdjaXCfKZJe4kBjjlxv/E g5YOLLszlKs9I0v6GPgfmvxTBvGeq8tDG5jtKtJ1897Qyt3QPQ0hsRV+T6vP4F4j2Q zFJ655PtTpgvA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17ABEC4450C; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Wed, 15 Jul 2026 02:37:47 -0400 Subject: [PATCH v2 2/3] phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-sm8475-bup-pcie-v2-2-48bd91a19abf@proton.me> References: <20260715-sm8475-bup-pcie-v2-0-48bd91a19abf@proton.me> In-Reply-To: <20260715-sm8475-bup-pcie-v2-0-48bd91a19abf@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784097545; l=762; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=XC8XSPTDRd/J/fHeOOhg0qB32EBC0liAXwtSxQB2wb4=; b=IE/Rciw/Vjeo3WceGDwW4nbymkrPBOEhmNgrYZr9XbTFxU6yq6Y9SNl3eBTGc0eDDuJvU0qWQ KS3JCMULfmeDow5fGhP4pF8stWe0EwJowvrk8CjQRXAJXVyeQx61EVz X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia Some SoCs such as SM8475 write data to registers using this offset, specifically SW_CTRL2 and MX_CTRL2. Add pcs_lane1 offset to V5 offsets to support this. Signed-off-by: Esteban Urrutia Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index d3effad7a074..3618812e84d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3554,6 +3554,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets= _v5 =3D { .pcs_misc =3D 0x0600, .tx =3D 0x0e00, .rx =3D 0x1000, + .pcs_lane1 =3D 0x1400, .tx2 =3D 0x1600, .rx2 =3D 0x1800, }; --=20 2.55.0 From nobody Sat Jul 25 18:08:48 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 744B0314D1F; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097547; cv=none; b=QVA/pnCkz9ufXlspY4kLrfRkI0celFqftF11KHn17O2SirAVrvaYcrbE/kQNDRoNSI9RB/ux0qei9Y4rN1Eq2G5jufukHtXQaLUZGsda0YYqQlUheiHfL8RoOhuvHHdFIusy/TStZgXJbLwa9YQP1yNalts3v0usmgvEQBFFK1o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784097547; c=relaxed/simple; bh=KNtoNOSTQHj4aRQJjaJ4F7cGHmEF2GRyW0HKh7XpJB0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Oad2vq6xSmfLiXy3oE+JQjTAyvu+vaOLOlIsC3fd2953drt2g+SORGjL+4mk4lqYM5JrW/goudQF6pnLUhSnrs+vvQlL9eIWzaXikhbkR818/I+Z4KprVGdq/g10hrHqmlGmRGIrT6kd3VaCCeVcynGa7XB9az7Yqz+sm7ucJaE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=iJKk5L1q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="iJKk5L1q" Received: by smtp.kernel.org (Postfix) with ESMTPS id 41F32C2BCFA; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784097547; bh=KNtoNOSTQHj4aRQJjaJ4F7cGHmEF2GRyW0HKh7XpJB0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=iJKk5L1qmIwTMBZrbii+CPlpvdNOJ6CVh4yzv3M0es5eUuozltFvCWKwCQIBpWhzD 9zTN+510jy5aOAu2Q4YA3IAXaxc2NlcYNjedZuixX3m0ErN8eM0SbA3Gf6BaHMwWQV Ssv+RD0NkqjQsEUOZpxGftINd9hBsbeM5u4EcEcc7LRyt3NWeA7zm10tLcdVULoqxY b6vn2XnBWy5myYytjHALWHWmRTx89lAqJ2o1ficEAgb/u/cBNsrWqIQ+44GFmXKreL oFSqYgUH6R6SMgd0A8wbFqOYaRUVnDk8ecuCcIqIzqy6CF0/SGjNJ3nf64gncjyRns XZC0WbZHO+6bQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B888C4450B; Wed, 15 Jul 2026 06:39:07 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Wed, 15 Jul 2026 02:37:48 -0400 Subject: [PATCH v2 3/3] phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-sm8475-bup-pcie-v2-3-48bd91a19abf@proton.me> References: <20260715-sm8475-bup-pcie-v2-0-48bd91a19abf@proton.me> In-Reply-To: <20260715-sm8475-bup-pcie-v2-0-48bd91a19abf@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784097545; l=6969; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=mHgoeOun6fcq+EMdXgLO95Oi1B+m8pBC9oBPCl3AEFE=; b=zarLZZgGzOeEbOXUeuphFAbOlhoFJmmNm40VCXilZmcSkly4+nZJBdkR4XVj5lRlCcIxGOzET 8DxWVHsgfuZAqqowr4mQw+DWvxCk4J1YCriIjWiVenZzX5fjWsSLK89 X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia This gets the port working. Tested with WCN6856 WLAN capabilities. Serdes, RX and PCS Misc tables had to be added, while TX and PCS tables were reused from SM8550, and PCS Lane1 was reused from SAR2130P. Signed-off-by: Esteban Urrutia Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 108 +++++++++++++++++++++++++++= ++++ 1 file changed, 108 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 3618812e84d5..47d7196460ee 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2454,6 +2454,82 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4= x2_pcie_ep_pcs_misc_tbl[] =3D QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), }; =20 +static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_serdes_tbl[] = =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_pcs_misc_tbl[]= =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), @@ -4406,6 +4482,35 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pc= iephy_cfg =3D { .aux_clock_rate =3D 20000000, }; =20 +static const struct qmp_phy_cfg sm8475_qmp_gen3x1_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_v5, + + .tbls =3D { + .serdes =3D sm8475_qmp_gen3x1_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_serdes_tbl), + .tx =3D sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx =3D sm8475_qmp_gen3x1_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_rx_tbl), + .pcs =3D sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc =3D sm8475_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_pcs_misc_tbl), + .pcs_lane1 =3D sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, + .pcs_lane1_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v6_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg =3D { .lanes =3D 2, =20 @@ -5631,6 +5736,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,sm8450-qmp-gen4x2-pcie-phy", .data =3D &sm8450_qmp_gen4x2_pciephy_cfg, + }, { + .compatible =3D "qcom,sm8475-qmp-gen3x1-pcie-phy", + .data =3D &sm8475_qmp_gen3x1_pciephy_cfg, }, { .compatible =3D "qcom,sm8550-qmp-gen3x2-pcie-phy", .data =3D &sm8550_qmp_gen3x2_pciephy_cfg, --=20 2.55.0