From nobody Sat Jul 25 18:54:12 2026 Received: from us.padl.com (us.padl.com [216.154.215.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1EFE435530; Tue, 14 Jul 2026 23:30:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.154.215.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784071804; cv=none; b=A2YA6zY4ppEg4sOAaEAR6ED1d1RMaURBd1HeEOjxCv48padOtGyT8tkf0Td0OhpsKuZdjL9+okdyFMhhIt9ShojCU6mzb61pUBmPznDpbluvrvmDhcm4smmzZfK+SEVsRWJiVHsi4xuYb4KyzZ8GDojetSRzawmzEKes3ekdNX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784071804; c=relaxed/simple; bh=1tgVA/S6BsdDQgVSNZZ0wBTm+kotMhPUlsrZqxAa5Y0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=iYDrHeUbyPkF+9fEuaiAoNF0QWNpO2hfJcTB+O/VjN8A0vG7MOtHhvuj3Oimk+eQrPosAJE/i6a1psGZmNZuxHJ2nA1cOlg4ICmP2TEYu7VfeyKzhlzgWc6awNkCzTkGlLQcEJLPFHB22T+lbEiAI8DfvwflzHg4D8GP4O8B/Oo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=padl.com; spf=pass smtp.mailfrom=padl.com; dkim=pass (2048-bit key) header.d=padl.com header.i=@padl.com header.b=Nk332/j0; arc=none smtp.client-ip=216.154.215.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=padl.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=padl.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=padl.com header.i=@padl.com header.b="Nk332/j0" Received: from [127.0.1.1] (border.lukktone.com [139.130.100.52]) by us.padl.com (Postfix) with ESMTPSA id D48A860D3C; Tue, 14 Jul 2026 19:29:51 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=padl.com; s=default; t=1784071795; bh=LyGpKfgTEhM2g/vwEavRerpfkyM31GgXBro05X4cAX4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Nk332/j0SYHc5CQh3jftLhe/idDvfTsLtoCMIClgNr/qsIeqtgg6kPfxGk5R2iO+q Ix6I7a47yAyAwtjuL8sgZsFERmjH99xN6seY7f4yQM6ORQPU6bCMY5CFxj1wFLYF9A DjEh4/uxdlKiI2BMWLvOVkPX+c3E624WWpKqyQqu2oO36+JTT/Re16gCP3MWZ7XSgh NscqfJw1DyRC+dnTFXx6LruXDDIJdQ28m5wINWy3vSkGnPXmyoZwyc0xADxCyCHy/2 l3V+JzsgKKZjdE0mgPc5Akbobt1LuQLcBSCvRk5ycVAbl+PRqkiEjIAl2tl+uDz4lR L7YvxoGu4DDvQ== From: Luke Howard Date: Wed, 15 Jul 2026 09:29:41 +1000 Subject: [PATCH net v3 1/3] net: dsa: mv88e6xxx: write the ATU FID register on 88E6141/88E6341 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-mv88e6x41-fixes-v3-1-9a8702b27ecc@padl.com> References: <20260715-mv88e6x41-fixes-v3-0-9a8702b27ecc@padl.com> In-Reply-To: <20260715-mv88e6x41-fixes-v3-0-9a8702b27ecc@padl.com> To: Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vivien Didelot , Gregory CLEMENT , Andrew Lunn , Richard Cochran Cc: Cedric Jehasse , Kieran Tyrrell , Max Holtmann , Max Hunter , Christoph Mellauner , Simon Gapp , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Luke Howard X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784071787; l=10235; i=lukeh@padl.com; s=20260701; h=from:subject:message-id; bh=1tgVA/S6BsdDQgVSNZZ0wBTm+kotMhPUlsrZqxAa5Y0=; b=885jrRxyFv8nQ7uiFjgB0c1ce4/nOw8EhkwHLG/v/6iDsfQ2Ai1g/ymbqrRMozA7KGl7w2+3x NAXpLIXV1xwCSdeO4tPBQo8FfKC4HhixXxJVoNYicgbA+liP7/CoFLt X-Developer-Key: i=lukeh@padl.com; a=ed25519; pk=D6YgUnH9/OzSZsduYm9XDbvXn1IHDwKwI1hLTsKNRLw= The driver decided whether a device has a dedicated ATU FID register from its database count, taking the register path only when there were more than 256 databases. The 88E6141/88E6341 have 256 databases but do have the register, so they fell back to the legacy path and the FID register was never written. Every FDB entry was then loaded into FID 0, breaking VLAN aware bridging. The number of databases does not imply whether the register is present. Add an explicit atu_fid_reg flag, set it on every device that has the register (all that previously matched the >256 heuristic, plus the 88E6141/88E6341), and key the register access off the flag instead of the database count. Fixes: a75961d0ebfd ("net: dsa: mv88e6xxx: Add support for ethernet switch = 88E6341") Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Luke Howard Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/chip.c | 27 +++++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 3 +++ drivers/net/dsa/mv88e6xxx/global1_atu.c | 4 ++-- 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 80b877c74513d..7938e50900ca8 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -5747,6 +5747,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6097, .name =3D "Marvell 88E6085", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 10, .num_internal_phys =3D 5, @@ -5792,6 +5793,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6097, .name =3D "Marvell 88E6097/88E6097F", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 11, .num_internal_phys =3D 8, @@ -5817,6 +5819,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6165, .name =3D "Marvell 88E6123", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 1024, .num_ports =3D 3, .num_internal_phys =3D 5, @@ -5863,6 +5866,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6341, .name =3D "Marvell 88E6141", .num_databases =3D 256, + .atu_fid_reg =3D true, .num_macs =3D 2048, .num_ports =3D 6, .num_internal_phys =3D 5, @@ -5889,6 +5893,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6165, .name =3D "Marvell 88E6161", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 1024, .num_ports =3D 6, .num_internal_phys =3D 5, @@ -5915,6 +5920,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6165, .name =3D "Marvell 88E6165", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 6, .num_internal_phys =3D 0, @@ -5940,6 +5946,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6351, .name =3D "Marvell 88E6171", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -5965,6 +5972,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6352, .name =3D "Marvell 88E6172", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -5991,6 +5999,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6351, .name =3D "Marvell 88E6175", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -6016,6 +6025,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6352, .name =3D "Marvell 88E6176", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -6064,6 +6074,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6390, .name =3D "Marvell 88E6190", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 16384, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, @@ -6089,6 +6100,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6390, .name =3D "Marvell 88E6190X", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 16384, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, @@ -6114,6 +6126,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6390, .name =3D "Marvell 88E6191", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 16384, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, @@ -6139,6 +6152,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6393, .name =3D "Marvell 88E6191X", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 8, .internal_phys_offset =3D 1, @@ -6164,6 +6178,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6393, .name =3D "Marvell 88E6193X", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 8, .num_tcam_entries =3D 256, @@ -6218,6 +6233,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6352, .name =3D "Marvell 88E6240", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -6267,6 +6283,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6390, .name =3D "Marvell 88E6290", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, .num_gpio =3D 16, @@ -6294,6 +6311,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6320, .name =3D "Marvell 88E6320", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 2, @@ -6322,6 +6340,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6320, .name =3D "Marvell 88E6321", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 2, @@ -6350,6 +6369,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6341, .name =3D "Marvell 88E6341", .num_databases =3D 256, + .atu_fid_reg =3D true, .num_macs =3D 2048, .num_internal_phys =3D 5, .num_ports =3D 6, @@ -6377,6 +6397,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6351, .name =3D "Marvell 88E6350", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -6402,6 +6423,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6351, .name =3D "Marvell 88E6351", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -6427,6 +6449,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6352, .name =3D "Marvell 88E6352", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 8192, .num_ports =3D 7, .num_internal_phys =3D 5, @@ -6453,6 +6476,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6393, .name =3D "Marvell 88E6361", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 16384, .num_ports =3D 11, /* Ports 1, 2 and 8 are not routed */ @@ -6480,6 +6504,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6390, .name =3D "Marvell 88E6390", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 16384, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, @@ -6508,6 +6533,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6390, .name =3D "Marvell 88E6390X", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_macs =3D 16384, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 9, @@ -6535,6 +6561,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = =3D { .family =3D MV88E6XXX_FAMILY_6393, .name =3D "Marvell 88E6393X", .num_databases =3D 4096, + .atu_fid_reg =3D true, .num_ports =3D 11, /* 10 + Z80 */ .num_internal_phys =3D 8, .num_tcam_entries =3D 256, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index e966e7c4cc5de..f1db12b7629bd 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -176,6 +176,9 @@ struct mv88e6xxx_info { /* Supports PTP */ bool ptp_support; =20 + /* Has a dedicated ATU FID register. */ + bool atu_fid_reg; + /* Internal PHY start index. 0 means that internal PHYs range starts at * port 0, 1 means internal PHYs range starts at port 1, etc */ diff --git a/drivers/net/dsa/mv88e6xxx/global1_atu.c b/drivers/net/dsa/mv88= e6xxx/global1_atu.c index c47f068f56b32..522978f638e2f 100644 --- a/drivers/net/dsa/mv88e6xxx/global1_atu.c +++ b/drivers/net/dsa/mv88e6xxx/global1_atu.c @@ -135,7 +135,7 @@ static int mv88e6xxx_g1_atu_op(struct mv88e6xxx_chip *c= hip, u16 fid, u16 op) int err; =20 /* FID bits are dispatched all around gradually as more are supported */ - if (mv88e6xxx_num_databases(chip) > 256) { + if (chip->info->atu_fid_reg) { err =3D mv88e6xxx_g1_atu_fid_write(chip, fid); if (err) return err; @@ -179,7 +179,7 @@ static int mv88e6xxx_g1_atu_fid_read(struct mv88e6xxx_c= hip *chip, u16 *fid) u16 val =3D 0, upper =3D 0, op =3D 0; int err =3D -EOPNOTSUPP; =20 - if (mv88e6xxx_num_databases(chip) > 256) { + if (chip->info->atu_fid_reg) { err =3D mv88e6xxx_g1_read(chip, MV88E6352_G1_ATU_FID, &val); val &=3D 0xfff; if (err) --=20 2.43.0 From nobody Sat Jul 25 18:54:12 2026 Received: from us.padl.com (us.padl.com [216.154.215.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38A4F41D640; Tue, 14 Jul 2026 23:30:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.154.215.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784071803; cv=none; b=flg000XTzJFPuqxTvi5EvfSXBYd7vFow4npUorLGynD9T9asy6obyH3mDlerVbGYOrFHvx0vuoKZbnKynHqpHx90KNdCOgjzbRFe1p3quGL5tBfJsxjiHETP8HLD2zH2U7bHcYoUgB405Qw25D6OtBObjoAVvg+8n79fdGWD7Bs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; 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[139.130.100.52]) by us.padl.com (Postfix) with ESMTPSA id 3968261935; Tue, 14 Jul 2026 19:29:56 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=padl.com; s=default; t=1784071800; bh=vL215MS/8idnecKgyAlKiTcIBe3X1kty3J9/cOedlys=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=aSECAsqu8mMW6e0exBzOI31eD6/P6OwQqS05RFYpHz2riPnJ133/yyopMCjqSLFwC 6UecUaggR0R51e5kjk6aeFu+etl4rwhoDr49qi8NCBNP1o2zCQhXvNKhxwJ8FNIAo+ B+hiY3C10tTFNc57mdVfoP7NRwoTqx7F2ITex3f3+LLZefGNBmxTPok9C/UGe0nIK7 Qc8I4eXlYC7730irQ+iBmkOoHo3bL2ehmbu4IG1IckEqvSNPquELHxGzbKXw1tBkSr IQM2Nspxp2FOsJwVYkUt17nXgkRkYDfhsV843rSBfJt4HZZl57/iLMI6PtR3RdyqDY hYPrZ/5xYwzxg== From: Luke Howard Date: Wed, 15 Jul 2026 09:29:42 +1000 Subject: [PATCH net v3 2/3] net: dsa: mv88e6xxx: flush the ATU when the hash algorithm changes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-mv88e6x41-fixes-v3-2-9a8702b27ecc@padl.com> References: <20260715-mv88e6x41-fixes-v3-0-9a8702b27ecc@padl.com> In-Reply-To: <20260715-mv88e6x41-fixes-v3-0-9a8702b27ecc@padl.com> To: Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vivien Didelot , Gregory CLEMENT , Andrew Lunn , Richard Cochran Cc: Cedric Jehasse , Kieran Tyrrell , Max Holtmann , Max Hunter , Christoph Mellauner , Simon Gapp , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Luke Howard X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784071787; l=2392; i=lukeh@padl.com; s=20260701; h=from:subject:message-id; bh=XDTWkz7O9M5hcf2/ooOl1pFfMwOqHJvSeAVx3aKFAn8=; b=rJwRxjXZZgT5qGBJ8yakfqPy3IpG78q7GcVRhMD8yxdaW0GCs514kc4rvY7NRihpKfD0cs4dB H1Mf3pX0ETKDtciMx0g5LT//aIe/iW6tHfmRz/x5xP6eoQfb8XIafzy X-Developer-Key: i=lukeh@padl.com; a=ed25519; pk=D6YgUnH9/OzSZsduYm9XDbvXn1IHDwKwI1hLTsKNRLw= Changing the ATU hash algorithm invalidates existing entries: those loaded under the previous algorithm end up in different bins and read back corrupted. Flush the ATU whenever the hash algorithm is changed through devlink and reload the default broadcast entries. Per-VLAN ATU entries and any static addresses are not replayed, so the hash must be selected before the FDB or MDB are configured. Fixes: 23e8b470c778 ("net: dsa: mv88e6xxx: Add devlink param for ATU hash a= lgorithm.") Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Luke Howard --- drivers/net/dsa/mv88e6xxx/chip.c | 2 +- drivers/net/dsa/mv88e6xxx/chip.h | 2 ++ drivers/net/dsa/mv88e6xxx/devlink.c | 6 ++++++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/c= hip.c index 7938e50900ca8..6faae74de04a9 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2523,7 +2523,7 @@ static int mv88e6xxx_port_add_broadcast(struct mv88e6= xxx_chip *chip, int port, return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); } =20 -static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) +int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) { int port; int err; diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/c= hip.h index f1db12b7629bd..abbb446b73456 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -893,4 +893,6 @@ int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, void *priv), void *priv); =20 +int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid); + #endif /* _MV88E6XXX_CHIP_H */ diff --git a/drivers/net/dsa/mv88e6xxx/devlink.c b/drivers/net/dsa/mv88e6xx= x/devlink.c index 6f034841883c6..5168335f52289 100644 --- a/drivers/net/dsa/mv88e6xxx/devlink.c +++ b/drivers/net/dsa/mv88e6xxx/devlink.c @@ -61,6 +61,12 @@ int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u= 32 id, switch (id) { case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: err =3D mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); + if (err) + break; + err =3D mv88e6xxx_g1_atu_flush(chip, 0, true); + if (err) + break; + err =3D mv88e6xxx_broadcast_setup(chip, 0); break; default: err =3D -EOPNOTSUPP; --=20 2.43.0 From nobody Sat Jul 25 18:54:12 2026 Received: from us.padl.com (us.padl.com [216.154.215.154]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DA2243F4DB; Tue, 14 Jul 2026 23:30:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=216.154.215.154 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784071807; cv=none; b=gvMiY9Y9LMe+DqL87x3nWiKlu8DOwFTNZb/MFAW4mpwBsdd01emV9TE9aTdYyEGFv0RJwf1gjYQOIjT/Ga3gSq78sQdzmtG6OLrGj8EJS0tc6IZ0ogHdhWPuENjJPAnUsOG6cDD5qAihhw1HixqOv4eWdCpnU2506G/8R4trV1w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784071807; c=relaxed/simple; bh=YOlXV4yx2JgouGFWLyMebwKdmLLgwS+W0jBg6q1zBP4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qCWOS7UBtCq78QpbXmdyajjFrzzkJwA+E2+D+OUIwQ7Rf5XTuciHdlp1x+fcjp7xA+lVMEgY3CCYGjJDMND92Fhe5OgSu9AlbIqhrq6oH0dctj0LaPieGSvtmClrAdqYeIatn2nMTxozPyruzlsSinY+ZJCzG9NvXv4R0ez7ySg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=padl.com; spf=pass smtp.mailfrom=padl.com; dkim=pass (2048-bit key) header.d=padl.com header.i=@padl.com header.b=N0oMd47p; arc=none smtp.client-ip=216.154.215.154 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=padl.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=padl.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=padl.com header.i=@padl.com header.b="N0oMd47p" Received: from [127.0.1.1] (border.lukktone.com [139.130.100.52]) by us.padl.com (Postfix) with ESMTPSA id 93BA9621FE; Tue, 14 Jul 2026 19:30:00 -0400 (EDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=padl.com; s=default; t=1784071804; bh=+j9TA7tndJOPgp/THSU1/hZJYBAHL0/MzIuEuvLGtzI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=N0oMd47pvl1y/V6ex0vbmtOxtywfz4hCEOJTuNPKEBd4MmUR8SSqe/XWTzEpBnRbi o+p5fmtjVQr4s3Sd3gZXWvELUor48GafixK+B1Ykl0vdmmjjSmW7NBElT8JSGfMT86 NjslXqHEhlHe5RzX+EZmoqyHDpNr4WNSWqqZb0wBkIFmPUiaxQGLcigvlqhrxgz3HE NnqhhVbEjH1h8REz0qFCrGRnZHl1W4LMv8Fsbg+IYo5dC6Tp+2l1KKgPTV+DYR7Ld8 kWg8qFUT+IK+Ow4afjpPi8Y91zeD9ZIlFW9Szl3Vn9QwoPdcTdGpGpm8q36t8poErp wYDcSn9Ob0OOA== From: Luke Howard Date: Wed, 15 Jul 2026 09:29:43 +1000 Subject: [PATCH net v3 3/3] net: dsa: mv88e6xxx: don't clip ATU Move ToPort delete sentinel Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-mv88e6x41-fixes-v3-3-9a8702b27ecc@padl.com> References: <20260715-mv88e6x41-fixes-v3-0-9a8702b27ecc@padl.com> In-Reply-To: <20260715-mv88e6x41-fixes-v3-0-9a8702b27ecc@padl.com> To: Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vivien Didelot , Gregory CLEMENT , Andrew Lunn , Richard Cochran Cc: Cedric Jehasse , Kieran Tyrrell , Max Holtmann , Max Hunter , Christoph Mellauner , Simon Gapp , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Luke Howard X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784071787; l=1857; i=lukeh@padl.com; s=20260701; h=from:subject:message-id; bh=YOlXV4yx2JgouGFWLyMebwKdmLLgwS+W0jBg6q1zBP4=; b=EqB59wGrl90LmAVRMClpJSs1f5mszE4+xB71AIy/bX+Bm1yhNnxyaJbEYN1Uj3mdMIvZg0yxK IlwaI8Wi3iaBmoaMOUKOJfrjf185EdtHlXVHmb7Xgo8Zv2CPhdYj5T2 X-Developer-Key: i=lukeh@padl.com; a=ed25519; pk=D6YgUnH9/OzSZsduYm9XDbvXn1IHDwKwI1hLTsKNRLw= mv88e6xxx_g1_atu_data_write() masked the port vector, which is correct for a load operation (where portvec is a bitmap) but wrong for a move, where the portvec encodes a ToPort/FromPort pair. An all-ones ToPort value is the sentinel used to delete an entry. Chips with fewer than eight ports (e.g. 88E6141) clipped this value, turning a delete into a move (to port 3 on the 6141/6341). Other chips such as the 7-port 88E6352 were unaffected by chance. Fix this by moving the mv88e6xxx_port_mask() mask into mv88e6xxx_g1_atu_loadpurge(), where the portvec always represents a bitmap; the move path then writes its ToPort/FromPort pair unmasked. Fixes: e606ca36bbf2 ("net: dsa: mv88e6xxx: rework ATU Remove") Assisted-by: Claude:claude-opus-4-8 Signed-off-by: Luke Howard Reviewed-by: Andrew Lunn --- drivers/net/dsa/mv88e6xxx/global1_atu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mv88e6xxx/global1_atu.c b/drivers/net/dsa/mv88= e6xxx/global1_atu.c index 522978f638e2f..6bee943c83575 100644 --- a/drivers/net/dsa/mv88e6xxx/global1_atu.c +++ b/drivers/net/dsa/mv88e6xxx/global1_atu.c @@ -239,7 +239,7 @@ static int mv88e6xxx_g1_atu_data_write(struct mv88e6xxx= _chip *chip, if (entry->trunk) data |=3D MV88E6XXX_G1_ATU_DATA_TRUNK; =20 - data |=3D (entry->portvec & mv88e6xxx_port_mask(chip)) << 4; + data |=3D entry->portvec << 4; } =20 return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_ATU_DATA, data); @@ -326,6 +326,11 @@ int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *= chip, u16 fid, if (err) return err; =20 + /* Mask portvec to a chip's real ports so they cannot spill into + * adjacent ATU Data register fields. + */ + entry->portvec &=3D mv88e6xxx_port_mask(chip); + err =3D mv88e6xxx_g1_atu_data_write(chip, entry); if (err) return err; --=20 2.43.0