From nobody Sat Jul 25 17:35:04 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55153367B77 for ; Wed, 15 Jul 2026 14:09:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784124545; cv=none; b=esTRLap3lk8YLKnWke7prVPX3jd/yLhujPD7hDM0sLoJS1uh8v8vUPA+0VkWe7sQbI4w8JfDUuF9sJe5Odr6l6w1Dy72y4zqiO8HRKtlzoy61reXyae0jKpB5xS5LnKOCcaNurRGbzYt6JUK2u1aL0fqhJ+j2LrY4QSb+QBSzVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784124545; c=relaxed/simple; bh=ATALO6HNchOr9CMZnlOgxknZVX2fMM4WKANowkCK63U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=YoGMpotPtCEbbIshDBe4g6SEqHCC5tqq58PvbHQSX9IdWOWXy8Le0ERrKpX+g1iBi08v6vzbcYWH9kQxdJK0rW5MnId03SqOBE8993gRxET2Or1+5BzSx/5NjhmKy2GxqSutK/Q3Q1EISUhZtiOsdMCS5kSD+neFJO8ficF1mgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=K1Nl8Q0E; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="K1Nl8Q0E" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1784124544; x=1815660544; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=ATALO6HNchOr9CMZnlOgxknZVX2fMM4WKANowkCK63U=; b=K1Nl8Q0ENqM0zdy1bHwGILEXfoYMTZIB3T3rnwhRF5U4L5hgMfVnB9TP 26ZQENgoRF2b9VxJsw9eUB36PlTeQTPr+0hwxil9/PLoa4JBsKv+GeNzV xlHqgSxY/P3iRtYmA78bW8PA01SdEfeLxoFs4kATsb9P6ChyM3sZeVVhC W60AoJyxqCiWulyc+PFnFWH/wOPqykRoOVYHdK83S6/HVQMpmv7mw9DCz uaCQCSe0cc0S9D+oiwTCqIemoxmp6Zca64wXG7CzXStPhIw5lz8E6M2zT dUz+cSEsj2UotBc3P0y1Jbb5D7n8Y+XVZq+F4MEsXaTb8xj4oPzx6Svu5 g==; X-CSE-ConnectionGUID: NzfCaZRQTUCrsXAJUMDaGw== X-CSE-MsgGUID: ej8o11/IShmgaXVbPFw8BA== X-IronPort-AV: E=McAfee;i="6800,10657,11847"; a="84615784" X-IronPort-AV: E=Sophos;i="6.25,165,1779174000"; d="scan'208";a="84615784" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2026 07:09:04 -0700 X-CSE-ConnectionGUID: D3ODEsDjRwGEhzgsVE+hxw== X-CSE-MsgGUID: 4B664tSAR4CBpXPEpOOoig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,165,1779174000"; d="scan'208";a="251777896" Received: from sannilnx-dsk.jer.intel.com (HELO [127.0.1.1]) ([10.12.231.107]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jul 2026 07:08:59 -0700 From: Alexander Usyskin Date: Wed, 15 Jul 2026 16:45:29 +0300 Subject: [PATCH 1/2] mtd: mtd_intel_dg: add survivability partition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-cri_surviv-v1-1-61763a6f1076@intel.com> References: <20260715-cri_surviv-v1-0-61763a6f1076@intel.com> In-Reply-To: <20260715-cri_surviv-v1-0-61763a6f1076@intel.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Rodrigo Vivi , David Airlie , Simona Vetter Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Alexander Usyskin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784123168; l=5677; i=alexander.usyskin@intel.com; s=20260315; h=from:subject:message-id; bh=ATALO6HNchOr9CMZnlOgxknZVX2fMM4WKANowkCK63U=; b=99dOaOuPtNF4sVbMxAPYsGJ6YFuaMNGPDcK0J22YBe7oVG2lCNq/LiyE/OP3GdenmBtnP0cwW B8j6P0+QU9TDHr3geGHNQ8IRIFm5r0ZvWPdEIVwoZJ9Co6dcJ+rIptT X-Developer-Key: i=alexander.usyskin@intel.com; a=ed25519; pk=X+qoF/nFCdDOV04IForWSxnkyoCAbUE10egZi6PSfcU= Add option to expose additional fixed-sized partition starting from the beginning of storage. Xe driver can request this partition exposure if firmware or hardware have detected failure that may involve corrupted partition table. Fixed-sized partition allows full storage re-write in this situation. Signed-off-by: Alexander Usyskin Acked-by: Miquel Raynal --- drivers/mtd/devices/mtd_intel_dg.c | 80 +++++++++++++++++++++++++++-------= ---- include/linux/intel_dg_nvm_aux.h | 1 + 2 files changed, 59 insertions(+), 22 deletions(-) diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_i= ntel_dg.c index f2fa8f68d190..d11ddc687c4a 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -31,6 +31,7 @@ struct intel_dg_nvm { void __iomem *base; void __iomem *base2; bool non_posted_erase; + bool survivability_enabled; =20 size_t size; unsigned int nregions; @@ -205,6 +206,13 @@ static unsigned int idg_nvm_get_region(const struct in= tel_dg_nvm *nvm, loff_t fr { unsigned int i; =20 + /* + * When survivability region is enabled it positioned on index 0 and has = region_id =3D 0 + * Region 0 is special, via this region whole device memory can be access= ed. + */ + if (nvm->survivability_enabled) + return 0; + for (i =3D 0; i < nvm->nregions; i++) { if ((nvm->regions[i].offset + nvm->regions[i].size - 1) >=3D from && nvm->regions[i].offset <=3D from && @@ -443,32 +451,39 @@ static int intel_dg_nvm_init(struct intel_dg_nvm *nvm= , struct device *device, u32 address, base, limit, region; u8 id =3D nvm->regions[i].id; =20 - address =3D NVM_FLREG(id); - region =3D idg_nvm_read32(nvm, address); + if (nvm->regions[i].size) { /* pre-defined survivability region */ + limit =3D nvm->regions[i].offset + nvm->regions[i].size - 1; =20 - base =3D FIELD_GET(NVM_FREG_BASE_MASK, region) << NVM_FREG_ADDR_SHIFT; - limit =3D (FIELD_GET(NVM_FREG_ADDR_MASK, region) << NVM_FREG_ADDR_SHIFT)= | - NVM_FREG_MIN_REGION_SIZE; + if (nvm->size < limit) + nvm->size =3D limit; + } else { + address =3D NVM_FLREG(id); + region =3D idg_nvm_read32(nvm, address); =20 - dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n", - id, nvm->regions[i].name, region, base, limit); + base =3D FIELD_GET(NVM_FREG_BASE_MASK, region) << NVM_FREG_ADDR_SHIFT; + limit =3D (FIELD_GET(NVM_FREG_ADDR_MASK, region) << NVM_FREG_ADDR_SHIFT= ) | + NVM_FREG_MIN_REGION_SIZE; =20 - if (base >=3D limit || (i > 0 && limit =3D=3D 0)) { - dev_dbg(device, "[%d] %s: disabled\n", - id, nvm->regions[i].name); - nvm->regions[i].is_readable =3D 0; - continue; - } + dev_dbg(device, "[%d] %s: region: 0x%08X base: 0x%08x limit: 0x%08x\n", + id, nvm->regions[i].name, region, base, limit); =20 - if (nvm->size < limit) - nvm->size =3D limit; + if (base >=3D limit || (i > 0 && limit =3D=3D 0)) { + dev_dbg(device, "[%d] %s: disabled\n", + id, nvm->regions[i].name); + nvm->regions[i].is_readable =3D 0; + continue; + } =20 - nvm->regions[i].offset =3D base; - nvm->regions[i].size =3D limit - base + 1; - /* No write access to descriptor; mask it out*/ - nvm->regions[i].is_writable =3D idg_nvm_region_writable(access_map, id); + if (nvm->size < limit) + nvm->size =3D limit; =20 - nvm->regions[i].is_readable =3D idg_nvm_region_readable(access_map, id); + nvm->regions[i].offset =3D base; + nvm->regions[i].size =3D limit - base + 1; + /* No write access to descriptor; mask it out*/ + nvm->regions[i].is_writable =3D idg_nvm_region_writable(access_map, id); + + nvm->regions[i].is_readable =3D idg_nvm_region_readable(access_map, id); + } dev_dbg(device, "Registered, %s id=3D%d offset=3D%lld size=3D%lld rd=3D%= d wr=3D%d\n", nvm->regions[i].name, nvm->regions[i].id, @@ -748,7 +763,7 @@ static int intel_dg_mtd_probe(struct auxiliary_device *= aux_dev, struct intel_dg_nvm *nvm; struct device *device; unsigned int nregions; - unsigned int i, n; + unsigned int i, n =3D 0; int ret; =20 device =3D &aux_dev->dev; @@ -764,6 +779,9 @@ static int intel_dg_mtd_probe(struct auxiliary_device *= aux_dev, return -ENODEV; } =20 + if (invm->survivability_size) + nregions++; + nvm =3D kzalloc_flex(*nvm, regions, nregions); if (!nvm) return -ENOMEM; @@ -771,8 +789,26 @@ static int intel_dg_mtd_probe(struct auxiliary_device = *aux_dev, kref_init(&nvm->refcnt); mutex_init(&nvm->lock); nvm->nregions =3D nregions; + nvm->survivability_enabled =3D !!invm->survivability_size; + + if (invm->survivability_size) { /* this partition should be at idx 0 */ + char *name =3D kasprintf(GFP_KERNEL, "%s.%s", + dev_name(&aux_dev->dev), "DATA"); + if (!name) { + ret =3D -ENOMEM; + goto err_norpm; + } + + nvm->regions[n].name =3D name; + nvm->regions[n].id =3D 0; + nvm->regions[n].offset =3D 0; + nvm->regions[n].size =3D invm->survivability_size; + nvm->regions[n].is_readable =3D true; + nvm->regions[n].is_writable =3D true; + n++; + } =20 - for (n =3D 0, i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { + for (i =3D 0; i < INTEL_DG_NVM_REGIONS; i++) { if (!invm->regions[i].name) continue; =20 diff --git a/include/linux/intel_dg_nvm_aux.h b/include/linux/intel_dg_nvm_= aux.h index 625d46a6b96e..84b5b6e0c4ea 100644 --- a/include/linux/intel_dg_nvm_aux.h +++ b/include/linux/intel_dg_nvm_aux.h @@ -21,6 +21,7 @@ struct intel_dg_nvm_dev { struct auxiliary_device aux_dev; bool writable_override; bool non_posted_erase; + size_t survivability_size; struct resource bar; struct resource bar2; const struct intel_dg_nvm_region *regions; --=20 2.53.0 From nobody Sat Jul 25 17:35:04 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9AABD270552 for ; Wed, 15 Jul 2026 14:09:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784124548; cv=none; b=c4WIyfXLpR6aN9rBCv4WBdgmq/Aa26XtADnFj2g8vbjkYG5Y535fRGQSq6Pa6BoucVE0vWM/2xFr7YEqHgUkDltS/xUpeqRUwDE6AEs2oZKvffmdJ4kthinSMNwKdTgnvBLIqIIDybGs5R1MzzHIuAZK6ze4w9sRwLiePZ0p0aM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784124548; c=relaxed/simple; bh=3UKX+8BIib6UlKTc8Qmw7hs4FxBN9EUwfGAbz940ins=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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15 Jul 2026 07:09:03 -0700 From: Alexander Usyskin Date: Wed, 15 Jul 2026 16:45:30 +0300 Subject: [PATCH 2/2] drm/xe/nvm: define survivabilty partition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-cri_surviv-v1-2-61763a6f1076@intel.com> References: <20260715-cri_surviv-v1-0-61763a6f1076@intel.com> In-Reply-To: <20260715-cri_surviv-v1-0-61763a6f1076@intel.com> To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Matthew Brost , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Rodrigo Vivi , David Airlie , Simona Vetter Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Alexander Usyskin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784123168; l=2005; i=alexander.usyskin@intel.com; s=20260315; h=from:subject:message-id; bh=3UKX+8BIib6UlKTc8Qmw7hs4FxBN9EUwfGAbz940ins=; b=yBx5lijfUBZz4oift9rnzndtHkCCy3xKlLYsITWioGCl4uyc4tYgpj3ZLIhssSD9L3pQC2qNL KXUTlq2cfcNCG/AYXaSv7p22JnFHy3Xv6Dw2x9XecWSz1OZ12+TtWgk X-Developer-Key: i=alexander.usyskin@intel.com; a=ed25519; pk=X+qoF/nFCdDOV04IForWSxnkyoCAbUE10egZi6PSfcU= Define 8M survivability partition for CRI when storage is open for write. Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/xe/xe_nvm.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c index 1ea67eaeae24..54de0dbe1fa4 100644 --- a/drivers/gpu/drm/xe/xe_nvm.c +++ b/drivers/gpu/drm/xe/xe_nvm.c @@ -55,10 +55,11 @@ static bool xe_nvm_non_posted_erase(struct xe_device *x= e) } } =20 -static bool xe_nvm_writable_override(struct xe_device *xe) +static bool xe_nvm_writable_override(struct xe_device *xe, size_t *surviva= bility_size) { struct xe_mmio *mmio =3D xe_root_tile_mmio(xe); bool writable_override; + size_t s_size =3D 0; struct xe_reg reg; u32 test_bit, test_val; =20 @@ -67,6 +68,7 @@ static bool xe_nvm_writable_override(struct xe_device *xe) reg =3D PCODE_SCRATCH(0); test_bit =3D FDO_MODE; test_val =3D FDO_MODE; + s_size =3D SZ_8M; break; case XE_BATTLEMAGE: reg =3D HECI_FWSTS2(DG2_GSC_HECI2_BASE); @@ -90,12 +92,17 @@ static bool xe_nvm_writable_override(struct xe_device *= xe) break; default: drm_err(&xe->drm, "Unknown platform\n"); + *survivability_size =3D 0; return true; } =20 writable_override =3D (xe_mmio_read32(mmio, reg) & test_bit) =3D=3D test_= val; - if (writable_override) + if (writable_override) { drm_info(&xe->drm, "NVM access overridden by jumper\n"); + *survivability_size =3D s_size; + } else { + *survivability_size =3D 0; + } return writable_override; } =20 @@ -142,7 +149,7 @@ int xe_nvm_init(struct xe_device *xe) if (!nvm) return -ENOMEM; =20 - nvm->writable_override =3D xe_nvm_writable_override(xe); + nvm->writable_override =3D xe_nvm_writable_override(xe, &nvm->survivabili= ty_size); nvm->non_posted_erase =3D xe_nvm_non_posted_erase(xe); nvm->bar.parent =3D &pdev->resource[0]; nvm->bar.start =3D GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; --=20 2.53.0