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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31189cd8234sm80216146eec.9.2026.07.15.00.12.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 00:12:18 -0700 (PDT) From: Varadarajan Narayanan Date: Wed, 15 Jul 2026 12:41:39 +0530 Subject: [PATCH v2 1/2] arm64: dts: qcom: ipq5210: Add nodes for multiple peripherals Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-08-dts-v2-1-b060b68e0256@oss.qualcomm.com> References: <20260715-08-dts-v2-0-b060b68e0256@oss.qualcomm.com> In-Reply-To: <20260715-08-dts-v2-0-b060b68e0256@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDA2NyBTYWx0ZWRfXzdGGcJDFi28G gt3VD0Fox6tHQGJJ73+wh+sbEjfn1oWBh+2j7zT98yFugkqXBK9VfDhZ6bo4mNqMARcl7YY+wrS ioWgDsIrk+im8+hmzHqP5Nm+ZjDwIF8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDA2NyBTYWx0ZWRfX3uafpCluC28V x58sSX4hJ3dfGB7iqC6MY+8gYoGROPEUncEpZEP+LMauaAIGHTJnZygLxXwExlvzQWFZrEg0yoE fnHR5Icha9OU/AKMEdwH54wqGPGPcj4L/lXXWTLXFBpG3Gpkjk4X82v4SRtxcfsG7OIlUZWyl4R c1L3l4i2pgl9lrjs34DFuDTcPewMTy6Hat1QIdA1FDR+vWEs8ZlqxivO4geVrja/dQDUH8utmid CYEfXhNsOiZInmYHVidw6hqntYzK9Q5nC44cLADW2HiMCh57BtXCqSKy38YLMFq+ni80CUOW5D+ aRx4Xm9LLjhuoBV0fz+aMNUxYXw2DZIHvrj5tRaa0BIvxBuMzORO+NqHeFtmvCbFcWDBpjVTdAC PINXFEaLE0OE4Bgl8YWnzequB4Q8Ph0w/aCoDoFq5RQ4usUzH99/1HUh5zhbcHLT6HW2DqwhK0x sjnIZs/JHIGZ6A10YKg== X-Proofpoint-ORIG-GUID: X_yH7J2xBGdMWf8bkU_z5LMDrpPWZgTn X-Authority-Analysis: v=2.4 cv=NfPWEWD4 c=1 sm=1 tr=0 ts=6a5732d4 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=L-oS5-zLtgPf8eA3vCsA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: X_yH7J2xBGdMWf8bkU_z5LMDrpPWZgTn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150067 Describe common IPQ5210 SoC peripherals in the base DTSI so board DTS files can enable the hardware they use. Add nodes for USB, PCIe, QPIC NAND/BAM, QFPROM, TSENS and thermal zones. Also describe the CPU OPP table and CPU cooling cells needed for CPU frequency scaling and thermal throttling. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5210.dtsi | 616 ++++++++++++++++++++++++++++++= +++- 1 file changed, 610 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qc= om/ipq5210.dtsi index 20e8b240642c..69f36ed38ea3 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -4,7 +4,9 @@ */ =20 #include +#include #include +#include #include =20 / { @@ -28,36 +30,48 @@ cpus { #address-cells =3D <1>; #size-cells =3D <0>; =20 - cpu@0 { + cpu0: cpu@0 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x0>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 - cpu@1 { + cpu1: cpu@1 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x1>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 - cpu@2 { + cpu2: cpu@2 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x2>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 - cpu@3 { + cpu3: cpu@3 { device_type =3D "cpu"; compatible =3D "arm,cortex-a53"; reg =3D <0x3>; enable-method =3D "psci"; next-level-cache =3D <&l2_0>; + #cooling-cells =3D <2>; + clocks =3D <&apcs_glb APCS_ALIAS0_CORE_CLK>; + operating-points-v2 =3D <&cpu_opp_table>; }; =20 l2_0: l2-cache { @@ -84,6 +98,40 @@ memory@80000000 { reg =3D <0x0 0x80000000 0x0 0x0>; }; =20 + cpu_opp_table: opp-table-cpu { + compatible =3D "operating-points-v2-kryo-cpu"; + opp-shared; + nvmem-cells =3D <&cpu_speed_bin>; + + opp-816000000 { + opp-hz =3D /bits/ 64 <816000000>; + opp-supported-hw =3D <0x3>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <200000>; + }; + + opp-1008000000 { + opp-hz =3D /bits/ 64 <1008000000>; + opp-supported-hw =3D <0x3>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <200000>; + }; + + opp-1200000000 { + opp-hz =3D /bits/ 64 <1200000000>; + opp-supported-hw =3D <0x3>; + opp-microvolt =3D <850000>; + clock-latency-ns =3D <200000>; + }; + + opp-1416000000 { + opp-hz =3D /bits/ 64 <1416000000>; + opp-supported-hw =3D <0x1>; + opp-microvolt =3D <1000000>; + clock-latency-ns =3D <200000>; + }; + }; + pmu { compatible =3D "arm,cortex-a53-pmu"; interrupts =3D ; @@ -130,6 +178,170 @@ soc@0 { dma-ranges =3D <0 0 0 0 0x10 0>; ranges =3D <0 0 0 0 0x10 0>; =20 + qusb_phy_0: phy@7b000 { + compatible =3D "qcom,ipq5210-qusb2-phy", "qcom,ipq6018-qusb2-phy"; + reg =3D <0x0 0x0007b000 0x0 0x180>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo_board>; + clock-names =3D "cfg_ahb", + "ref"; + + resets =3D <&gcc GCC_QUSB2_0_PHY_BCR>; + status =3D "disabled"; + }; + + ssphy_0: phy@7d000 { + compatible =3D "qcom,ipq5210-qmp-usb3-phy", "qcom,ipq9574-qmp-usb3-phy"; + reg =3D <0x0 0x0007d000 0x0 0xa00>; + #phy-cells =3D <0>; + + clocks =3D <&gcc GCC_USB0_AUX_CLK>, + <&xo_board>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_PIPE_CLK>; + clock-names =3D "aux", + "ref", + "cfg_ahb", + "pipe"; + + resets =3D <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names =3D "phy", + "phy_phy"; + + #clock-cells =3D <0>; + clock-output-names =3D "usb0_pipe_clk"; + + status =3D "disabled"; + }; + + pcie0_phy: phy@84000 { + compatible =3D "qcom,ipq5210-qmp-gen3x1-pcie-phy"; + reg =3D <0x0 0x00084000 0x0 0x1000>; + + clocks =3D <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie0_pipe_clk"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + pcie1_phy: phy@f4000 { + compatible =3D "qcom,ipq5210-qmp-gen3x2-pcie-phy", + "qcom,ipq9574-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x000f4000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names =3D "aux", "cfg_ahb", "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names =3D "phy", "common"; + + #clock-cells =3D <0>; + clock-output-names =3D "pcie1_pipe_clk"; + + #phy-cells =3D <0>; + status =3D "disabled"; + }; + + efuse@a4000 { + compatible =3D "qcom,ipq5210-qfprom", "qcom,qfprom"; + reg =3D <0x0 0x000a4000 0x0 0x741>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_speed_bin: cpu-speed-bin@28 { + reg =3D <0x28 0x1>; + bits =3D <0 8>; + }; + + tsens_sens11_off: s11@3dd { + reg =3D <0x3dd 0x1>; + bits =3D <4 4>; + }; + + tsens_sens12_off: s12@3de { + reg =3D <0x3de 0x1>; + bits =3D <0 4>; + }; + + tsens_sens13_off: s13@3de { + reg =3D <0x3de 0x1>; + bits =3D <4 4>; + }; + + tsens_sens14_off: s14@3e5 { + reg =3D <0x3e5 0x2>; + bits =3D <7 4>; + }; + + tsens_sens15_off: s15@3e6 { + reg =3D <0x3e6 0x1>; + bits =3D <3 4>; + }; + + tsens_mode: mode@419 { + reg =3D <0x419 0x1>; + bits =3D <0 3>; + }; + + tsens_base0: base0@419 { + reg =3D <0x419 0x2>; + bits =3D <3 10>; + }; + + tsens_base1: base1@41a { + reg =3D <0x41a 0x2>; + bits =3D <5 10>; + }; + }; + + tsens: thermal-sensor@4a9000 { + compatible =3D "qcom,ipq5210-tsens", "qcom,ipq5332-tsens"; + reg =3D <0x0 0x004a9000 0x0 0x1000>, + <0x0 0x004a8000 0x0 0x1000>; + nvmem-cells =3D <&tsens_mode>, + <&tsens_base0>, + <&tsens_base1>, + <&tsens_sens11_off>, + <&tsens_sens12_off>, + <&tsens_sens13_off>, + <&tsens_sens14_off>, + <&tsens_sens15_off>; + nvmem-cell-names =3D "mode", + "base0", + "base1", + "tsens_sens11_off", + "tsens_sens12_off", + "tsens_sens13_off", + "tsens_sens14_off", + "tsens_sens15_off"; + interrupts =3D ; + interrupt-names =3D "combined"; + #thermal-sensor-cells =3D <1>; + #qcom,sensors =3D <5>; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5210-tlmm"; reg =3D <0x0 0x01000000 0x0 0x300000>; @@ -146,8 +358,8 @@ gcc: clock-controller@1800000 { reg =3D <0x0 0x01800000 0x0 0x40000>; clocks =3D <&xo_board>, <&sleep_clk>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, <0>, <0>; #clock-cells =3D <1>; @@ -205,6 +417,89 @@ sdhc: mmc@7804000 { status =3D "disabled"; }; =20 + qpic_bam: dma-controller@7984000 { + compatible =3D "qcom,bam-v1.7.0"; + reg =3D <0x0 0x07984000 0x0 0x1c000>; + interrupts =3D ; + clocks =3D <&gcc GCC_QPIC_AHB_CLK>; + clock-names =3D "bam_clk"; + #dma-cells =3D <1>; + qcom,ee =3D <0>; + status =3D "disabled"; + }; + + qpic_nand: spi@79b0000 { + compatible =3D "qcom,ipq5210-snand", "qcom,ipq9574-snand"; + reg =3D <0x0 0x079b0000 0x0 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <0>; + clocks =3D <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names =3D "core", + "aon", + "iom"; + + dmas =3D <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names =3D "tx", + "rx", + "cmd"; + + status =3D "disabled"; + }; + + usb3: usb@8a00000 { + compatible =3D "qcom,ipq5210-dwc3", "qcom,snps-dwc3"; + reg =3D <0x0 0x08a00000 0x0 0x200000>; + + clocks =3D <&gcc GCC_CNOC_USB_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + + clock-names =3D "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks =3D <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates =3D <200000000>, + <24000000>; + + interrupts-extended =3D <&intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "dwc_usb3", + "pwr_event", + "qusb2_phy", + "dp_hs_phy_irq", + "dm_hs_phy_irq"; + + phys =3D <&qusb_phy_0>, + <&ssphy_0>; + phy-names =3D "usb2-phy", + "usb3-phy"; + + resets =3D <&gcc GCC_USB_BCR>; + + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold =3D /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + + dr_mode =3D "host"; + + status =3D "disabled"; + }; + intc: interrupt-controller@b000000 { compatible =3D "qcom,msm-qgic2"; interrupt-controller; @@ -244,6 +539,24 @@ watchdog@b017000 { clocks =3D <&sleep_clk>; }; =20 + apcs_glb: mailbox@b111000 { + compatible =3D "qcom,ipq5210-apcs-apps-global", + "qcom,ipq6018-apcs-apps-global"; + reg =3D <0x0 0x0b111000 0x0 0x1000>; + #clock-cells =3D <1>; + clocks =3D <&a53pll>, <&xo_board>, <&gcc GPLL0>; + clock-names =3D "pll", "xo", "gpll0"; + #mbox-cells =3D <1>; + }; + + a53pll: clock@b116000 { + compatible =3D "qcom,ipq5210-a53pll"; + reg =3D <0x0 0x0b116000 0x0 0x1000>; + #clock-cells =3D <0>; + clocks =3D <&xo_board>; + clock-names =3D "xo"; + }; + timer@b120000 { compatible =3D "arm,armv7-timer-mem"; reg =3D <0x0 0x0b120000 0x0 0x1000>; @@ -307,6 +620,297 @@ frame@b128000 { status =3D "disabled"; }; }; + + pcie1: pcie@50000000 { + compatible =3D "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x50000000 0x0 0xf1c>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x0 0x0 0x50200000 0x0 0x00100000>, + <0x02000000 0x0 0x0 0x0 0x50300000 0x0 0x0fd00000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE1_PIPE_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_ARES>, + <&gcc GCC_PCIE1_AUX_ARES>, + <&gcc GCC_PCIE1_AHB_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>, + <&gcc MASTER_SNOC_PCIE1 &gcc SLAVE_SNOC_PCIE1>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie1_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + phys =3D <&pcie1_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible =3D "qcom,pcie-ipq5210", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x70000000 0x0 0xf1c>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + bus-range =3D <0x00 0xff>; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x0 0x0 0x70200000 0x0 0x00100000>, + <0x02000000 0x0 0x0 0x0 0x70300000 0x0 0x0fd00000>; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + clocks =3D <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_ARES>, + <&gcc GCC_PCIE0_AUX_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>, + <&gcc MASTER_SNOC_PCIE0 &gcc SLAVE_SNOC_PCIE0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie0_port0: pcie@0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + phys =3D <&pcie0_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + }; + + thermal_zones: thermal-zones { + ethphy-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens 11>; + + trips { + ethphy-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + pon-uniphy-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens 12>; + + trips { + pon-uniphy-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + nss-top-thermal { + polling-delay-passive =3D <0>; + polling-delay =3D <0>; + thermal-sensors =3D <&tsens 13>; + + trips { + nss-top-critical { + temperature =3D <125000>; + hysteresis =3D <9000>; + type =3D "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive =3D <0>; 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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-31189cd8234sm80216146eec.9.2026.07.15.00.12.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 00:12:21 -0700 (PDT) From: Varadarajan Narayanan Date: Wed, 15 Jul 2026 12:41:40 +0530 Subject: [PATCH v2 2/2] arm64: dts: qcom: ipq5210: Enable USB and PCIe on RDP504 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260715-08-dts-v2-2-b060b68e0256@oss.qualcomm.com> References: <20260715-08-dts-v2-0-b060b68e0256@oss.qualcomm.com> In-Reply-To: <20260715-08-dts-v2-0-b060b68e0256@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Varadarajan Narayanan X-Mailer: b4 0.14.3 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE1MDA2NyBTYWx0ZWRfXwwvMGbtgMrp4 L5fzQ3VeFOHefaMU7URo+Uzjv7PZlCHDQC1lCZgc07SzXMWHG1CjMXYgJVZwEc2E9UFX3Q5ZtnM g8nsju5qFiWp2ZqTDKQCfZVKheZVcgU= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE1MDA2NyBTYWx0ZWRfX9JT6MFnV8jJe BkzQM2l0k6QvCc5mXp1atLqzVknRGgXvAST7+BVVDVdmn+MS7v4LAFfgNUfmhrRWD5WAGoc6+2I xHRQaDcEQ89EnAb7NRFXB5TrFBbgs6Yma7/wC1W6SJr/ma1vehE75Rk4WyF8qdUATN9REFvs8Xe /ca0Yd8Z0NwPaMrHodyJFCnBW5x0Ojfg6pVm4gE1a0Dg3Y+6bKlFbpgXIMLOtrMy4mHFN1X0oRz aU/Hfx5kEFf1zAQnZSHB1Jgv19iMPLQX9FRFPnCf86z9baog+JlSR8QQLqlP34GD0hNe4Xu7/Qx DyCM0NDsOrecVaKpDEL+o7C8XwLiKq/ij5yJeA+MNG5l0ZEHMu6x9qbbqYUyFMNrmziXhUo3Ulf HMuecmDRVQ1WnNEjTnvyUzneJB7ETfCbtLPDqsUtDZKJmCD8H5mTDTwuuwNfvJd/wH9ZRmcmLRT quSyAQT9wb4TRxPu3OQ== X-Proofpoint-ORIG-GUID: r4Fl2LUJXnCp4_x_dKknzsgCw2WtfYNM X-Authority-Analysis: v=2.4 cv=NfPWEWD4 c=1 sm=1 tr=0 ts=6a5732d7 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=WPSE4gBbNDprgx3kWUIA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: r4Fl2LUJXnCp4_x_dKknzsgCw2WtfYNM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-15_02,2026-07-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 spamscore=0 suspectscore=0 bulkscore=0 impostorscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607150067 RDP504 has USB, PCIe and SPI NAND devices populated. EMMC and NAND share the GPIOs. The board has to be reworked to change from EMMC to NAND variant. Hence add the NAND node but do not enable it. Describe the fixed USB regulators, PCIe reset GPIOs, QPIC SPI NAND flash and required pinctrl states. Enable QPIC BAM, USB and PCIe for the board. Signed-off-by: Varadarajan Narayanan --- arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts | 131 ++++++++++++++++++++++++= ++++ 1 file changed, 131 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts b/arch/arm64/boot/= dts/qcom/ipq5210-rdp504.dts index 941f866ecfe9..c47e18eabc98 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts +++ b/arch/arm64/boot/dts/qcom/ipq5210-rdp504.dts @@ -5,6 +5,7 @@ =20 /dts-v1/; =20 +#include #include "ipq5210.dtsi" =20 / { @@ -18,6 +19,88 @@ aliases { chosen { stdout-path =3D "serial0"; }; + + vreg_misc_3p3: regulator-usb-3p3 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "usb_hs_vdda_3p3"; + }; + + vreg_misc_1p8: regulator-usb-1p8 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "vdda_1p8_usb"; + }; + + vreg_misc_0p925: regulator-usb-0p925 { + compatible =3D "regulator-fixed"; + regulator-min-microvolt =3D <925000>; + regulator-max-microvolt =3D <925000>; + regulator-boot-on; + regulator-always-on; + regulator-name =3D "vdd_core_usb"; + }; +}; + +&pcie0_phy { + status =3D "okay"; +}; + +&pcie0_port0 { + reset-gpios =3D <&tlmm 32 GPIO_ACTIVE_LOW>; +}; + +&pcie0 { + pinctrl-0 =3D <&pcie0_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&pcie1_phy { + status =3D "okay"; +}; + +&pcie1_port0 { + reset-gpios =3D <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&pcie1 { + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&qpic_bam { + status =3D "okay"; +}; + +&qpic_nand { + pinctrl-0 =3D <&qpic_snand_default_state>; + pinctrl-names =3D "default"; + + flash@0 { + compatible =3D "spi-nand"; + reg =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <1>; + nand-ecc-engine =3D <&qpic_nand>; + nand-ecc-strength =3D <4>; + nand-ecc-step-size =3D <512>; + }; +}; + +&qusb_phy_0 { + vdd-supply =3D <&vreg_misc_0p925>; + vdda-pll-supply =3D <&vreg_misc_1p8>; + vdda-phy-dpdm-supply =3D <&vreg_misc_3p3>; + + status =3D "okay"; }; =20 &sdhc { @@ -35,7 +118,51 @@ &sleep_clk { clock-frequency =3D <32000>; }; =20 +&ssphy_0 { + vdda-pll-supply =3D <&vreg_misc_1p8>; + vdda-phy-supply =3D <&vreg_misc_0p925>; + + status =3D "okay"; +}; + &tlmm { + pcie1_default_state: pcie1-default-state { + pins =3D "gpio29"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + }; + + pcie0_default_state: pcie0-default-state { + pins =3D "gpio32"; + function =3D "gpio"; + drive-strength =3D <6>; + bias-pull-down; + }; + + qpic_snand_default_state: qpic-snand-default-state { + data-pins { + pins =3D "gpio0", "gpio1", "gpio2", "gpio3"; + function =3D "qspi_data"; + drive-strength =3D <8>; + bias-disable; + }; + + cs-pins { + pins =3D "gpio4"; + function =3D "qspi_cs_n"; + drive-strength =3D <8>; + bias-disable; + }; + + clock-pins { + pins =3D "gpio5"; + function =3D "qspi_clk"; + drive-strength =3D <8>; + bias-disable; + }; + }; + qup_uart1_default_state: qup-uart1-default-state { pins =3D "gpio38", "gpio39"; function =3D "qup_se1"; @@ -74,6 +201,10 @@ &uart1 { status =3D "okay"; }; =20 +&usb3 { + status =3D "okay"; +}; + &xo_board { clock-frequency =3D <24000000>; }; --=20 2.34.1