From nobody Sat Jul 25 18:53:29 2026 Received: from mail-pj1-f46.google.com (mail-pj1-f46.google.com [209.85.216.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D5F2F2DB78C for ; Tue, 14 Jul 2026 23:38:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784072341; cv=none; b=BbO24Xyw5ZeexQB1k3Wq3XVOojWLL66gCKQZOs/9vxIFXwu43V5OGi/fzXvNgQXpxr2Qg8Mx3EAY4VAsonvWstgVMrWApEzbwk9KMD9bTB204oqfzby3bcjk6aLNaVlGFs1XXsCqt6n3Ij9RV8tT+7fzk2E422bQIj/kRL0Jiak= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784072341; c=relaxed/simple; bh=yv1tuWDWJhSyiyvMNhanYGrFvbz3c1/jLUP8Tguzisk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gPiqmXLTzm9GWnwcedQio402qJ4PT1f0U+RkfsqE8tm6nUZF6oSr7zBSvgOL1rQIrEXCfzYP0KWOu4Lnfks32WK9ydSbnwvE5obbUGs7f5kUtOQezRt1csLjt+l+ZJfJWtx89KSZcXYdNSvbX9HxF6XdigGP2bw3E1xn7S+s5W4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=fK8nKOuC; arc=none smtp.client-ip=209.85.216.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="fK8nKOuC" Received: by mail-pj1-f46.google.com with SMTP id 98e67ed59e1d1-384930ca5e2so5038613a91.3 for ; Tue, 14 Jul 2026 16:38:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784072339; x=1784677139; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=MfgBILHJrY4C17rMIeQ269NwG+vZxxLm9/G2lcTQrFA=; b=fK8nKOuC8wdQV3hvn3F/CfePdi8VcNG3JqAiZML8HHiBSd/Q9fulcjQRM4XUmKOUAI Ie4D+t97BotaZTmAerTU2aA+a+X4Zx24Tfl6/UvIPaLJrQqVt4tmCOmjGPzD6SLtq9wG iWhbJL2VyGFwG9Vt4IXSd1G7PMlb31rl88SOpG302C59PzQBheZiaoRI8VznsN0M2sAj DS9ekek/d4/ttpUeJoGkG1KpBxhnSrxUp24HSN1cUO39szCJi1Y5IgYcCeb7uiCkowAX MtAblzM1eWsPmL7TeUQfS5FL6MvYF9F8WWPCMP1gKPyIinHHHe/zSOd+EuRQGAqUu1q9 RE9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784072339; x=1784677139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=MfgBILHJrY4C17rMIeQ269NwG+vZxxLm9/G2lcTQrFA=; b=IMaLzko5rwsK+S7OcYEfsSKOPbKrLTZ4LArsV4oArNESBhRqqqnlf1lLxN2Pv031+z hc7yVqP2ZXdC3aXx63kB/dwNA5n3tSyRBjAYtGNIprIbomZa2n53C8OP7SVz4yZ4p+bV 8+jROEQdSk7ldubGuP0P8+Mwr0+rfSfXYXb7FfiuzMQuQ1z+Fbw6izAGoAAtHvsXSUR6 SFWJeaLCHDQ8YzyzsaQw83XtrkRMOxQntmMzBcEV0oMyKse1xyFLcczl4fmO4sk9aEHE aQJ8SO9L1kd7r2PkfIk399fWZIlIN7EEfr74eCBD6D5aZk3f5MyFNcFHrrdJvVic6PPW 2Kqw== X-Forwarded-Encrypted: i=1; AHgh+RqfENBneCayDbbhqdks+7JPx/2+mHmLYS9g0Ze4/X7OLtcy6vik8rFesyNJm6wI+129MziEMP/ZIwI34Bs=@vger.kernel.org X-Gm-Message-State: AOJu0YyLjR9a+efuKUDwucWlC+uG9LREyMLu7lKIvytoQN6R1WlOVlmH hjPZFTDBv4quHM0IFYZUYvDXaap0dSgTkhF5Uh5nGIBps8qTWtwxkMe5 X-Gm-Gg: AfdE7ckAx3JI3JsGr+56ezRUETbhNt9Pu2N+pih2+ZSklzOrRJ8GLUY8LB7EdVlsPzm x3KPyCxDsHI5XAaGXll5EYZqfWvgmDA0hhhWBWfYR+BP5kq7L+5YjlIn9gd2D9Sh9fiPorChQHs BhDnFuTCkaz/f8QG0UrcVsuexNLgsnl2pPFj78vapNRB7SDQcDYcc6mG/dflaZngbjCmfrYLKWy WiaZE+LJFkrUuBI+R5mog1lt+3kXW446AH/jkU5SS+Mve0l0DRa2ObiZbf3PTkosxnDDOkAEgMA gu5ltvXpr7OMe+rSOXTgEslHpwLJL015S4ec3+gGPQewihLCtIkgodY8uUAQdFBRXA+/NwP7dGV BQFeHaVpFfzoWMY453mjnONxoaaRyop16zsQTZYn05JHMMzibl4Hzb3jss1Yqmp6H0TfqR/+rGz l3PaGLurWLdkU5qUgoPtBARzulMCBYNVsMGkmcJrqP06cxLIZb0NB7I5/kvq6GUQU9LToTHwcTM YxMFnEh7uJ9C7VNJ9cKr/ClTcbAl+01EtkK39OECLC+gEodroJ0ZU1Z61QpyzGnHQ== X-Received: by 2002:a17:90b:1646:b0:38d:c834:24cf with SMTP id 98e67ed59e1d1-38e2a01d044mr537748a91.23.1784072339212; Tue, 14 Jul 2026 16:38:59 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3118389d9bcsm72317509eec.20.2026.07.14.16.38.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 16:38:58 -0700 (PDT) From: Rosen Penev To: dmaengine@vger.kernel.org Cc: Vinod Koul , Frank Li , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/3] dma: fsl_raid: fix endianness of in-memory descriptor stores Date: Tue, 14 Jul 2026 16:38:53 -0700 Message-ID: <20260714233855.870797-2-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260714233855.870797-1-rosenp@gmail.com> References: <20260714233855.870797-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The descriptor structs (fsl_re_cmpnd_frame / fsl_re_hw_desc) are in-memory but their fields are __be32, because the structures are handed to the device as big-endian. The driver stored CPU-endian u32 values into them directly, which is both wrong (the engine would see byte-swapped lengths/addresses) and flagged by sparse as a base-type mismatch. Wrap those stores in cpu_to_be32() so the values are little->big converted. The final-frame bit is now passed as the "final" argument of fill_cfd_frame() (as fsl_re_prep_dma_memcpy already did) and set in CPU order before the single cpu_to_be32() store, replacing the previous read-modify-write of the __be32 efrl32 field. Reported-by: kernel test robot Fixes: https://lore.kernel.org/oe-kbuild-all/202008111749.yy85rFMD%25lkp@in= tel.com/ Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev --- drivers/dma/fsl_raid.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index 99945845d8b5..888f55b672a5 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -242,9 +242,9 @@ static void fill_cfd_frame(struct fsl_re_cmpnd_frame *c= f, u8 index, u32 efrl =3D length & FSL_RE_CF_LENGTH_MASK; =20 efrl |=3D final << FSL_RE_CF_FINAL_SHIFT; - cf[index].efrl32 =3D efrl; - cf[index].addr_high =3D upper_32_bits(addr); - cf[index].addr_low =3D lower_32_bits(addr); + cf[index].efrl32 =3D cpu_to_be32(efrl); + cf[index].addr_high =3D cpu_to_be32(upper_32_bits(addr)); + cf[index].addr_low =3D cpu_to_be32(lower_32_bits(addr)); } =20 static struct fsl_re_desc *fsl_re_init_desc(struct fsl_re_chan *re_chan, @@ -256,9 +256,10 @@ static struct fsl_re_desc *fsl_re_init_desc(struct fsl= _re_chan *re_chan, dma_async_tx_descriptor_init(&desc->async_tx, &re_chan->chan); INIT_LIST_HEAD(&desc->node); =20 - desc->hwdesc.fmt32 =3D FSL_RE_FRAME_FORMAT << FSL_RE_HWDESC_FMT_SHIFT; - desc->hwdesc.lbea32 =3D upper_32_bits(paddr); - desc->hwdesc.addr_low =3D lower_32_bits(paddr); + desc->hwdesc.fmt32 =3D cpu_to_be32(FSL_RE_FRAME_FORMAT << + FSL_RE_HWDESC_FMT_SHIFT); + desc->hwdesc.lbea32 =3D cpu_to_be32(upper_32_bits(paddr)); + desc->hwdesc.addr_low =3D cpu_to_be32(lower_32_bits(paddr)); desc->cf_addr =3D cf; desc->cf_paddr =3D paddr; =20 @@ -374,11 +375,11 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dm= a_genq( for (i =3D 2, j =3D 0; j < save_src_cnt; i++, j++) fill_cfd_frame(cf, i, len, src[j], 0); =20 + /* Fill the last frame and mark it final */ if (cont_q) - fill_cfd_frame(cf, i++, len, dest, 0); - - /* Setting the final bit in the last source buffer frame in CFD */ - cf[i - 1].efrl32 |=3D 1 << FSL_RE_CF_FINAL_SHIFT; + fill_cfd_frame(cf, i, len, dest, 1); + else + fill_cfd_frame(cf, i - 1, len, src[j - 1], 1); =20 return &desc->async_tx; } @@ -504,16 +505,16 @@ static struct dma_async_tx_descriptor *fsl_re_prep_dm= a_pq( p[save_src_cnt + 2] =3D 1; fill_cfd_frame(cf, i++, len, dest[0], 0); fill_cfd_frame(cf, i++, len, dest[1], 0); - fill_cfd_frame(cf, i++, len, dest[1], 0); + fill_cfd_frame(cf, i++, len, dest[1], 1); } else { dev_err(re_chan->dev, "PQ tx continuation error!\n"); return NULL; } + } else { + /* Mark the last source buffer frame final */ + fill_cfd_frame(cf, i - 1, len, src[j - 1], 1); } =20 - /* Setting the final bit in the last source buffer frame in CFD */ - cf[i - 1].efrl32 |=3D 1 << FSL_RE_CF_FINAL_SHIFT; - return &desc->async_tx; } =20 --=20 2.55.0 From nobody Sat Jul 25 18:53:29 2026 Received: from mail-pj1-f45.google.com (mail-pj1-f45.google.com [209.85.216.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DD10368D5A for ; Tue, 14 Jul 2026 23:39:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784072343; cv=none; b=fP41hPOlhCTHzUW3q/YscWw1IHYcbI6mtvgVUlJvSgIF9I7RVWeiDHeBbmi286cUxBXagpanymbvG1p8qazb+1RufBGYwr1wHSD9NntrPV66llVfKqkaqnezltFqTHe/Nd34HmBL3XegKOaKqLw5RBiGPOMHvR9WsQw7TPItpvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784072343; c=relaxed/simple; bh=wi/MMgULAybZVLtK8371fsJgjgFlbmj6qmhUZ12gmMg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TGTg82SrKuJdnDcfG/QVEHHUL7XKV07uKgekc0dFMUIJP4mHoHxA5dmdiRBPH/esUOPQ4ci12FTFsw57xfrn4hs+dZ/LTWOVGMC9TdsLfITjsXcBqj5KGAHI8Tzu7+6hqPW54LmOxHo4areQ/0cK+EMuVWqJOnrv+G73LSuetRE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ke/oBmRT; arc=none smtp.client-ip=209.85.216.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ke/oBmRT" Received: by mail-pj1-f45.google.com with SMTP id 98e67ed59e1d1-38125cebfdaso1857044a91.1 for ; Tue, 14 Jul 2026 16:39:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784072341; x=1784677141; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=1l02xGyRBTD067iKEsMBqmmqfaPsVp34wo3pg2+qQRU=; b=ke/oBmRTZjMSaREqpKL1WGCzz+GqXQ4mg2nRNkuzZ5qqYSUwMHJXPeDHPE4KcxdLUl /XAEyJoadkZcthC7UMu31ik/pP6RT1F76ybcTyD8NKriMipAbUTFhN/WKYBTzK/h2zRm XK2yCGWWaiHErgTercD+CUZlFse2nBe1zMax3E45mEn2JB9OXwuaTjkzvw2/0EFofYAb vGWMBwYA04htxljOqX07Jn16yq6QTb++oqxfxzGQKv7dK68WgzL7vbN/J19bJSlE8GBm kf3Awi+ioZqf2gscFgVyIwwzfEBCJbS59QsyNQM/v/ouUmtSV8hWXDV4anszOrFuPuNN 3Bug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784072341; x=1784677141; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=1l02xGyRBTD067iKEsMBqmmqfaPsVp34wo3pg2+qQRU=; b=EaTTnnpVZElR7fYvhc0saiqXVveTBhLBJkqmR6PrXpVkypELDGE2AL9LhnLTnvrUbo KnfmrIemedV4gE5CkmcSeutHg0zfEZKR92ltT8ImnGkcPi4Qx2DmtY8hdofayVTxW/fW +h5bkN0Z5zOVLcwIEQ6yWq5L1zA4UvAsG7VBBa/4qAqKeSV3PX2ngwpikyINrCDDfVsx 1CX6D5DTzYLzrl2OX/U0jg/y+iiCaPSN75fhHA1ZeUxpb7HvpQOMVrGzdBmrEGITD6gA mAZShOHFDICXB1xdSl32tb0EpTS4GVM2mPQnCQcN97i2MFQCW0aGulc+xiL2wm4y+L5W +x4g== X-Forwarded-Encrypted: i=1; AHgh+RoXdMtS+TIv16VAoduSZ9nlc/wZIvN3nvAzoUyOo+bKuTsCYSyxHE/wHc9n6kJcwdFkGXFECABN4nsIMqg=@vger.kernel.org X-Gm-Message-State: AOJu0YyCdW2s12+C5b24zfHY2nNLVhUarfKzuvxVXybdrMgcUJbS9ER+ fjkYqhOmOr948WvO4aKA3A45ttLudK/xSjtJQq1Eohx1k898D/OMMhLW X-Gm-Gg: AfdE7cnzlXTI98y+24EQCiKxPl3OBwuuf+dIODLTyHPTNZzBTZii/rWPSy4hJ9eLgv3 Gon0yo0Q0dyC18iVpwYCo2An+hpkos/Fnw2Rv1jwOYHvTR6iBrqYcicetYPxADuC3b7JHkfElIL 8TO1j6ovS7sUTQKGNWijL30L5BEPtrPwHSGBEYklAj1YX3M6BJZd8bYbgXdaUuaCKtklthYw+lH jfWh3Q4bMgkfUqCUo1GV4nyD+KT61Kxw3TrcZRVuxVeXG+cNHrUVdKFVLGjlAqSfPBPEy9oaz7V n+aqNUqmDH2xKuYlYbYPLcJ6Qg7O6DgRiOMirBsucPgirfUj/RhwfWW4qLa31DlvXVu0NfQDxuJ QW8hVySaSKYU12n9rw3Bd3iOtBRandxgX7WKQoF+zQjJAu6hjQQpBq0Uohw+Nj7EwQ4/EUEhfc1 GGA6CUzqmnpUlKWem8qHVtWxl7Og64Elzns4Jd82JsF4+YQ4YEHKlZTIXFd8O5xHOM0bQxU8aRv LAoLAv3Y4QVq0da428DLQT7ELF8bsgGcP78GAk4j3xQI1SpjsIrG5YGqw5eI+4gqA== X-Received: by 2002:a17:90b:5344:b0:381:e74f:8a6a with SMTP id 98e67ed59e1d1-38dc74d5646mr14736298a91.16.1784072340901; Tue, 14 Jul 2026 16:39:00 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3118389d9bcsm72317509eec.20.2026.07.14.16.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 16:38:59 -0700 (PDT) From: Rosen Penev To: dmaengine@vger.kernel.org Cc: Vinod Koul , Frank Li , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/3] dma: fsl_raid: keep MMIO bases as void __iomem and cast at access Date: Tue, 14 Jul 2026 16:38:54 -0700 Message-ID: <20260714233855.870797-3-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260714233855.870797-1-rosenp@gmail.com> References: <20260714233855.870797-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The fsl_re_ctrl and fsl_re_chan_cfg structures describe memory-mapped RAID Engine registers accessed only via ioread32be()/iowrite32be(), yet the pointers to them (re_regs in struct fsl_re_drv_private, and jrregs in struct fsl_re_chan) were not __iomem-qualified, so sparse emitted "different address spaces" warnings for every register access. Store both MMIO bases as a plain void __iomem * and derive jrregs with void __iomem * arithmetic from re_regs, rather than carrying typed register struct pointers through the driver. Each function that touches the registers introduces a local typed pointer (struct fsl_re_ctrl __iomem *ctrl / struct fsl_re_chan_cfg __iomem *jr) and uses ->field, which is the idiomatic kernel pattern and keeps the registers' __iomem qualification intact. Reported-by: kernel test robot Fixes: https://lore.kernel.org/oe-kbuild-all/202008111749.yy85rFMD%25lkp@in= tel.com/ Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev --- drivers/dma/fsl_raid.c | 66 ++++++++++++++++++++---------------------- drivers/dma/fsl_raid.h | 4 +-- 2 files changed, 34 insertions(+), 36 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index 888f55b672a5..47ebdf274331 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -106,15 +106,17 @@ static dma_cookie_t fsl_re_tx_submit(struct dma_async= _tx_descriptor *tx) static void fsl_re_issue_pending(struct dma_chan *chan) { struct fsl_re_chan *re_chan; + struct fsl_re_chan_cfg __iomem *jr; int avail; struct fsl_re_desc *desc, *_desc; unsigned long flags; =20 re_chan =3D container_of(chan, struct fsl_re_chan, chan); + jr =3D re_chan->jrregs; =20 spin_lock_irqsave(&re_chan->desc_lock, flags); avail =3D FSL_RE_SLOT_AVAIL( - in_be32(&re_chan->jrregs->inbring_slot_avail)); + in_be32(&jr->inbring_slot_avail)); =20 list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) { if (!avail) @@ -127,7 +129,7 @@ static void fsl_re_issue_pending(struct dma_chan *chan) =20 re_chan->inb_count =3D (re_chan->inb_count + 1) & FSL_RE_RING_SIZE_MASK; - out_be32(&re_chan->jrregs->inbring_add_job, FSL_RE_ADD_JOB(1)); + out_be32(&jr->inbring_add_job, FSL_RE_ADD_JOB(1)); avail--; } spin_unlock_irqrestore(&re_chan->desc_lock, flags); @@ -158,6 +160,7 @@ static void fsl_re_cleanup_descs(struct fsl_re_chan *re= _chan) static void fsl_re_dequeue(struct tasklet_struct *t) { struct fsl_re_chan *re_chan =3D from_tasklet(re_chan, t, irqtask); + struct fsl_re_chan_cfg __iomem *jr =3D re_chan->jrregs; struct fsl_re_desc *desc, *_desc; struct fsl_re_hw_desc *hwdesc; unsigned long flags; @@ -167,7 +170,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t) fsl_re_cleanup_descs(re_chan); =20 spin_lock_irqsave(&re_chan->desc_lock, flags); - count =3D FSL_RE_SLOT_FULL(in_be32(&re_chan->jrregs->oubring_slot_full)); + count =3D FSL_RE_SLOT_FULL(in_be32(&jr->oubring_slot_full)); while (count--) { found =3D 0; hwdesc =3D &re_chan->oub_ring_virt_addr[re_chan->oub_count]; @@ -192,8 +195,7 @@ static void fsl_re_dequeue(struct tasklet_struct *t) oub_count =3D (re_chan->oub_count + 1) & FSL_RE_RING_SIZE_MASK; re_chan->oub_count =3D oub_count; =20 - out_be32(&re_chan->jrregs->oubring_job_rmvd, - FSL_RE_RMVD_JOB(1)); + out_be32(&jr->oubring_job_rmvd, FSL_RE_RMVD_JOB(1)); } spin_unlock_irqrestore(&re_chan->desc_lock, flags); } @@ -201,12 +203,12 @@ static void fsl_re_dequeue(struct tasklet_struct *t) /* Per Job Ring interrupt handler */ static irqreturn_t fsl_re_isr(int irq, void *data) { - struct fsl_re_chan *re_chan; + struct device *dev =3D data; + struct fsl_re_chan *re_chan =3D dev_get_drvdata(dev); + struct fsl_re_chan_cfg __iomem *jr =3D re_chan->jrregs; u32 irqstate, status; =20 - re_chan =3D dev_get_drvdata((struct device *)data); - - irqstate =3D in_be32(&re_chan->jrregs->jr_interrupt_status); + irqstate =3D in_be32(&jr->jr_interrupt_status); if (!irqstate) return IRQ_NONE; =20 @@ -216,13 +218,13 @@ static irqreturn_t fsl_re_isr(int irq, void *data) * need to do something more than just crashing */ if (irqstate & FSL_RE_ERROR) { - status =3D in_be32(&re_chan->jrregs->jr_status); + status =3D in_be32(&jr->jr_status); dev_err(re_chan->dev, "chan error irqstate: %x, status: %x\n", irqstate, status); } =20 /* Clear interrupt */ - out_be32(&re_chan->jrregs->jr_interrupt_status, FSL_RE_CLR_INTR); + out_be32(&jr->jr_interrupt_status, FSL_RE_CLR_INTR); =20 tasklet_schedule(&re_chan->irqtask); =20 @@ -627,6 +629,7 @@ static int fsl_re_chan_probe(struct platform_device *of= dev, struct device *dev, *chandev; struct fsl_re_drv_private *re_priv; struct fsl_re_chan *chan; + struct fsl_re_chan_cfg __iomem *jr; struct dma_device *dma_dev; u32 ptr; u32 status; @@ -657,8 +660,8 @@ static int fsl_re_chan_probe(struct platform_device *of= dev, goto err_free; } =20 - chan->jrregs =3D (struct fsl_re_chan_cfg *)((u8 *)re_priv->re_regs + - off + ptr); + jr =3D re_priv->re_regs + off + ptr; + chan->jrregs =3D jr; =20 /* read irq property from dts */ chan->irq =3D irq_of_parse_and_map(np, 0); @@ -709,30 +712,23 @@ static int fsl_re_chan_probe(struct platform_device *= ofdev, } =20 /* Program the Inbound/Outbound ring base addresses and size */ - out_be32(&chan->jrregs->inbring_base_h, - chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK); - out_be32(&chan->jrregs->oubring_base_h, - chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK); - out_be32(&chan->jrregs->inbring_base_l, - chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIFT); - out_be32(&chan->jrregs->oubring_base_l, - chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIFT); - out_be32(&chan->jrregs->inbring_size, - FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT); - out_be32(&chan->jrregs->oubring_size, - FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT); + out_be32(&jr->inbring_base_h, chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK); + out_be32(&jr->oubring_base_h, chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK); + out_be32(&jr->inbring_base_l, chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIF= T); + out_be32(&jr->oubring_base_l, chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIF= T); + out_be32(&jr->inbring_size, FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT); + out_be32(&jr->oubring_size, FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT); =20 /* Read LIODN value from u-boot */ - status =3D in_be32(&chan->jrregs->jr_config_1) & FSL_RE_REG_LIODN_MASK; + status =3D in_be32(&jr->jr_config_1) & FSL_RE_REG_LIODN_MASK; =20 /* Program the CFG reg */ - out_be32(&chan->jrregs->jr_config_1, - FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status); + out_be32(&jr->jr_config_1, FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status); =20 dev_set_drvdata(chandev, chan); =20 /* Enable RE/CHAN */ - out_be32(&chan->jrregs->jr_command, FSL_RE_ENABLE); + out_be32(&jr->jr_command, FSL_RE_ENABLE); =20 return 0; =20 @@ -752,6 +748,7 @@ static int fsl_re_probe(struct platform_device *ofdev) u8 ridx =3D 0; struct dma_device *dma_dev; struct resource *res; + struct fsl_re_ctrl __iomem *re_regs; int rc; struct device *dev =3D &ofdev->dev; =20 @@ -767,17 +764,18 @@ static int fsl_re_probe(struct platform_device *ofdev) re_priv->re_regs =3D devm_ioremap(dev, res->start, resource_size(res)); if (!re_priv->re_regs) return -EBUSY; + re_regs =3D re_priv->re_regs; =20 /* Program the RE mode */ - out_be32(&re_priv->re_regs->global_config, FSL_RE_NON_DPAA_MODE); + out_be32(&re_regs->global_config, FSL_RE_NON_DPAA_MODE); =20 /* Program Galois Field polynomial */ - out_be32(&re_priv->re_regs->galois_field_config, FSL_RE_GFM_POLY); + out_be32(&re_regs->galois_field_config, FSL_RE_GFM_POLY); =20 dev_info(dev, "version %x, mode %x, gfp %x\n", - in_be32(&re_priv->re_regs->re_version_id), - in_be32(&re_priv->re_regs->global_config), - in_be32(&re_priv->re_regs->galois_field_config)); + in_be32(&re_regs->re_version_id), + in_be32(&re_regs->global_config), + in_be32(&re_regs->galois_field_config)); =20 dma_dev =3D &re_priv->dma_dev; dma_dev->dev =3D dev; diff --git a/drivers/dma/fsl_raid.h b/drivers/dma/fsl_raid.h index 69d743c04973..6069615e2e1e 100644 --- a/drivers/dma/fsl_raid.h +++ b/drivers/dma/fsl_raid.h @@ -256,7 +256,7 @@ struct fsl_re_hw_desc { struct fsl_re_drv_private { u8 total_chans; struct dma_device dma_dev; - struct fsl_re_ctrl *re_regs; + void __iomem *re_regs; struct fsl_re_chan *re_jrs[FSL_RE_MAX_CHANS]; struct dma_pool *cf_desc_pool; struct dma_pool *hw_desc_pool; @@ -273,7 +273,7 @@ struct fsl_re_chan { struct device *dev; struct fsl_re_drv_private *re_dev; struct dma_chan chan; - struct fsl_re_chan_cfg *jrregs; + void __iomem *jrregs; int irq; struct tasklet_struct irqtask; u32 alloc_count; --=20 2.55.0 From nobody Sat Jul 25 18:53:29 2026 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 512D13E9580 for ; Tue, 14 Jul 2026 23:39:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784072345; cv=none; b=YxIxLLCalnbNoltHNJNZP9YIOkyvEUn63M7dyeXQGdT+jhF/gRqGkK/F9BEhQl8t0MgB4rcobr+KyA5GCEKhQEVmd2DwdCYBp1M36z46acHpediDjJwaNBtezq9nXfoQTCDbDKOEzhInaFU/6btMi3/c0WC3jR5TGeFSWvUUh3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784072345; c=relaxed/simple; bh=scac1LoCOoZlclfHOjh/NGC+6kM4IpG7zrAGD+2FOuo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ozDvns1SqwnXqdfxwwFrLeVo4dToiP98k+KF9zlNDQup+USZXkmj4tJEyUSy7Zc+VymYBtKxOoYz51T+UgGzHkzpHvk1yoccQEjRhIoHnWwJAt2HeLcInGZaVLOWo3PAhv2LIkax+wEjQJHnTSzD2e+8izft03vJRNMNoVR7njE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=e33aPU/G; arc=none smtp.client-ip=209.85.216.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="e33aPU/G" Received: by mail-pj1-f41.google.com with SMTP id 98e67ed59e1d1-38101f85591so74228a91.1 for ; Tue, 14 Jul 2026 16:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784072343; x=1784677143; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=klA6vgVRqJZz6oksZGdOEYmB++Nc+N5JXap4nZREOdE=; b=e33aPU/G96AiXGbxBMiOeMSSZloOnt87/CvxmI5dD1B680+Zc6GcCUcgONmB6gMepK BJEOgT3FmXHz+kOGD4PkgPkMZoJ4q1NX+CJ+z/iKe1UOJjwgu5tQJlZajgZPkY6yhy+u dAgIfmVcW07CO/3T5AdkTD7OKWSteA7P/9x09I//lnhsV3O2sGcbV4FH87vHWo0fadv0 o+q5U2EAIO4lyboKiTdLJ5mPH7ZfM46riE7JEVTJ5ERKOvGqhCwn6edCnuO63Pfxm0v7 cVIHXp52SrSrRHBsCSwa5VJXMDlYdJ0aOjRU833aRHzMascY86tLqrR8oG5SIl5icuXs u1Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784072343; x=1784677143; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=klA6vgVRqJZz6oksZGdOEYmB++Nc+N5JXap4nZREOdE=; b=pSlO6oOz5zxHg014meGn5ldfUbcnBFo2qA5ILsaRbvhjOrMKtFTLgIiDSqJcbWqLhJ iDOnzPgt3pmKRXIh1cGLvvuHVXoOqP6Y7cVkYRUWR0gzAuKKpHv/FH5eSoAIqFAeRAUK UXLliGyu7soiwNunk5yVspikqLJi1kPqCmtAKxr51fICi6hZXGS4vrY0PD4EwJiQVAzO ASEPL8s13IvyFBJzVCuT3OL0hxXIS5KNvhLaUHonBDyIIYNq6CB4tuPIIbd7dTh6nFh9 umyTo96R4lvjsStWvlugDnq1NDfSFmtLmDIeC9/p4dvzwFPOxGFXimtP1fXnpyUEPJH1 mFPA== X-Forwarded-Encrypted: i=1; AHgh+Rr2UJDRelS+ENuvhfi1utMekWgf189J6SDiSG1LxhIes7Pk4XaZXyfMTPrYvCoRQg1XiKel6OasYwEnaEI=@vger.kernel.org X-Gm-Message-State: AOJu0YzqSXNvlQCLjpCpABLac5oE9rm1pRnQVxKR7gitj5woVUZTIOX3 YLAlRTmhEi/Y26Yne+fD89zCi0+e3591RBHeNmihvKkx4Mp+WmF2Qg6I X-Gm-Gg: AfdE7cl47WDCfaqpBx1AtCaob7fSuC5tx695rrJV390YUneyMB13NvEzeWBGa/YrEBY bQov/UKNxvdRUI1BpS+Dj5ass8S2V/TRajeVRHXO24+03+qVGn1nC/f5OHUpKG5RfvXsUXCenqN fW/YrWIYPHyoKHHTEQP6XHOn1wEl/2vEodyjwKPP2UdlD1999MmAPEhWTYwn9+VP97Mk+wz/Flo bj8ajMdnb1eCYXBxO4hOMFkLHq7re/W7rIfflQvoNGAdoKDHW4AeSSn9COWNMzeHOGCW3/Ca7em kdwOE9m2UqYZjfUIk2n3WKx0bzrFvjaoDJ+xXX+4pITwBex3gppjM8LnbbB5bVEW2HgD7ypx40B TxB9sEmNU5fHb8cSdlCGjxn2oJO8qFqi6eyxqi8rZYh9e5HjKFurPifewlv6/FGLXHzcqzVnELo SyF8tGUumWuZ2Yh8huUcSHS0n0mP+tbT6BiqNQDNQqNU1n9UyRcA1GeT2PRm+I/GND7l3EqK771 JCcuQPo8PTFfkiRYMpE5xJjFRypeDVoHvGmccGyzpEmXm2ZeJYEBkUZqK6d+Bcy5g== X-Received: by 2002:a17:90b:2548:b0:36b:4d63:4a93 with SMTP id 98e67ed59e1d1-38d15364030mr19810776a91.13.1784072342552; Tue, 14 Jul 2026 16:39:02 -0700 (PDT) Received: from ryzen.lan ([2601:644:8000:7a86::e34]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3118389d9bcsm72317509eec.20.2026.07.14.16.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 16:39:01 -0700 (PDT) From: Rosen Penev To: dmaengine@vger.kernel.org Cc: Vinod Koul , Frank Li , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/3] dma: fsl_raid: use devm_platform_ioremap_resource Date: Tue, 14 Jul 2026 16:38:55 -0700 Message-ID: <20260714233855.870797-4-rosenp@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260714233855.870797-1-rosenp@gmail.com> References: <20260714233855.870797-1-rosenp@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Replace the open-coded platform_get_resource() plus devm_ioremap() sequence with devm_platform_ioremap_resource(), which fetches the resource, requests the region and maps it in one call. Switch the error check to IS_ERR()/PTR_ERR() and drop the now-unused struct resource pointer. The raideng node has a single reg region (0x320000, 0x10000); the job-queue/ring children are separate OF devices probed independently, so the region reservation added by devm_ioremap_resource() is exclusive and does not introduce overlap failures. Assisted-by: opencode:hy3-free Signed-off-by: Rosen Penev Reviewed-by: Frank Li --- drivers/dma/fsl_raid.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/dma/fsl_raid.c b/drivers/dma/fsl_raid.c index 47ebdf274331..aadb3dcb1b03 100644 --- a/drivers/dma/fsl_raid.c +++ b/drivers/dma/fsl_raid.c @@ -747,24 +747,20 @@ static int fsl_re_probe(struct platform_device *ofdev) u32 off; u8 ridx =3D 0; struct dma_device *dma_dev; - struct resource *res; struct fsl_re_ctrl __iomem *re_regs; int rc; struct device *dev =3D &ofdev->dev; =20 + /* IOMAP the entire RAID Engine region */ + re_regs =3D devm_platform_ioremap_resource(ofdev, 0); + if (IS_ERR(re_regs)) + return PTR_ERR(re_regs); + re_priv =3D devm_kzalloc(dev, sizeof(*re_priv), GFP_KERNEL); if (!re_priv) return -ENOMEM; =20 - res =3D platform_get_resource(ofdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - - /* IOMAP the entire RAID Engine region */ - re_priv->re_regs =3D devm_ioremap(dev, res->start, resource_size(res)); - if (!re_priv->re_regs) - return -EBUSY; - re_regs =3D re_priv->re_regs; + re_priv->re_regs =3D re_regs; =20 /* Program the RE mode */ out_be32(&re_regs->global_config, FSL_RE_NON_DPAA_MODE); --=20 2.55.0