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charset="utf-8" Some Rockchip SoCs, such as the RV1106, give each GPIO bank its own IO control (IOC) register block rather than grouping the registers of all banks into a shared GRF region. Add an optional rockchip,grf property to the gpio-bank binding so that each bank node can reference the syscon for its own IOC block. Signed-off-by: Simon Glass --- Changes in v2: - Add new patch for the per-bank IOC reference .../devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml= b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml index bdd83f42615c..774e9c7de606 100644 --- a/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml +++ b/Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml @@ -44,6 +44,13 @@ properties: power-domains: maxItems: 1 =20 + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node managing the IO control registers + of this bank, on SoCs such as the RV1106 where each GPIO bank has + its own IOC block. + patternProperties: "^.+-hog(-[0-9]+)?$": type: object --=20 2.43.0 From nobody Sat Jul 25 18:53:40 2026 Received: from mail-ot1-f53.google.com (mail-ot1-f53.google.com [209.85.210.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77BEE4F799D for ; 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Tue, 14 Jul 2026 12:25:56 -0700 (PDT) Received: from chromium.org ([174.51.25.52]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4519d89f7desm15759043fac.7.2026.07.14.12.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 12:25:56 -0700 (PDT) From: Simon Glass To: Linus Walleij Cc: Heiko Stuebner , Rob Herring , Jonas Karlman , Conor Dooley , linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Simon Glass , Jeffy Chen , huang lin , linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] dt-bindings: pinctrl: rockchip: Add RV1106 compatible Date: Tue, 14 Jul 2026 13:25:30 -0600 Message-ID: <20260714132531.v2.2.3a4f9d47d4dba36e14141f8796afe8907028aa9c@changeid> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714192535.2082729-1-sjg@chromium.org> References: <20260714192535.2082729-1-sjg@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the compatible for the pin controller of the Rockchip RV1106 and its RV1103 package variant. Signed-off-by: Simon Glass Acked-by: Rob Herring (Arm) --- (no changes since v1) Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yam= l b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml index 9b3cbeb54fed..81747bb53056 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml @@ -51,6 +51,7 @@ properties: - rockchip,rk3576-pinctrl - rockchip,rk3588-pinctrl - rockchip,rv1103b-pinctrl + - rockchip,rv1106-pinctrl - rockchip,rv1108-pinctrl - rockchip,rv1126-pinctrl =20 --=20 2.43.0 From nobody Sat Jul 25 18:53:40 2026 Received: from mail-oo1-f49.google.com (mail-oo1-f49.google.com [209.85.161.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16973418A2F for ; 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Tue, 14 Jul 2026 12:25:58 -0700 (PDT) Received: from chromium.org ([174.51.25.52]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4519d89f7desm15759043fac.7.2026.07.14.12.25.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 12:25:58 -0700 (PDT) From: Simon Glass To: Linus Walleij Cc: Heiko Stuebner , Rob Herring , Jonas Karlman , Conor Dooley , linux-gpio@vger.kernel.org, linux-rockchip@lists.infradead.org, Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Simon Glass , Jeffy Chen , huang lin , linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] pinctrl: rockchip: Add RV1106 pinctrl support Date: Tue, 14 Jul 2026 13:25:31 -0600 Message-ID: <20260714132531.v2.3.0af20e702c540f54a3d1694654b158a9b783d68e@changeid> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714192535.2082729-1-sjg@chromium.org> References: <20260714192535.2082729-1-sjg@chromium.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add pinctrl support for the Rockchip RV1106, based on the vendor kernel in the Luckfox Pico SDK [1] at commit 824b817f8 (a Linux 5.10.160 kernel tree). Each GPIO bank has its own IO control (IOC) register block, referenced by the rockchip,grf phandle of the bank node; the register offsets are relative to the bank's own block. The drive strength uses the RK3568-style exponential encoding and only pins 0-6 of GPIO0 have drive-strength registers. The RV1103 is a package variant of the RV1106 with fewer pins and uses the same pin controller. [1] https://github.com/LuckfoxTECH/luckfox-pico Signed-off-by: Simon Glass Reviewed-by: Heiko Stuebner --- Changes in v2: - Use a separate IOC regmap per bank, taken from the rockchip,grf phandle of each bank node and identified by the gpio alias, with block-relative register offsets - Reject drive-strength requests for GPIO0 pins above 6, which have no drive-strength registers - Specify only the first iomux offset for each bank, letting the driver calculate the increments drivers/pinctrl/pinctrl-rockchip.c | 168 +++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-rockchip.h | 4 + 2 files changed, 172 insertions(+) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-r= ockchip.c index 7e0fcd45fd26..0589a7a0879f 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -1188,6 +1188,10 @@ static int rockchip_get_mux(struct rockchip_pin_bank= *bank, int pin) else regmap =3D info->regmap_base; =20 + /* Banks with their own IOC block use its regmap for the iomux */ + if (bank->regmap_ioc) + regmap =3D bank->regmap_ioc; + if (ctrl->type =3D=3D RV1103B && bank->bank_num =3D=3D 2 && pin >=3D 12) return 0; =20 @@ -1317,6 +1321,10 @@ static int rockchip_set_mux(struct rockchip_pin_bank= *bank, int pin, int mux) else regmap =3D info->regmap_base; =20 + /* Banks with their own IOC block use its regmap for the iomux */ + if (bank->regmap_ioc) + regmap =3D bank->regmap_ioc; + if (ctrl->type =3D=3D RV1103B && bank->bank_num =3D=3D 2 && pin >=3D 12) return 0; =20 @@ -1725,6 +1733,78 @@ static int rv1103b_calc_schmitt_reg_and_bit(struct r= ockchip_pin_bank *bank, return 0; } =20 +#define RV1106_DRV_BITS_PER_PIN 8 +#define RV1106_DRV_PINS_PER_REG 2 +#define RV1106_PULL_BITS_PER_PIN 2 +#define RV1106_PULL_PINS_PER_REG 8 +#define RV1106_SMT_BITS_PER_PIN 1 +#define RV1106_SMT_PINS_PER_REG 8 + +/* + * Each bank has its own IOC block, referenced by the rockchip,grf + * phandle of the bank node. The offsets below are relative to the + * bank's own block. + */ +static const int rv1106_drv_offsets[] =3D { 0x10, 0x80, 0xc0, 0x100, 0x20 = }; +static const int rv1106_pull_offsets[] =3D { 0x38, 0x1c0, 0x1d0, 0x1e0, 0x= 70 }; +static const int rv1106_smt_offsets[] =3D { 0x40, 0x280, 0x290, 0x2a0, 0xa= 0 }; + +static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >=3D ARRAY_SIZE(rv1106_drv_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + /* Only pins 0-6 of GPIO0 have drive-strength registers */ + if (bank->bank_num =3D=3D 0 && pin_num > 6) + return -ENOTSUPP; + + *regmap =3D bank->regmap_ioc; + *reg =3D rv1106_drv_offsets[bank->bank_num]; + *reg +=3D ((pin_num / RV1106_DRV_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1106_DRV_PINS_PER_REG; + *bit *=3D RV1106_DRV_BITS_PER_PIN; + + return 0; +} + +static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >=3D ARRAY_SIZE(rv1106_pull_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + *regmap =3D bank->regmap_ioc; + *reg =3D rv1106_pull_offsets[bank->bank_num]; + *reg +=3D ((pin_num / RV1106_PULL_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1106_PULL_PINS_PER_REG; + *bit *=3D RV1106_PULL_BITS_PER_PIN; + + return 0; +} + +static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + if (bank->bank_num >=3D ARRAY_SIZE(rv1106_smt_offsets) || + !bank->regmap_ioc) + return -EINVAL; + + *regmap =3D bank->regmap_ioc; + *reg =3D rv1106_smt_offsets[bank->bank_num]; + *reg +=3D ((pin_num / RV1106_SMT_PINS_PER_REG) * 4); + *bit =3D pin_num % RV1106_SMT_PINS_PER_REG; + *bit *=3D RV1106_SMT_BITS_PER_PIN; + + return 0; +} + #define RV1108_PULL_PMU_OFFSET 0x10 #define RV1108_PULL_OFFSET 0x110 #define RV1108_PULL_PINS_PER_REG 8 @@ -3310,6 +3390,7 @@ static int rockchip_set_drive_perpin(struct rockchip_= pin_bank *bank, ret =3D strength; goto config; } else if (ctrl->type =3D=3D RV1103B || + ctrl->type =3D=3D RV1106 || ctrl->type =3D=3D RK3506 || ctrl->type =3D=3D RK3528 || ctrl->type =3D=3D RK3562 || @@ -3482,6 +3563,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank= *bank, int pin_num) : PIN_CONFIG_BIAS_DISABLE; case PX30: case RV1103B: + case RV1106: case RV1108: case RK3188: case RK3288: @@ -3547,6 +3629,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank= *bank, break; case PX30: case RV1103B: + case RV1106: case RV1108: case RV1126: case RK3188: @@ -3843,6 +3926,7 @@ static bool rockchip_pinconf_pull_valid(struct rockch= ip_pin_ctrl *ctrl, return pull ? false : true; case PX30: case RV1103B: + case RV1106: case RV1108: case RV1126: case RK3188: @@ -4452,6 +4536,7 @@ static int rockchip_pinctrl_probe(struct platform_dev= ice *pdev) struct resource *res; void __iomem *base; int ret; + int i; =20 if (!dev->of_node) return dev_err_probe(dev, -ENODEV, "device tree node not found\n"); @@ -4505,6 +4590,44 @@ static int rockchip_pinctrl_probe(struct platform_de= vice *pdev) /* try to find the optional reference to the ioc1 syscon */ info->regmap_ioc1 =3D syscon_regmap_lookup_by_phandle_optional(np, "rockc= hip,ioc1"); =20 + /* + * On SoCs where each GPIO bank has its own IOC block, the bank nodes + * carry a rockchip,grf phandle pointing at it. The bank number comes + * from the gpio alias, as used by the gpio driver, falling back to + * the node position for devicetrees without aliases. The fallback is + * wrong when an SoC variant omits a bank, so aliases are needed + * there. + */ + i =3D 0; + for_each_child_of_node_scoped(np, child) { + struct rockchip_pin_bank *bank =3D NULL; + int id, j; + + if (!of_match_node(rockchip_bank_match, child)) + continue; + + id =3D of_alias_get_id(child, "gpio"); + if (id < 0) + id =3D i; + i++; + + for (j =3D 0; j < ctrl->nr_banks; j++) { + if (ctrl->pin_banks[j].bank_num =3D=3D id) { + bank =3D &ctrl->pin_banks[j]; + break; + } + } + if (!bank) + continue; + + bank->regmap_ioc =3D syscon_regmap_lookup_by_phandle_optional( + child, "rockchip,grf"); + if (IS_ERR(bank->regmap_ioc)) + return dev_err_probe(dev, PTR_ERR(bank->regmap_ioc), + "%pOFn: failed to look up bank ioc\n", + child); + } + ret =3D rockchip_pinctrl_register(pdev, info); if (ret) return ret; @@ -4623,6 +4746,49 @@ static struct rockchip_pin_ctrl rv1103b_pin_ctrl __m= aybe_unused =3D { .schmitt_calc_reg =3D rv1103b_calc_schmitt_reg_and_bit, }; =20 +static struct rockchip_pin_bank rv1106_pin_banks[] =3D { + PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, -1, -1, -1), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, -1, -1, -1), + PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x20, -1, -1, -1), + PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x40, -1, -1, -1), + PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0, + 0, -1, -1, -1), +}; + +static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused =3D { + .pin_banks =3D rv1106_pin_banks, + .nr_banks =3D ARRAY_SIZE(rv1106_pin_banks), + .label =3D "RV1106-GPIO", + .type =3D RV1106, + .pull_calc_reg =3D rv1106_calc_pull_reg_and_bit, + .drv_calc_reg =3D rv1106_calc_drv_reg_and_bit, + .schmitt_calc_reg =3D rv1106_calc_schmitt_reg_and_bit, +}; + static struct rockchip_pin_bank rv1108_pin_banks[] =3D { PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU, IOMUX_SOURCE_PMU, @@ -5261,6 +5427,8 @@ static const struct of_device_id rockchip_pinctrl_dt_= match[] =3D { .data =3D &px30_pin_ctrl }, { .compatible =3D "rockchip,rv1103b-pinctrl", .data =3D &rv1103b_pin_ctrl }, + { .compatible =3D "rockchip,rv1106-pinctrl", + .data =3D &rv1106_pin_ctrl }, { .compatible =3D "rockchip,rv1108-pinctrl", .data =3D &rv1108_pin_ctrl }, { .compatible =3D "rockchip,rv1126-pinctrl", diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-r= ockchip.h index bb0e803e3b8a..f62213d99792 100644 --- a/drivers/pinctrl/pinctrl-rockchip.h +++ b/drivers/pinctrl/pinctrl-rockchip.h @@ -186,6 +186,7 @@ enum rockchip_pinctrl_type { PX30, RV1103B, + RV1106, RV1108, RV1126, RK2928, @@ -295,6 +296,8 @@ struct rockchip_drv { * @dev: the pinctrl device bind to the bank * @reg_base: register base of the gpio bank * @regmap_pull: optional separate register for additional pull settings + * @regmap_ioc: optional per-bank IO control regmap, for SoCs where each + * bank has its own IOC block * @clk: clock of the gpio bank * @db_clk: clock of the gpio debounce * @irq: interrupt of the gpio bank @@ -323,6 +326,7 @@ struct rockchip_pin_bank { struct device *dev; void __iomem *reg_base; struct regmap *regmap_pull; + struct regmap *regmap_ioc; struct clk *clk; struct clk *db_clk; int irq; --=20 2.43.0