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charset="utf-8" PME, hotplug, and bandwidth notification are all services of the PCI Express Capability and share a single MSI/MSI-X interrupt vector. The set of these services is open-coded as a bitmask in more than one place, which is repetitive and easy to get out of sync as services are added. Define a single PCIE_PORT_SERVICE_EXPCAP mask and use it in place of the open-coded expressions. No functional change intended. Signed-off-by: Yazen Ghannam Assisted-by: Claude:claude-opus-4-8 --- drivers/pci/pcie/portdrv.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 2d6aa488fe7b..53144c99cb3c 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -29,6 +29,10 @@ */ #define PCIE_PORT_MAX_MSI_ENTRIES 32 =20 +#define PCIE_PORT_SERVICE_EXPCAP (PCIE_PORT_SERVICE_PME | \ + PCIE_PORT_SERVICE_HP | \ + PCIE_PORT_SERVICE_BWCTRL) + #define get_descriptor_id(type, service) (((type - 4) << 8) | service) =20 struct portdrv_service_data { @@ -67,8 +71,7 @@ static int pcie_message_numbers(struct pci_dev *dev, int = mask, * 7.8.2, 7.10.10, 7.31.2. */ =20 - if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | - PCIE_PORT_SERVICE_BWCTRL)) { + if (mask & PCIE_PORT_SERVICE_EXPCAP) { pcie_capability_read_word(dev, PCI_EXP_FLAGS, ®16); *pme =3D FIELD_GET(PCI_EXP_FLAGS_IRQ, reg16); nvec =3D *pme + 1; @@ -149,8 +152,7 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev= , int *irqs, int mask) } =20 /* PME, hotplug and bandwidth notification share an MSI/MSI-X vector */ - if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP | - PCIE_PORT_SERVICE_BWCTRL)) { + if (mask & PCIE_PORT_SERVICE_EXPCAP) { pcie_irq =3D pci_irq_vector(dev, pme); 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7L8/YgiDHNzNKdHP41Z2pKrE6cY+Afkh1Kir0kZlu/PjZeZjWKEcUw2/cIyLnQuMt6tKqyDHca70eiqKP0pxuPNyJsDlW0hFziRJE1G/XFW4yntlctWw/Y5vqOKSddFZF9eGp93S6OJ4egbEOJkyWrAQFFTIOP0VZa8t9vn81H3gB0M/ysT2xCobyImG04OXt6DMsqYbKi45CSKkfkoQbIspZnkBzH8PZPHrPTc0dKQGo4tYpoO8m2dwnJfvCJyzIwg/Ex9pDKaLacffbmGqiMSRfQG7yutfP/AgM520k7NiqCdWDkTvWFvC1zmhMLrT8ux8p0sql+auquHPi/51PR+p3OZIZuvUCeTRX6SJ7EzhMi22SbsodUPJEqI6cXPksOsID3qsIiEBM9xJNuvCdYhUQ7+bTFjmPNw0Z04IGspsTtNybHt3T3rcvE+Jkt0K X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2026 18:40:06.4996 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 26acf787-cea8-4d50-6ae8-08dee1d75354 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00006000.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9479 From: Avadhut Naik PCIe r6.0 introduced Flit Logging Extended Capability for logging erroneous flits. This extended capability must be implemented by ports and RCRBs that support PCIe Gen6 Flit Mode.[1] Introduce support required for the Extended Capability as a port service driver. [1] PCI Express=C2=AE Base Specification Revision 6.0, section 7.7.8 [Yazen: Fix ups, etc.] Signed-off-by: Avadhut Naik Co-developed-by: Yazen Ghannam Signed-off-by: Yazen Ghannam Assisted-by: Claude:claude-opus-4-8 --- drivers/pci/pci.h | 6 ++ drivers/pci/pcie/Kconfig | 10 ++ drivers/pci/pcie/Makefile | 1 + drivers/pci/pcie/flit.c | 170 ++++++++++++++++++++++++++++++++++ drivers/pci/pcie/portdrv.c | 15 ++- drivers/pci/pcie/portdrv.h | 10 +- drivers/pci/probe.c | 1 + include/linux/pci.h | 4 + include/uapi/linux/pci_regs.h | 14 ++- 9 files changed, 227 insertions(+), 4 deletions(-) create mode 100644 drivers/pci/pcie/flit.c diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 4469e1a77f3c..31d04366b980 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -894,6 +894,12 @@ static inline void pci_dpc_init(struct pci_dev *pdev) = { } static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false;= } #endif =20 +#ifdef CONFIG_PCIE_FLIT +void pci_flit_init(struct pci_dev *pdev); +#else +static inline void pci_flit_init(struct pci_dev *pdev) { } +#endif + #ifdef CONFIG_PCIEPORTBUS void pci_rcec_init(struct pci_dev *dev); void pci_rcec_exit(struct pci_dev *dev); diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 207c2deae35f..1ee3c85e63c1 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -146,3 +146,13 @@ config PCIE_EDR the PCI Firmware Specification r3.2. Enable this if you want to support hybrid DPC model which uses both firmware and OS to implement DPC. + +config PCIE_FLIT + bool "PCI Express Flit Mode Error Logging support" + depends on PCIEPORTBUS + help + This enables support for the PCI Express Flit Logging Extended + Capability, which logs errors encountered by a port operating + in PCIe Gen6 Flit Mode. If your system doesn't have this + capability or you do not want to use this feature, it is safe + to answer N. diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile index b0b43a18c304..14a5222920b9 100644 --- a/drivers/pci/pcie/Makefile +++ b/drivers/pci/pcie/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_PCIE_PME) +=3D pme.o obj-$(CONFIG_PCIE_DPC) +=3D dpc.o obj-$(CONFIG_PCIE_PTM) +=3D ptm.o obj-$(CONFIG_PCIE_EDR) +=3D edr.o +obj-$(CONFIG_PCIE_FLIT) +=3D flit.o diff --git a/drivers/pci/pcie/flit.c b/drivers/pci/pcie/flit.c new file mode 100644 index 000000000000..12f2b6fbf1de --- /dev/null +++ b/drivers/pci/pcie/flit.c @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Service driver for PCIe Flit Logging Capability + * + * Copyright (c) 2026, Advanced Micro Devices, Inc. + * All Rights Reserved. + * + * Authors: Avadhut Naik + * Yazen Ghannam + */ + +#define pr_fmt(fmt) "Flit: " fmt +#define dev_fmt pr_fmt + +#include +#include +#include +#include "portdrv.h" +#include "../pci.h" + +void pci_flit_init(struct pci_dev *pdev) +{ + u16 cap; + + if (pcie_capability_read_word(pdev, PCI_EXP_FLAGS, &cap)) + return; + + if (!(cap & PCI_EXP_FLAGS_FLIT)) + return; + + pdev->flit_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_FLIT); + if (pdev->flit_cap) + pci_dbg(pdev, "Flit Mode Error Logging Capability present.\n"); +} + +static void flit_cntr_enable(struct pci_dev *pdev) +{ + u16 flit =3D pdev->flit_cap; + u16 reg; + + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_STA, ®); + pci_write_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_STA, reg); + + /* + * NOTE: The "Set Events to Count" and "Trigger Event Count" fields + * are left as set by the platform. + */ + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, ®); + reg |=3D PCI_FLIT_ERR_CNTR_EN; + reg |=3D PCI_FLIT_ERR_CNTR_INTR_EN; + pci_write_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, reg); +} + +static void flit_cntr_disable(struct pcie_device *dev) +{ + struct pci_dev *pdev =3D dev->port; + u16 ctrl, flit =3D pdev->flit_cap; + + /* Disable both Error Counter and Interrupt generation */ + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, &ctrl); + ctrl &=3D ~(PCI_FLIT_ERR_CNTR_EN | PCI_FLIT_ERR_CNTR_INTR_EN); + pci_write_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, ctrl); +} + +static irqreturn_t flit_isr(int irq, void *context) +{ + struct pcie_device *dev =3D (struct pcie_device *)context; + struct pci_dev *pdev =3D dev->port; + u16 flit =3D pdev->flit_cap; + u16 cntr_ctrl, cntr_sta; + u32 err_log1, err_log2; + + /* Read and log Counter and Error Log Registers. */ + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, &cntr_ctrl); + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_STA, &cntr_sta); + + pci_info(pdev, HW_ERR "Counter Control: 0x%04x Counter Status: 0x%04x\n",= cntr_ctrl, cntr_sta); + + do { + pci_read_config_dword(pdev, flit + PCI_FLIT_ERR_LOG1, &err_log1); + + if (!(err_log1 & PCI_FLIT_ERR_LOG_VALID)) + break; + + pci_read_config_dword(pdev, flit + PCI_FLIT_ERR_LOG2, &err_log2); + pci_info(pdev, HW_ERR " Error Log1: 0x%08x Error Log2: 0x%08x\n", err_l= og1, err_log2); + + pci_write_config_dword(pdev, flit + PCI_FLIT_ERR_LOG1, err_log1); + } while (err_log1 & PCI_FLIT_ERR_LOG_MORE); + + /* + * Re-enabling the counter is the interrupt acknowledgment. + * + * The status bit checked in flit_irq() (Interrupt Generated based on + * Trigger Event Count) is cleared by a 0->1 transition of Flit Error + * Counter Enable, per PCIe r6.4 Table 7-96. + */ + cntr_ctrl |=3D PCI_FLIT_ERR_CNTR_EN; + pci_write_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, cntr_ctrl); + return IRQ_HANDLED; +} + +static irqreturn_t flit_irq(int irq, void *context) +{ + struct pcie_device *dev =3D (struct pcie_device *)context; + struct pci_dev *pdev =3D dev->port; + u16 flit =3D pdev->flit_cap; + u16 cntr_sta, cntr_ctrl; + + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_STA, &cntr_sta); + if (!(cntr_sta & PCI_FLIT_INTR_GEN_CNTR)) + return IRQ_NONE; + + pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, &cntr_ctrl); + cntr_ctrl &=3D ~PCI_FLIT_ERR_CNTR_EN; + pci_write_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, cntr_ctrl); + return IRQ_WAKE_THREAD; +} + +static int flit_probe(struct pcie_device *dev) +{ + struct device *device =3D &dev->device; + struct pci_dev *pdev =3D dev->port; + int status; + + status =3D devm_request_threaded_irq(device, dev->irq, flit_irq, + flit_isr, IRQF_SHARED, + "pcie-flit", dev); + if (status) { + pci_warn(pdev, "request Flit IRQ%d failed: %d\n", dev->irq, status); + return status; + } + + flit_cntr_enable(pdev); + pci_info(pdev, "enabled with IRQ %d\n", dev->irq); + + return 0; +} + +static int flit_cntr_suspend(struct pcie_device *dev) +{ + flit_cntr_disable(dev); + return 0; +} + +static int flit_cntr_resume(struct pcie_device *dev) +{ + flit_cntr_enable(dev->port); + return 0; +} + +static void flit_cntr_remove(struct pcie_device *dev) +{ + flit_cntr_disable(dev); +} + +static struct pcie_port_service_driver flitdriver =3D { + .name =3D "flit", + .port_type =3D PCIE_ANY_PORT, + .service =3D PCIE_PORT_SERVICE_FLIT, + .probe =3D flit_probe, + .suspend =3D flit_cntr_suspend, + .resume =3D flit_cntr_resume, + .remove =3D flit_cntr_remove, +}; + +int __init pcie_flit_init(void) +{ + return pcie_port_service_register(&flitdriver); +} diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 53144c99cb3c..1a649d6f4ab8 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -31,7 +31,8 @@ =20 #define PCIE_PORT_SERVICE_EXPCAP (PCIE_PORT_SERVICE_PME | \ PCIE_PORT_SERVICE_HP | \ - PCIE_PORT_SERVICE_BWCTRL) + PCIE_PORT_SERVICE_BWCTRL | \ + PCIE_PORT_SERVICE_FLIT) =20 #define get_descriptor_id(type, service) (((type - 4) << 8) | service) =20 @@ -151,12 +152,16 @@ static int pcie_port_enable_irq_vec(struct pci_dev *d= ev, int *irqs, int mask) return nr_entries; } =20 - /* PME, hotplug and bandwidth notification share an MSI/MSI-X vector */ + /* + * PME, hotplug, flit error counter, and bandwidth notification share + * an MSI/MSI-X vector + */ if (mask & PCIE_PORT_SERVICE_EXPCAP) { pcie_irq =3D pci_irq_vector(dev, pme); irqs[PCIE_PORT_SERVICE_PME_SHIFT] =3D pcie_irq; irqs[PCIE_PORT_SERVICE_HP_SHIFT] =3D pcie_irq; irqs[PCIE_PORT_SERVICE_BWCTRL_SHIFT] =3D pcie_irq; + irqs[PCIE_PORT_SERVICE_FLIT_SHIFT] =3D pcie_irq; } =20 if (mask & PCIE_PORT_SERVICE_AER) @@ -280,6 +285,11 @@ static int get_port_device_capability(struct pci_dev *= dev) services |=3D PCIE_PORT_SERVICE_BWCTRL; } =20 +#ifdef CONFIG_PCIE_FLIT + if (dev->flit_cap) + services |=3D PCIE_PORT_SERVICE_FLIT; +#endif + return services; } =20 @@ -836,6 +846,7 @@ static void __init pcie_init_services(void) pcie_dpc_init(); pcie_bwctrl_init(); pcie_hp_init(); + pcie_flit_init(); } =20 static int __init pcie_portdrv_init(void) diff --git a/drivers/pci/pcie/portdrv.h b/drivers/pci/pcie/portdrv.h index cc58bf2f2c84..db80faecf34c 100644 --- a/drivers/pci/pcie/portdrv.h +++ b/drivers/pci/pcie/portdrv.h @@ -22,8 +22,10 @@ #define PCIE_PORT_SERVICE_DPC (1 << PCIE_PORT_SERVICE_DPC_SHIFT) #define PCIE_PORT_SERVICE_BWCTRL_SHIFT 4 /* Bandwidth Controller (notifica= tions) */ #define PCIE_PORT_SERVICE_BWCTRL (1 << PCIE_PORT_SERVICE_BWCTRL_SHIFT) +#define PCIE_PORT_SERVICE_FLIT_SHIFT 5 /* Flit Logging */ +#define PCIE_PORT_SERVICE_FLIT (1 << PCIE_PORT_SERVICE_FLIT_SHIFT) =20 -#define PCIE_PORT_DEVICE_MAXSERVICES 5 +#define PCIE_PORT_DEVICE_MAXSERVICES 6 =20 extern bool pcie_ports_dpc_native; =20 @@ -51,6 +53,12 @@ int pcie_dpc_init(void); static inline int pcie_dpc_init(void) { return 0; } #endif =20 +#ifdef CONFIG_PCIE_FLIT +int pcie_flit_init(void); +#else +static inline int pcie_flit_init(void) { return 0; } +#endif + int pcie_bwctrl_init(void); =20 /* Port Type */ diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index dd0abbc63e18..a1ec44b04eb0 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -2666,6 +2666,7 @@ static void pci_init_capabilities(struct pci_dev *dev) pci_pasid_init(dev); /* Process Address Space ID */ pci_acs_init(dev); /* Access Control Services */ pci_ptm_init(dev); /* Precision Time Measurement */ + pci_flit_init(dev); /* Flit Logging */ pci_aer_init(dev); /* Advanced Error Reporting */ pci_dpc_init(dev); /* Downstream Port Containment */ pci_rcec_init(dev); /* Root Complex Event Collector */ diff --git a/include/linux/pci.h b/include/linux/pci.h index ebb5b9d76360..a8d8dbac6640 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -592,6 +592,10 @@ struct pci_dev { u8 tph_mode; /* TPH mode */ u8 tph_req_type; /* TPH requester type */ #endif + +#ifdef CONFIG_PCIE_FLIT + u16 flit_cap; /* Flit Logging Capabilities */ +#endif }; =20 static inline struct pci_dev *pci_physfn(struct pci_dev *dev) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index facaa324bd86..774eeed80bed 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -763,7 +763,8 @@ #define PCI_EXT_CAP_ID_DEV3 0x2F /* Device 3 Capability/Control/Status */ #define PCI_EXT_CAP_ID_IDE 0x30 /* Integrity and Data Encryption */ #define PCI_EXT_CAP_ID_PL_64GT 0x31 /* Physical Layer 64.0 GT/s */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_64GT +#define PCI_EXT_CAP_ID_FLIT 0x32 /* Flit Error Logging */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_FLIT =20 #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 @@ -1187,6 +1188,17 @@ /* Physical Layer 64.0 GT/s */ #define PCI_PL_64GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ =20 +/* Flit Mode Error Logging */ +#define PCI_FLIT_ERR_LOG1 0x04 /* Flit Error Log 1 Register */ +#define PCI_FLIT_ERR_LOG_VALID 0x1 /* Flit Error Log Valid */ +#define PCI_FLIT_ERR_LOG_MORE 0x2000 /* More Entries Valid */ +#define PCI_FLIT_ERR_LOG2 0x08 /* Flit Error Log 2 Register */ +#define PCI_FLIT_ERR_CNTR_CTRL 0x0c /* Flit Error Counter Control Regist= er */ +#define PCI_FLIT_ERR_CNTR_EN 0x0001 /* Flit Error Counter Enable */ +#define PCI_FLIT_ERR_CNTR_INTR_EN 0x0002 /* Flit Error Counter Interrupt= Enable */ +#define PCI_FLIT_ERR_CNTR_STA 0x0e /* Flit Error Counter Status Register= */ +#define PCI_FLIT_INTR_GEN_CNTR 0x0008 /* Interrupt on Trigger Event Cou= nt */ + /* Native PCIe Enclosure Management */ #define PCI_NPEM_CAP 0x04 /* NPEM capability register */ #define PCI_NPEM_CAP_CAPABLE 0x00000001 /* NPEM Capable */ --=20 2.53.0 From nobody Sat Jul 25 18:54:00 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011052.outbound.protection.outlook.com [40.107.208.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3C5A377A9D; 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charset="utf-8" The Flit Logging Extended Capability may be managed by the platform firmware. Negotiate ownership through _OSC before the OS enables the Flit Error Counter, and only register the port service when the OS is granted native control. Advertise support via a new OSC_PCI_EXPRESS_FLIT_CONTROL bit, record the negotiated result in the host bridge's native_flit flag, and gate the Flit port service on it. Signed-off-by: Yazen Ghannam Assisted-by: Claude:claude-opus-4-8 --- drivers/acpi/pci_root.c | 6 ++++++ drivers/pci/pcie/portdrv.c | 2 +- drivers/pci/probe.c | 1 + include/linux/acpi.h | 1 + include/linux/pci.h | 1 + 5 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c index 4c06c3ffd0cb..e6f74b8129a3 100644 --- a/drivers/acpi/pci_root.c +++ b/drivers/acpi/pci_root.c @@ -136,6 +136,7 @@ static struct pci_osc_bit_struct pci_osc_control_bit[] = =3D { { OSC_PCI_EXPRESS_CAPABILITY_CONTROL, "PCIeCapability" }, { OSC_PCI_EXPRESS_LTR_CONTROL, "LTR" }, { OSC_PCI_EXPRESS_DPC_CONTROL, "DPC" }, + { OSC_PCI_EXPRESS_FLIT_CONTROL, "FlitErrorLogging" }, }; =20 static struct pci_osc_bit_struct cxl_osc_support_bit[] =3D { @@ -523,6 +524,9 @@ static u32 calculate_control(void) if (IS_ENABLED(CONFIG_PCIE_DPC) && IS_ENABLED(CONFIG_PCIE_EDR)) control |=3D OSC_PCI_EXPRESS_DPC_CONTROL; =20 + if (IS_ENABLED(CONFIG_PCIE_FLIT)) + control |=3D OSC_PCI_EXPRESS_FLIT_CONTROL; + return control; } =20 @@ -1039,6 +1043,8 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_= root *root, host_bridge->native_ltr =3D 0; if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL)) host_bridge->native_dpc =3D 0; + if (!(root->osc_control_set & OSC_PCI_EXPRESS_FLIT_CONTROL)) + host_bridge->native_flit =3D 0; =20 if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL)) host_bridge->native_cxl_error =3D 0; diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 1a649d6f4ab8..ef224e7243f3 100644 --- a/drivers/pci/pcie/portdrv.c +++ b/drivers/pci/pcie/portdrv.c @@ -286,7 +286,7 @@ static int get_port_device_capability(struct pci_dev *d= ev) } =20 #ifdef CONFIG_PCIE_FLIT - if (dev->flit_cap) + if (dev->flit_cap && host->native_flit) services |=3D PCIE_PORT_SERVICE_FLIT; #endif =20 diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index a1ec44b04eb0..f9183a4ea3b3 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -674,6 +674,7 @@ static void pci_init_host_bridge(struct pci_host_bridge= *bridge) bridge->native_pme =3D 1; bridge->native_ltr =3D 1; bridge->native_dpc =3D 1; + bridge->native_flit =3D 1; bridge->domain_nr =3D PCI_DOMAIN_NR_NOT_SET; bridge->native_cxl_error =3D 1; bridge->dev.type =3D &pci_host_bridge_type; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 10d6c6c11bdf..507cd985ff14 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -644,6 +644,7 @@ extern u32 osc_sb_native_usb4_control; #define OSC_PCI_EXPRESS_CAPABILITY_CONTROL 0x00000010 #define OSC_PCI_EXPRESS_LTR_CONTROL 0x00000020 #define OSC_PCI_EXPRESS_DPC_CONTROL 0x00000080 +#define OSC_PCI_EXPRESS_FLIT_CONTROL 0x00000800 =20 /* CXL _OSC: Capabilities DWORD 4: Support Field */ #define OSC_CXL_1_1_PORT_REG_ACCESS_SUPPORT 0x00000001 diff --git a/include/linux/pci.h b/include/linux/pci.h index a8d8dbac6640..4e4d1d9eb7fe 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -660,6 +660,7 @@ struct pci_host_bridge { unsigned int native_pme:1; /* OS may use PCIe PME */ unsigned int native_ltr:1; /* OS may use PCIe LTR */ unsigned int native_dpc:1; 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charset="utf-8" Emit a trace event for each erroneous flit logged by the Flit Error Counter, capturing the counter control/status and both Error Log registers. This provides a structured, low-overhead record of flit errors that userspace RAS tooling can consume without parsing the kernel log. Signed-off-by: Yazen Ghannam Assisted-by: Claude:claude-opus-4-8 --- drivers/pci/pcie/Kconfig | 1 + drivers/pci/pcie/flit.c | 2 ++ include/ras/ras_event.h | 48 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig index 1ee3c85e63c1..6a0f3abfbfe7 100644 --- a/drivers/pci/pcie/Kconfig +++ b/drivers/pci/pcie/Kconfig @@ -150,6 +150,7 @@ config PCIE_EDR config PCIE_FLIT bool "PCI Express Flit Mode Error Logging support" depends on PCIEPORTBUS + select RAS help This enables support for the PCI Express Flit Logging Extended Capability, which logs errors encountered by a port operating diff --git a/drivers/pci/pcie/flit.c b/drivers/pci/pcie/flit.c index 12f2b6fbf1de..83cf53f39291 100644 --- a/drivers/pci/pcie/flit.c +++ b/drivers/pci/pcie/flit.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "portdrv.h" #include "../pci.h" =20 @@ -84,6 +85,7 @@ static irqreturn_t flit_isr(int irq, void *context) =20 pci_read_config_dword(pdev, flit + PCI_FLIT_ERR_LOG2, &err_log2); pci_info(pdev, HW_ERR " Error Log1: 0x%08x Error Log2: 0x%08x\n", err_l= og1, err_log2); + trace_flit_event(pci_name(pdev), cntr_ctrl, cntr_sta, err_log1, err_log2= ); =20 pci_write_config_dword(pdev, flit + PCI_FLIT_ERR_LOG1, err_log1); } while (err_log1 & PCI_FLIT_ERR_LOG_MORE); diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h index fdb785fa4613..0f02928b5cda 100644 --- a/include/ras/ras_event.h +++ b/include/ras/ras_event.h @@ -381,6 +381,54 @@ TRACE_EVENT(aer_event, "Not available") ); #endif /* CONFIG_PCIEAER */ + +/* + * PCIe Flit Error Logging trace event + * + * These events are generated when the Flit Error Counter of a PCIe Gen6 + * Flit Mode port records one or more erroneous flits. + * + * char * dev_name - The name of the slot where the device resides + * ([domain:]bus:device.function). + * u16 cntr_ctrl - Flit Error Counter Control register value. + * u16 cntr_sta - Flit Error Counter Status register value. + * u32 err_log1 - Flit Error Log 1 register value. + * u32 err_log2 - Flit Error Log 2 register value. + */ +#ifdef CONFIG_PCIE_FLIT +TRACE_EVENT(flit_event, + TP_PROTO(const char *dev_name, + const u16 cntr_ctrl, + const u16 cntr_sta, + const u32 err_log1, + const u32 err_log2), + + TP_ARGS(dev_name, cntr_ctrl, cntr_sta, err_log1, err_log2), + + TP_STRUCT__entry( + __string( dev_name, dev_name ) + __field( u16, cntr_ctrl ) + __field( u16, cntr_sta ) + __field( u32, err_log1 ) + __field( u32, err_log2 ) + ), + + TP_fast_assign( + __assign_str(dev_name); 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charset="utf-8" A high rate of flit errors can flood the kernel log with error counter and error log messages. Model the throttling on the AER capability: give each device its own ratelimit_state, initialized in pci_flit_init() with the default interval and burst, rather than a single static per-call-site limiter shared across all ports. Take one ratelimit decision per interrupt and use it to gate the console output, so a storm on one port cannot suppress logging on another. Leave the flit_error trace event unthrottled so RAS tooling still records every erroneous flit while the log is limited. Expose the interval and burst through per-device sysfs attributes (flit_ratelimit_interval_ms, flit_ratelimit_burst), gated on CAP_SYS_ADMIN, so the limit can be tuned or disabled at runtime. Signed-off-by: Yazen Ghannam Assisted-by: Claude:claude-opus-4-8 --- drivers/pci/pci-sysfs.c | 3 + drivers/pci/pci.h | 1 + drivers/pci/pcie/flit.c | 119 ++++++++++++++++++++++++++++++++++++++-- include/linux/pci.h | 2 + 4 files changed, 121 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c index e985a3854f8d..e85953c249f2 100644 --- a/drivers/pci/pci-sysfs.c +++ b/drivers/pci/pci-sysfs.c @@ -1932,6 +1932,9 @@ const struct attribute_group *pci_dev_attr_groups[] = =3D { &aer_stats_attr_group, &aer_attr_group, #endif +#ifdef CONFIG_PCIE_FLIT + &flit_attr_group, +#endif #ifdef CONFIG_PCIEASPM &aspm_ctrl_attr_group, #endif diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 31d04366b980..28ff4243d125 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -896,6 +896,7 @@ static inline bool pci_dpc_recovered(struct pci_dev *pd= ev) { return false; } =20 #ifdef CONFIG_PCIE_FLIT void pci_flit_init(struct pci_dev *pdev); +extern const struct attribute_group flit_attr_group; #else static inline void pci_flit_init(struct pci_dev *pdev) { } #endif diff --git a/drivers/pci/pcie/flit.c b/drivers/pci/pcie/flit.c index 83cf53f39291..7cb5aff7c552 100644 --- a/drivers/pci/pcie/flit.c +++ b/drivers/pci/pcie/flit.c @@ -12,9 +12,12 @@ #define pr_fmt(fmt) "Flit: " fmt #define dev_fmt pr_fmt =20 +#include #include #include #include +#include +#include #include #include "portdrv.h" #include "../pci.h" @@ -30,10 +33,106 @@ void pci_flit_init(struct pci_dev *pdev) return; =20 pdev->flit_cap =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_FLIT); - if (pdev->flit_cap) - pci_dbg(pdev, "Flit Mode Error Logging Capability present.\n"); + if (!pdev->flit_cap) + return; + + ratelimit_state_init(&pdev->flit_ratelimit, DEFAULT_RATELIMIT_INTERVAL, + DEFAULT_RATELIMIT_BURST); + + pci_dbg(pdev, "Flit Mode Error Logging Capability present.\n"); +} + +/* + * Ratelimit interval + * <=3D0: disabled with ratelimit.interval =3D 0 + * >0: enabled with ratelimit.interval in ms + */ +static ssize_t flit_ratelimit_interval_ms_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + return sysfs_emit(buf, "%d\n", + jiffies_to_msecs(pdev->flit_ratelimit.interval)); +} + +static ssize_t flit_ratelimit_interval_ms_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + int interval; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (kstrtoint(buf, 0, &interval) < 0) + return -EINVAL; + + if (interval <=3D 0) + interval =3D 0; + else + interval =3D msecs_to_jiffies(interval); + + pdev->flit_ratelimit.interval =3D interval; + + return count; +} +static DEVICE_ATTR_RW(flit_ratelimit_interval_ms); + +static ssize_t flit_ratelimit_burst_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + + return sysfs_emit(buf, "%d\n", pdev->flit_ratelimit.burst); +} + +static ssize_t flit_ratelimit_burst_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct pci_dev *pdev =3D to_pci_dev(dev); + int burst; + + if (!capable(CAP_SYS_ADMIN)) + return -EPERM; + + if (kstrtoint(buf, 0, &burst) < 0) + return -EINVAL; + + pdev->flit_ratelimit.burst =3D burst; + + return count; +} +static DEVICE_ATTR_RW(flit_ratelimit_burst); + +static struct attribute *flit_attrs[] =3D { + &dev_attr_flit_ratelimit_interval_ms.attr, + &dev_attr_flit_ratelimit_burst.attr, + NULL +}; + +static umode_t flit_attrs_are_visible(struct kobject *kobj, + struct attribute *a, int n) +{ + struct device *dev =3D kobj_to_dev(kobj); + struct pci_dev *pdev =3D to_pci_dev(dev); + + if (!pdev->flit_cap) + return 0; + + return a->mode; } =20 +const struct attribute_group flit_attr_group =3D { + .name =3D "flit", + .attrs =3D flit_attrs, + .is_visible =3D flit_attrs_are_visible, +}; + static void flit_cntr_enable(struct pci_dev *pdev) { u16 flit =3D pdev->flit_cap; @@ -70,12 +169,22 @@ static irqreturn_t flit_isr(int irq, void *context) u16 flit =3D pdev->flit_cap; u16 cntr_ctrl, cntr_sta; u32 err_log1, err_log2; + bool print; =20 /* Read and log Counter and Error Log Registers. */ pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_CTRL, &cntr_ctrl); pci_read_config_word(pdev, flit + PCI_FLIT_ERR_CNTR_STA, &cntr_sta); =20 - pci_info(pdev, HW_ERR "Counter Control: 0x%04x Counter Status: 0x%04x\n",= cntr_ctrl, cntr_sta); + /* + * Take a single ratelimit decision per interrupt and use it to gate + * the console output. The trace event is always emitted so RAS + * tooling records every erroneous flit even while the log is throttled. + */ + print =3D __ratelimit(&pdev->flit_ratelimit); + + if (print) + pci_info(pdev, HW_ERR "Counter Control: 0x%04x Counter Status: 0x%04x\n", + cntr_ctrl, cntr_sta); =20 do { pci_read_config_dword(pdev, flit + PCI_FLIT_ERR_LOG1, &err_log1); @@ -84,7 +193,9 @@ static irqreturn_t flit_isr(int irq, void *context) break; =20 pci_read_config_dword(pdev, flit + PCI_FLIT_ERR_LOG2, &err_log2); - pci_info(pdev, HW_ERR " Error Log1: 0x%08x Error Log2: 0x%08x\n", err_l= og1, err_log2); + if (print) + pci_info(pdev, HW_ERR " Error Log1: 0x%08x Error Log2: 0x%08x\n", + err_log1, err_log2); trace_flit_event(pci_name(pdev), cntr_ctrl, cntr_sta, err_log1, err_log2= ); =20 pci_write_config_dword(pdev, flit + PCI_FLIT_ERR_LOG1, err_log1); diff --git a/include/linux/pci.h b/include/linux/pci.h index 4e4d1d9eb7fe..01df7c84a658 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -40,6 +40,7 @@ #include #include #include +#include #include =20 #include @@ -595,6 +596,7 @@ struct pci_dev { =20 #ifdef CONFIG_PCIE_FLIT u16 flit_cap; /* Flit Logging Capabilities */ + struct ratelimit_state flit_ratelimit; /* Flit error log ratelimit */ #endif }; =20 --=20 2.53.0