From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3864E448D01; Tue, 14 Jul 2026 17:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050415; cv=none; b=H0BTlHIgcrAVIEAVet4NXlJkqxSCjv0KK2EP160IC6f8wm8CdDo8x1LNZD5P6hAPcHIcXJRFSavTNqimFPzN+E5RUfbSILRMIsWl6R0o/yIyKLqfieGnJQfaPp7uncq7eOp0tMPGTBMYBBiMGUiBCq8QsU4Dd9RDfg0vdAQ+WQ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050415; c=relaxed/simple; bh=fpnyT2P6jLx3GA1z2t3fW28sbeVdXN+YjwrNxL3NFo4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZegRmj1WLt5Hxk0tlHAZEPrlXrM2x/bRMb04l/0uCEsf+BMm5u7trH6lcfngD5PryifPygMswIuxd3m1syWLEiTOo3xraGUXsnpNzl7lndAW1n880nf7wZ/gEmJAPdqq1UcnQqlqVEhealeIWzi2rb9fJkQQKfc+RvLBf05hRG4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 618041F00A3A; Tue, 14 Jul 2026 17:33:30 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 1/8] clk: r9a08g045-cpg: Add clocks and resets for CAN-FD Date: Tue, 14 Jul 2026 20:33:08 +0300 Message-ID: <20260714173315.1981708-2-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Renesas RZ/G3S SoC has a CAN-FD IP. Add clocks and resets for it. Reviewed-by: Biju Das Reviewed-by: Geert Uytterhoeven Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - used R9A08G045_CLK_P4 ID for P4 clock - still collected the tags; Biju, Geert, please let me know if you consider otherwise drivers/clk/renesas/r9a08g045-cpg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 624fc5e6fb24..ea2a6a71aebd 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -77,6 +77,7 @@ enum clk_ids { CLK_SEL_PLL4, CLK_P1_DIV2, CLK_P3_DIV2, + CLK_P4_DIV2, CLK_SD0_DIV4, CLK_SD1_DIV4, CLK_SD2_DIV4, @@ -172,6 +173,8 @@ static const struct cpg_core_clk r9a08g045_core_clks[] = __initconst =3D { DEF_G3S_DIV("P3", R9A08G045_CLK_P3, CLK_PLL3_DIV2_4, DIVPL3C, G3S_DIVPL3C= _STS, dtable_1_32, 0, 0, 0, NULL), DEF_FIXED("P3_DIV2", CLK_P3_DIV2, R9A08G045_CLK_P3, 1, 2), + DEF_FIXED("P4", R9A08G045_CLK_P4, CLK_PLL2_DIV2, 1, 5), + DEF_FIXED("P4_DIV2", CLK_P4_DIV2, R9A08G045_CLK_P4, 1, 2), DEF_FIXED("P5", R9A08G045_CLK_P5, CLK_PLL2_DIV2, 1, 4), DEF_FIXED("ZT", R9A08G045_CLK_ZT, CLK_PLL3_DIV2_8, 1, 1), DEF_FIXED("S0", R9A08G045_CLK_S0, CLK_SEL_PLL4, 1, 2), @@ -274,6 +277,10 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[]= =3D { MSTOP(BUS_MCPU2, BIT(5))), DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584= , 5, MSTOP(BUS_MCPU3, BIT(4))), + DEF_MOD("canfd_pclk", R9A08G045_CANFD_PCLK, CLK_P4_DIV2, 0x594, 0, + MSTOP(BUS_MCPU2, BIT(9))), + DEF_MOD("canfd_clk_ram", R9A08G045_CANFD_CLK_RAM, R9A08G045_CLK_P4, 0x594= , 1, + MSTOP(BUS_MCPU2, BIT(9))), DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, MSTOP(BUS_PERI_CPU, BIT(6))), DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0, @@ -324,6 +331,8 @@ static const struct rzg2l_reset r9a08g045_resets[] =3D { DEF_RST(R9A08G045_SCIF3_RST_SYSTEM_N, 0x884, 3), DEF_RST(R9A08G045_SCIF4_RST_SYSTEM_N, 0x884, 4), DEF_RST(R9A08G045_SCIF5_RST_SYSTEM_N, 0x884, 5), + DEF_RST(R9A08G045_CANFD_RSTP_N, 0x894, 0), + DEF_RST(R9A08G045_CANFD_RSTC_N, 0x894, 1), DEF_RST(R9A08G045_GPIO_RSTN, 0x898, 0), DEF_RST(R9A08G045_GPIO_PORT_RESETN, 0x898, 1), DEF_RST(R9A08G045_GPIO_SPARE_RESETN, 0x898, 2), --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF6D83644AF; Tue, 14 Jul 2026 17:33:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050420; cv=none; b=m81SzcLXG7ErClT+blbY0LuFTRi1YkcvHPWxJ7bsI1G3itIqKwJyVytrJ4isC0smk6ekGCywHiGO7S0f00c/KS87MJV89p+jqvVqL1KzhnLuRseQIwtPjY8OJn8FRk97M8K58rFLHiP6XbnkiZmmeyRdKsmHgyiYGOX4njooEDw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050420; c=relaxed/simple; bh=dififgWOK3PWSQubZAj5C5b8QiytMc/6UcgNO63ndD0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uoHrsZmgMvnOQU2vUFNscdEnuUmoNmU+/pyx9Nudyo4xanoaHHcT+5/pn/CPV5jITPUarY80rEw5QcstyArLs9Cg1+o3r4RoVscYEVDkydlR5Bkxc+e7HEc3Cl/yOqW0kfqTOZOFxEymWlpeASRqOH36ohPIAyL2cVId41i4Nlo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8ED0C1F000E9; Tue, 14 Jul 2026 17:33:34 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 2/8] dt-bindings: can: renesas,rcar-canfd: Document RZ/G3S SoC Date: Tue, 14 Jul 2026 20:33:09 +0300 Message-ID: <20260714173315.1981708-3-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The CAN FD controller found on the Renesas RZ/G3S SoC is largely compatible with the variant present on the RZ/G3E SoC. The main differences are: - the RZ/G3S provides only two CAN FD channels - the RZ/G3S supports only CAN FD operation; the Channel n CAN FD Configuration Register does not implement the bits used to select classical CAN-only mode (bit 30) or CAN FD-only mode (bit 28); consequently, bit 31 (CAN FD Frame Distinction Enable) of the same register is also not implemented - some bits in several registers (mainly reserved or status bits) are read-write on the RZ/G3S but read-only on the RZ/G3E; their behavior is otherwise identical: the bits read back as 0 on both SoCs and software is allowed to write only 0 to them on the RZ/G3S - the RZ/G3S provides 256 acceptance filters, compared to 768 on the RZ/G3E - the RZ/G3S can use PCLK clock as the CAN FD clock source through an internal clock divider, while also supporting an external CAN FD clock source Since: - the SoC clock generator provides to the CAN IP only the peripheral and the RAM clocks - when sourced from the peripheral clock, the CAN-FD clock is obtained inside the IP itself by dividing the peripheral clock - the assigned-clocks and assigned-clock-rates properties are specific to the CAN-FD clock the assigned-clocks and assigned-clock-rates properties were dropped from the required properties list of the Renesas RZ/G3S SoC. Add documentation for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring (Arm) --- Changes in v3: - updated the patch description to reflect RZ/G3S has 256 acceptance filters and RZ/G3E has 768 acceptance filters - kept compatibles alphanumerically sorted Changes in v2: - forbid renesas,no-can-fd and renesas,fd-only since the IP supports only CAN-FD; for this didn't collect Biju's tag .../bindings/net/can/renesas,rcar-canfd.yaml | 20 +++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.y= aml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml index b9d9dd7a7967..bbaaef8f4282 100644 --- a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - renesas,r9a08g045-canfd # RZ/G3S - renesas,r9a09g047-canfd # RZ/G3E - renesas,r9a09g077-canfd # RZ/T2H =20 @@ -185,8 +186,6 @@ required: - clocks - clock-names - power-domains - - assigned-clocks - - assigned-clock-rates - channel0 - channel1 =20 @@ -198,6 +197,7 @@ allOf: compatible: contains: enum: + - renesas,r9a08g045-canfd - renesas,rzg2l-canfd then: properties: @@ -266,6 +266,7 @@ allOf: compatible: contains: enum: + - renesas,r9a08g045-canfd - renesas,r9a09g077-canfd - renesas,rcar-gen3-canfd - renesas,rzg2l-canfd @@ -330,6 +331,7 @@ allOf: compatible: contains: enum: + - renesas,r9a08g045-canfd - renesas,r9a09g047-canfd - renesas,rzg2l-canfd then: @@ -350,6 +352,20 @@ allOf: properties: reset-names: false =20 + - if: + properties: + compatible: + contains: + const: renesas,r9a08g045-canfd + then: + properties: + renesas,no-can-fd: false + renesas,fd-only: false + else: + required: + - assigned-clocks + - assigned-clock-rates + unevaluatedProperties: false =20 examples: --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 001B04156CC; Tue, 14 Jul 2026 17:33:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050424; cv=none; b=cldy0w2+FBZ+4d1LZH82gPAaeMw5bHWR6QuKNqGeTKGwHs32uvgF+oDNO8i67lzd4UMkZDrurz0npk3iJpKVSsD1S0BnsQGJejGLubXImcrXoQvh9AZCoYLmLphRtO7018nMvRGy85/aiQ1UvHPJvi2yG48s+pS/pgz2Bk/WsWI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050424; c=relaxed/simple; bh=jxkwVsHs3W4Putzopxt0rSxixe4whDDMZvaz6fq5ED0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dNIzj0kd9uTh8CS8NzKhJJi1rOWRKE2TQIQt7KF43ptK44KDs+AoXNHRVPpP+xQ8a2DSuHWKpM1C1vi6lt+qur7GPfb5j+VjxzapMwrN22izqmiaODjXHbA6eryZC+vdm/LlGcDUzgkuOtdcJRSUxEcTwvvvztRxWS5fHxyJPCM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id E78E51F00A3A; Tue, 14 Jul 2026 17:33:38 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 3/8] can: rcar_canfd: Fix typos in macro names Date: Tue, 14 Jul 2026 20:33:10 +0300 Message-ID: <20260714173315.1981708-4-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The bits 1..0 of the Channel n Control Register are named CHMDC (Channel Mode select). Fix typos in macro names by replacing DMC with MDC. Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected tags drivers/net/can/rcar/rcar_canfd.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_= canfd.c index 4ee108abffb8..879f31c97276 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -132,9 +132,9 @@ #define RCANFD_CCTR_BEIE BIT(8) #define RCANFD_CCTR_CSLPR BIT(2) #define RCANFD_CCTR_CHMDC_MASK (0x3) -#define RCANFD_CCTR_CHDMC_COPM (0x0) -#define RCANFD_CCTR_CHDMC_CRESET (0x1) -#define RCANFD_CCTR_CHDMC_CHLT (0x2) +#define RCANFD_CCTR_CHMDC_COPM (0x0) +#define RCANFD_CCTR_CHMDC_CRESET (0x1) +#define RCANFD_CCTR_CHMDC_CHLT (0x2) =20 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */ #define RCANFD_CSTS_COMSTS BIT(7) @@ -828,7 +828,7 @@ static int rcar_canfd_reset_controller(struct rcar_canf= d_global *gpriv) =20 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch), RCANFD_CCTR_CHMDC_MASK, - RCANFD_CCTR_CHDMC_CRESET); + RCANFD_CCTR_CHMDC_CRESET); =20 /* Ensure Channel reset mode */ err =3D readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts, @@ -1504,7 +1504,7 @@ static int rcar_canfd_start(struct net_device *ndev) =20 /* Set channel to Operational mode */ rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch), - RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM); + RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHMDC_COPM); =20 /* Verify channel mode change */ err =3D readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts, @@ -1578,7 +1578,7 @@ static void rcar_canfd_stop(struct net_device *ndev) =20 /* Transition to channel reset mode */ rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch), - RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET); + RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHMDC_CRESET); =20 /* Check Channel reset mode */ err =3D readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts, --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 073E34156DC; Tue, 14 Jul 2026 17:33:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050428; cv=none; b=ILmPTlbL5ls65Bhcr+ul9n0YBsc1nt+dodpgmXXFGxSXax9SXrmvez4spmDSSf3jXH5pYDcItOkDyFbs04SDiU3OemAXXwb+F7Hn2pnBRklub3GSXTIbt2EvS19upcH9a25iG8n8/q9vOvP2f6xCOt9yGkLNr4y7OBYO+eO1Pw0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050428; c=relaxed/simple; bh=73zxd/RVy+/H17HZAYFHekphuc4IOP7GnpgmHBbB0c8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=pRddoiLqdE1GNk46zVdODjMTbjVkJL+SmsdSOCQeBxg9ksqH3yD30LCS7pAWNtSKDMMGftMCSaMyps9qvu419hHCql0DYCmLHotdMRWzQQ37WYCX0fTp+PINgMkZgFfNP2uFgmINIb7m85vWKVc4Xg0Z1TSaBvGmNZUNJESPMsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1D27C1F000E9; Tue, 14 Jul 2026 17:33:42 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 4/8] can: rcar_canfd: Allow the CAN FD clock to be sourced from fck Date: Tue, 14 Jul 2026 20:33:11 +0300 Message-ID: <20260714173315.1981708-5-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea On the Renesas RZ/G3S, the CAN FD clock can be sourced either from fck (the peripheral clock) or from an external clock (can_clk). When fck is used, it is divided internally by the CAN FD controller. Adjust the existing canfd clock handling code to support the RZ/G3S CAN. The existing struct rcar_canfd_hw_info instances were updated to address the request in the Link discussion. Link: https://lore.kernel.org/all/1d9719e3-10ff-4cd8-b729-55fea93c37ce@wana= doo.fr Signed-off-by: Claudiu Beznea --- Changes in v3: - set gpriv->can_clk =3D NULL if info->fcan_pclk Changes in v2: - changed the logic to request canfd only if info->fcan_pclk and contrary get the fcan clock from pclk; for this didn't collect the Rb tag drivers/net/can/rcar/rcar_canfd.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_= canfd.c index 879f31c97276..7fa9cbbf8dde 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -444,6 +444,7 @@ struct rcar_canfd_hw_info { unsigned ch_interface_mode:1; /* Has channel interface mode */ unsigned shared_can_regs:1; /* Has shared classical can registers */ unsigned external_clk:1; /* Has external clock */ + unsigned fcan_pclk:1; /* Has fcan sourced from pclk. */ }; =20 /* Channel priv data */ @@ -617,6 +618,7 @@ static const struct rcar_canfd_hw_info rcar_gen3_hw_inf= o =3D { .ch_interface_mode =3D 0, .shared_can_regs =3D 0, .external_clk =3D 1, + .fcan_pclk =3D 0, }; =20 static const struct rcar_canfd_hw_info rcar_gen4_hw_info =3D { @@ -634,6 +636,7 @@ static const struct rcar_canfd_hw_info rcar_gen4_hw_inf= o =3D { .ch_interface_mode =3D 1, .shared_can_regs =3D 1, .external_clk =3D 1, + .fcan_pclk =3D 0, }; =20 static const struct rcar_canfd_hw_info rzg2l_hw_info =3D { @@ -651,6 +654,7 @@ static const struct rcar_canfd_hw_info rzg2l_hw_info = =3D { .ch_interface_mode =3D 0, .shared_can_regs =3D 0, .external_clk =3D 1, + .fcan_pclk =3D 0, }; =20 static const struct rcar_canfd_hw_info r9a09g047_hw_info =3D { @@ -668,6 +672,7 @@ static const struct rcar_canfd_hw_info r9a09g047_hw_inf= o =3D { .ch_interface_mode =3D 1, .shared_can_regs =3D 1, .external_clk =3D 0, + .fcan_pclk =3D 0, }; =20 static const struct rcar_canfd_hw_info r9a09g077_hw_info =3D { @@ -685,6 +690,7 @@ static const struct rcar_canfd_hw_info r9a09g077_hw_inf= o =3D { .ch_interface_mode =3D 1, .shared_can_regs =3D 1, .external_clk =3D 1, + .fcan_pclk =3D 0, }; =20 /* Helper functions */ @@ -2191,13 +2197,20 @@ static int rcar_canfd_probe(struct platform_device = *pdev) */ gpriv->can_clk =3D devm_clk_get(dev, "can_clk"); if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) =3D=3D 0)) { - gpriv->can_clk =3D devm_clk_get(dev, "canfd"); - if (IS_ERR(gpriv->can_clk)) - return dev_err_probe(dev, PTR_ERR(gpriv->can_clk), - "cannot get canfd clock\n"); + if (info->fcan_pclk) { + fcan_freq =3D clk_get_rate(gpriv->clkp); + gpriv->can_clk =3D NULL; + } else { + gpriv->can_clk =3D devm_clk_get(dev, "canfd"); + if (IS_ERR(gpriv->can_clk)) + return dev_err_probe(dev, PTR_ERR(gpriv->can_clk), + "cannot get canfd clock\n"); + + fcan_freq =3D clk_get_rate(gpriv->can_clk); + } =20 /* CANFD clock may be further divided within the IP */ - fcan_freq =3D clk_get_rate(gpriv->can_clk) / info->postdiv; + fcan_freq /=3D info->postdiv; } else { fcan_freq =3D clk_get_rate(gpriv->can_clk); gpriv->extclk =3D gpriv->info->external_clk; --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8EE2230214B; Tue, 14 Jul 2026 17:33:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050432; cv=none; b=Fw5Skaj6CA/dM3p9VykygiJeOOWxYL5SUF4fflcZFJC1702vSGBfuCpFiwUjRy7Axwu/mbX5qMuj9V/dsnMuv6ISd8RS6EdtIkPtC3tidxEk2X8TkdSQw8VXSMoKsw3JnJr/fY6RRdfRXaRS8vUbLosfY/wUyU0rKXvUzRa7OhI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050432; c=relaxed/simple; bh=cyreKOa5S4fRT0pSZLRECO69cQw7bxhM+Z2w0N+B8jE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KxBIgJ6SzU8zT368apbSB7m2MO7OulOmDXXddFAGSgZR+PYb1/DSSYevtskjAe8kSwuu03EgLL2vVezp+oYeCVJYI8/2mlIQC2WRMJVD3CR1SJLMJbec49VQf3r/QKhqr6viTwtBRP5SJCIZQoCbQB9MNBWnOToMEAJh7eBFpmc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5416E1F00A3A; Tue, 14 Jul 2026 17:33:47 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 5/8] can: rcar_canfd: Do not set registers selecting the CAN mode Date: Tue, 14 Jul 2026 20:33:12 +0300 Message-ID: <20260714173315.1981708-6-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The bits 30 (classical CAN-only mode) and 28 (FD-only enable) of the Channel n CAN-FD Configuration Register of the Renesas RZ/G3S SoC are not available. The IP supports only CAN-FD mode. RZ/G3S HW manual (revision 1.30) specify the bits are read as zero and the write value should always be zero. Add the mode_select_na flag in struct rcar_canfd_hw_info to cover RZ/G3S and avoid writing to unavailable bits. The existing struct rcar_canfd_hw_info instances were updated to address the request in the Link discussion. Commit prepares for the addition of the Renesas RZ/G3S SoC. Link: https://lore.kernel.org/all/1d9719e3-10ff-4cd8-b729-55fea93c37ce@wana= doo.fr Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected the tags - updated patch description to reflect this is a preparatory commit drivers/net/can/rcar/rcar_canfd.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_= canfd.c index 7fa9cbbf8dde..8ba8905c965a 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -445,6 +445,7 @@ struct rcar_canfd_hw_info { unsigned shared_can_regs:1; /* Has shared classical can registers */ unsigned external_clk:1; /* Has external clock */ unsigned fcan_pclk:1; /* Has fcan sourced from pclk. */ + unsigned mode_select_na:1; /* Has no bits for selecting the mode. */ }; =20 /* Channel priv data */ @@ -619,6 +620,7 @@ static const struct rcar_canfd_hw_info rcar_gen3_hw_inf= o =3D { .shared_can_regs =3D 0, .external_clk =3D 1, .fcan_pclk =3D 0, + .mode_select_na =3D 0, }; =20 static const struct rcar_canfd_hw_info rcar_gen4_hw_info =3D { @@ -637,6 +639,7 @@ static const struct rcar_canfd_hw_info rcar_gen4_hw_inf= o =3D { .shared_can_regs =3D 1, .external_clk =3D 1, .fcan_pclk =3D 0, + .mode_select_na =3D 0, }; =20 static const struct rcar_canfd_hw_info rzg2l_hw_info =3D { @@ -655,6 +658,7 @@ static const struct rcar_canfd_hw_info rzg2l_hw_info = =3D { .shared_can_regs =3D 0, .external_clk =3D 1, .fcan_pclk =3D 0, + .mode_select_na =3D 0, }; =20 static const struct rcar_canfd_hw_info r9a09g047_hw_info =3D { @@ -673,6 +677,7 @@ static const struct rcar_canfd_hw_info r9a09g047_hw_inf= o =3D { .shared_can_regs =3D 1, .external_clk =3D 0, .fcan_pclk =3D 0, + .mode_select_na =3D 0, }; =20 static const struct rcar_canfd_hw_info r9a09g077_hw_info =3D { @@ -691,6 +696,7 @@ static const struct rcar_canfd_hw_info r9a09g077_hw_inf= o =3D { .shared_can_regs =3D 1, .external_clk =3D 1, .fcan_pclk =3D 0, + .mode_select_na =3D 0, }; =20 /* Helper functions */ @@ -846,6 +852,9 @@ static int rcar_canfd_reset_controller(struct rcar_canf= d_global *gpriv) } =20 /* Set the controller into appropriate mode */ + if (gpriv->info->mode_select_na) + continue; + if (gpriv->info->ch_interface_mode) { /* Do not set CLOE and FDOE simultaneously */ if (!gpriv->fdmode) { --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A621F30214B; Tue, 14 Jul 2026 17:33:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050436; cv=none; b=ozZdXWXwoSnkQIQgb7qHYiHQWvAUngJ/fKgh4ajqX38O0n1vgTUjpHtG2UR0pxtpUCdm5DXfy8/TAROmFFriFBpCDNb/SxDTJEHXkwLMrbbJqphU+u87NpE58RIvUkbnQV2o0HRc2ujD9eAljus2QGrvIGmndcYL0QbLILMJXzM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050436; c=relaxed/simple; bh=+TGsxrTN5qKYKi2IrMeJvVe0ZSdFGNfOPw/BA7opNmE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lKkRSCBGGhJGF0/KjKjxGePMy6NPulFvWBOI4KcAkFp45mSsQwk1kytDszLJ6hWyOLXf/BHzJwYgq/hFWPRKZqbpZTdSa49oX8u5c0ojBND+ZZc+bLN3ApgZF+w9J1HWgUL2zNooRXoNipit9c3Hwz94H/afyR9rQb+6h8PWwgQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 901291F000E9; Tue, 14 Jul 2026 17:33:51 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 6/8] can: rcar_canfd: Add support for Renesas RZ/G3S Date: Tue, 14 Jul 2026 20:33:13 +0300 Message-ID: <20260714173315.1981708-7-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add support for Renesas RZ/G3S The Renesas RZ/G3S CAN-FD controller is largely compatible with the variant found on the Renesas RZ/G3E. The main differences are: - the RZ/G3S provides 16 AFL pages - the RZ/G3S supports only two channels - the RZ/G3S supports only CAN-FD operation and does not implement the bits used to select between classical CAN-only and CAN FD-only modes. - the RZ/G3S includes an internal divider that allows the peripheral clock to be used as the CAN FD clock source. Add support for the Renesas RZ/G3S. Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea --- Changes in v3: - updated max_aflpn as it refers to the number of available pages that could be used to access the acceptance filters; updated the patch description for this change Changes in v2: - initialized shared_global_irqs =3D 0 for RZ/G3S, to follow the request from https://lore.kernel.org/all/1d9719e3-10ff-4cd8-b729-55fea93c37ce@wan= adoo.fr - collected tags drivers/net/can/rcar/rcar_canfd.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_= canfd.c index 8ba8905c965a..d858778ff002 100644 --- a/drivers/net/can/rcar/rcar_canfd.c +++ b/drivers/net/can/rcar/rcar_canfd.c @@ -661,6 +661,26 @@ static const struct rcar_canfd_hw_info rzg2l_hw_info = =3D { .mode_select_na =3D 0, }; =20 +static const struct rcar_canfd_hw_info r9a08g045_hw_info =3D { + .nom_bittiming =3D &rcar_canfd_gen4_nom_bittiming_const, + .data_bittiming =3D &rcar_canfd_gen4_data_bittiming_const, + .tdc_const =3D &rcar_canfd_gen4_tdc_const, + .regs =3D &rcar_gen4_regs, + .sh =3D &rcar_gen4_shift_data, + .rnc_field_width =3D 16, + .max_aflpn =3D 15, + .max_cftml =3D 31, + .max_channels =3D 2, + .postdiv =3D 2, + .shared_global_irqs =3D 0, + .multi_channel_irqs =3D 1, + .ch_interface_mode =3D 1, + .shared_can_regs =3D 1, + .external_clk =3D 1, + .fcan_pclk =3D 1, + .mode_select_na =3D 1, +}; + static const struct rcar_canfd_hw_info r9a09g047_hw_info =3D { .nom_bittiming =3D &rcar_canfd_gen4_nom_bittiming_const, .data_bittiming =3D &rcar_canfd_gen4_data_bittiming_const, @@ -2384,6 +2404,7 @@ static DEFINE_SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rc= ar_canfd_suspend, =20 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] =3D { { .compatible =3D "renesas,r8a779a0-canfd", .data =3D &rcar_gen4_hw_info = }, + { .compatible =3D "renesas,r9a08g045-canfd", .data =3D &r9a08g045_hw_info= }, { .compatible =3D "renesas,r9a09g047-canfd", .data =3D &r9a09g047_hw_info= }, { .compatible =3D "renesas,r9a09g077-canfd", .data =3D &r9a09g077_hw_info= }, { .compatible =3D "renesas,rcar-gen3-canfd", .data =3D &rcar_gen3_hw_info= }, --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17D2E412BED; Tue, 14 Jul 2026 17:33:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050441; cv=none; b=e0IKx9ugDW6TebSDA0L3XfKEsNeLlrGcx3km0yNHFwj+d5ajIKZw3HAj5hk1vez+PirwJcdJKtWBa1GtsimaO/5vORXlSpFL5wjPnTEagaJqgwi9e0KGakHVHW2bWzFL+sSWx7ULfcuLfsQRQ2bx1kperMnXMnHe8CPi4l6xR6g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050441; c=relaxed/simple; bh=tUkFIuFgLfdWDV6zFJ62wA8JOettaHfNX/xL5WYvroI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=M5zLHAqHR2mbiLa5QjhzmmMGH3y+rZRZh9Jk1Sp4B80YH+798DABGHMaL3xglf8UksyF/czFq7VchmB57QwllQVWeF1OLQFnKFyu0hGvb8DCt35pYdrjKBxRv2PxjKoaplBBQeHlk08EoExJebBYxA74uetex1kZhjUqt1zrMkI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id F2C981F00A3A; Tue, 14 Jul 2026 17:33:55 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 7/8] arm64: dts: renesas: r9a08g045: Add CAN-FD node Date: Tue, 14 Jul 2026 20:33:14 +0300 Message-ID: <20260714173315.1981708-8-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S SoC includes a CAN-FD controller with two channels. Add the corresponding device tree node. Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected tags arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 39 ++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/d= ts/renesas/r9a08g045.dtsi index 3a69bb246bab..fe46f3d9c7cc 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -29,6 +29,13 @@ audio_clk2: audio2-clk { clock-frequency =3D <0>; }; =20 + can_clk: can-clk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + /* This value must be overridden by boards that provide it. */ + clock-frequency =3D <0>; + }; + cluster0_opp: opp-table-0 { compatible =3D "operating-points-v2"; opp-shared; @@ -498,6 +505,38 @@ ssi3: ssi@100a8c00 { status =3D "disabled"; }; =20 + canfd: can@100c0000 { + compatible =3D "renesas,r9a08g045-canfd"; + reg =3D <0 0x100c0000 0 0x20000>; + interrupts =3D , + , + , + , + , + , + , + ; + interrupt-names =3D "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks =3D <&cpg CPG_MOD R9A08G045_CANFD_PCLK>, + <&cpg CPG_MOD R9A08G045_CANFD_CLK_RAM>, + <&can_clk>; + clock-names =3D "fck", "ram_clk", "can_clk"; + resets =3D <&cpg R9A08G045_CANFD_RSTP_N>, + <&cpg R9A08G045_CANFD_RSTC_N>; + reset-names =3D "rstp_n", "rstc_n"; + power-domains =3D <&cpg>; + status =3D "disabled"; + + channel0 { + status =3D "disabled"; + }; + channel1 { + status =3D "disabled"; + }; + }; + cpg: clock-controller@11010000 { compatible =3D "renesas,r9a08g045-cpg"; reg =3D <0 0x11010000 0 0x10000>; --=20 2.43.0 From nobody Sat Jul 25 18:54:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BFC9412BED; Tue, 14 Jul 2026 17:34:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050445; cv=none; b=ZhJlE8LnTdPOSKZRPEt0K/CCqYwPMOcUaH45RA0kl9gMrMRNAa0RUhroGWHTBZDpePLSGJpSKGpmLbwM5Ce+4lz2PuTEFKSLsSz+UfF8EdjDGKVf/EyLjwCADu3BdhJ+etHvKVqFfCmrmQlOMwrgNY1/WUaihW4guq5TfVoom64= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784050445; c=relaxed/simple; bh=kpsV++C9WrOZZ5JntFDCjSPIbIlEv7orzSyhCEFAjF8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=se7NHaPMxy9OM/kYp8u24SrO7inoWVr4B1V4ZGj5aRpJurGDMjP145iPToPGEWpfps5kocBy4dLp86t0lGFsdY+Ipp19x2vx0JSLKkMHHR+htB1M2723jNOccNZsUu3NZ63eSttPLCpMbIMpDcrEeq6RF085nTK6v4kN+rExV5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2DD461F000E9; Tue, 14 Jul 2026 17:34:00 +0000 (UTC) From: Claudiu Beznea To: mkl@pengutronix.de, mailhol@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, biju.das.jz@bp.renesas.com, fabrizio.castro.jz@renesas.com Cc: claudiu.beznea@tuxon.dev, linux-can@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Claudiu Beznea Subject: [PATCH v3 8/8] arm64: dts: renesas: rzg3s-smarc: Enable CAN-FD Date: Tue, 14 Jul 2026 20:33:15 +0300 Message-ID: <20260714173315.1981708-9-claudiu.beznea+renesas@tuxon.dev> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> References: <20260714173315.1981708-1-claudiu.beznea+renesas@tuxon.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The two CAN FD channels available on the Renesas RZ/G3S SoC are routed through the Renesas SMARC Carrier II board when used with the Renesas RZ/G3S SMARC Module. The CAN transceiver on the Carrier II board has its standby pins connected to GPIOs that are selected through the SW_GPIO_CAN_PMOD switches. By default, these switches route the GPIOs to the PMOD interfaces. Enable the CAN FD controller and its two available channels. Reviewed-by: Biju Das Signed-off-by: Claudiu Beznea --- Changes in v3: - none Changes in v2: - collected tags .../boot/dts/renesas/rzg3s-smarc-switches.h | 12 +++++ arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 46 +++++++++++++++++++ 2 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h b/arch/arm6= 4/boot/dts/renesas/rzg3s-smarc-switches.h index bbf908a5322c..198874ad9a65 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-switches.h @@ -37,4 +37,16 @@ */ #define SW_OPT_MUX4 SW_ON =20 +/* + * SW_GPIO_CAN_PMOD[x] switches' states: + * @SW_GPIO_CAN_PMOD1: + * SW_OFF - GPIO8 connected to CAN0_STB (position 1-2) + * SW_ON - GPIO8 connected to PMOD1 (position 2-3) + * @SW_GPIO_CAN_PMOD2: + * SW_OFF - GPIO9 connected to CAN1_STB (position 4-5) + * SW_ON - GPIO9 connected to PMOD1 (position 5-6) + */ +#define SW_GPIO_CAN_PMOD1 SW_ON +#define SW_GPIO_CAN_PMOD2 SW_ON + #endif /* __RZG3S_SMARC_SWITCHES_H__ */ diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg3s-smarc.dtsi index 70af605168b0..2be684f55914 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -68,6 +68,24 @@ codec_dai: simple-audio-card,codec { }; }; =20 + can_transceiver0: can-phy0 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <8000000>; +#if SW_GPIO_CAN_PMOD1 =3D=3D SW_OFF + standby-gpios =3D <&pinctrl RZG2L_GPIO(13, 0) GPIO_ACTIVE_HIGH>; +#endif + }; + + can_transceiver1: can-phy1 { + compatible =3D "ti,tcan1042"; + #phy-cells =3D <0>; + max-bitrate =3D <8000000>; +#if SW_GPIO_CAN_PMOD2 =3D=3D SW_OFF + standby-gpios =3D <&pinctrl RZG2L_GPIO(13, 1) GPIO_ACTIVE_HIGH>; +#endif + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible =3D "regulator-fixed"; regulator-name =3D "SDHI1 Vcc"; @@ -92,6 +110,22 @@ &audio_clk2 { clock-frequency =3D <12288000>; }; =20 +&canfd { + pinctrl-0 =3D <&canfd_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + + channel0 { + phys =3D <&can_transceiver0>; + status =3D "okay"; + }; + + channel1 { + phys =3D <&can_transceiver1>; + status =3D "okay"; + }; +}; + &ehci0 { dr_mode =3D "otg"; status =3D "okay"; @@ -171,6 +205,18 @@ audio_clock_pins: audio-clock { input-enable; }; =20 + canfd_pins: canfd { + can0_pins: can0 { + pinmux =3D , /* CAN0_TX */ + ; /* CAN0_RX */ + }; + + can1_pins: can1 { + pinmux =3D , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + key-1-gpio-hog { gpio-hog; gpios =3D ; --=20 2.43.0