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[95.248.227.210]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-493fd3ccfd4sm180531655e9.2.2026.07.14.04.58.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 04:58:57 -0700 (PDT) From: Christian Marangi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Krzysztof Kozlowski Subject: [PATCH v4 1/4] dt-bindings: clock: airoha: Add additional reset for PCIe PERSTOUT Date: Tue, 14 Jul 2026 13:58:43 +0200 Message-ID: <20260714115848.8537-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260714115848.8537-1-ansuelsmth@gmail.com> References: <20260714115848.8537-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add additional reset to control PCIe PERSTOUT reset line for each of the 3 PCIe lines. Signed-off-by: Christian Marangi Acked-by: Krzysztof Kozlowski --- include/dt-bindings/reset/airoha,en7581-reset.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/reset/airoha,en7581-reset.h b/include/dt-b= indings/reset/airoha,en7581-reset.h index 6544a1790b83..25e75534daa9 100644 --- a/include/dt-bindings/reset/airoha,en7581-reset.h +++ b/include/dt-bindings/reset/airoha,en7581-reset.h @@ -62,5 +62,9 @@ #define EN7581_CPU_TIMER_RST 50 #define EN7581_PCIE_HB_RST 51 #define EN7581_XPON_MAC_RST 52 +/* RST_PCIC */ +#define EN7581_PCIC_PERSTOUT0_RST 53 +#define EN7581_PCIC_PERSTOUT1_RST 54 +#define EN7581_PCIC_PERSTOUT2_RST 55 =20 #endif /* __DT_BINDINGS_RESET_CONTROLLER_AIROHA_EN7581_H_ */ --=20 2.53.0 From nobody Sat Jul 25 19:28:28 2026 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D761D38D3E3 for ; Tue, 14 Jul 2026 11:59:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784030343; cv=none; b=u/j0m2uDWDZs612O5Qrd+wJlq82cmIX/xsJH/sp/CAtxqVZ2g5MZL1R7R5FWlErHBNazoeI5MC8siAKEP6P4xOOG/U6PNfdFCrQZi2jH58dKdxGGki4AKz74YNQUrUqKI9oNjF7iNwylXuBCdQcQX4EhLyzbaI7liJ5q39AHMDQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784030343; c=relaxed/simple; bh=eCjKiSsxMp3e7aAVuQZl2wQDtfBKEbKNnbzvbF592Vo=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N5nZcEXpSQE9XipGdfucZUQmw+Tnz1n0UMkybt7/O1aAM8ou4NCfTDEinC1d7wobE/KsVO9BaE93odeZcQlpdemL3X0YX0Pxna58rddza1pIGqprG7aGXEtNCxWvZKY1gjrSszIKwBIGwQYV0KLyCydHlFd1lyAAzGEwIkN/rpQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mvjI1uJv; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mvjI1uJv" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-493b1710405so22433085e9.2 for ; Tue, 14 Jul 2026 04:59:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784030340; x=1784635140; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=Oqp269fPqkkP0y4F1qhxEIUZdEYzw+E7N13spqrG24g=; b=mvjI1uJvlDqzyAB6vONyr0hgVo5xPCln18h7LbF26cqg1tRMP5eLg4o+gQcp2vLaR4 1XqLmMidej9aJqE+j2MSh1CCy/k0hcskkLyFYldVVq+YuK8xsk58pbyDUOchcpyU5Uuj KHhHawYEUaW4u7Wz6QsD9muGxAsOtf+ebu/9hzMHpHEgXfyjjxHXcGDKFtVgye0PKz+4 5nfvyCgzMJC9d9DNtwG9uoql/kcYFVm7ZwnjD6V8oEItw3P2yxLhN0dLEFQG0fXRquP5 uaiYsLMGsVqq5Fb6kdt8MsFAN++PDKMmcbcZZnTnuaso5re1y3Jti1tRR96s/hf/1sn1 RFPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784030340; x=1784635140; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=Oqp269fPqkkP0y4F1qhxEIUZdEYzw+E7N13spqrG24g=; b=XDGxQ7AzdYksBelqn8uuVyjYKaLVFgnZxEs+UxVQOHyyuzlPmEHGxA7Gjie0QoCGnB mF4RvTLxH1IuDvX3hMrMukQO4EM5M1jd52UzHsCI2VUybIU1mGY1GO+7/2DlKjF2lPK+ TrkpaGigTk/qRNYmjuNO3vNQCYoyNC/Yg4pF1CilGi5SAm1x1Rfw3nNxBxDkdV5XrhVv /bCaWL9sAnAmRwM7+Uvon3+PNRPGE+zvP2+nbnmpo4J5qgknNo+8oFZOSRGaNt9ZKBDd rq+uQZuTiT+1rJh+UjjW/wXykwIJZM/NMJidrsS9NTljDQq63I5iQuvg55B0gpPKOSUm CcKQ== X-Forwarded-Encrypted: i=1; AHgh+Ro9weH3hVjC/9v9blche4LgPxF3ByPjNuZOgPBhE3YUtmzVu3ScCtjjW45dtKUa+ap8K4rLJifpwosVgD0=@vger.kernel.org X-Gm-Message-State: AOJu0Yw9PfA/2tVHxk5zqD6DXZGNx0apptDJ/icbVTYwyGBk0O+2+ByQ x+QQQYc5aGImJckYaQkwM/zoLbyLMelfg4v2/3lgj7iMPvfqidCnEoSQ X-Gm-Gg: AfdE7cmA4jbTB1b6merIkjsD7mKYwdvlf0f9O3qb1SdWjXDo6ITaKIz2o1uE1AawHhw PkxljLA+yybsxNeC7A9N6iQpbFKH7Vtol0385A+pIhzTmE9fLKFYs9KDWjw/eFkO5bMpAbCuQoE 8kaC9WlGRUXQ7pIA2aoWriYGQAwzJpLEUMYmEHDICjZuamBAFs/FU7rVDGd5HjyOvierANmW+r1 oVrZhQm8CtccTcaBTBT6qMIgLxIUfqppvnc48KRYnXhN/dGsMO4x5a8JPeAmlk0yvj2NJWHSoAu xt8Sfbq4iAE6T0laqTXRk0m/CiHEV4PayIddijiAUyquGglHjUvty4GgPzlxcW4lcSXCkHFf8Uh 6WGQ7xyRYCbEvcnqI7rxProbOwUnhv3tG7jleevMsy/939j7LjJjV2LR2Pn+TyBbMl01prVc3aG 22vtPM4KddIMrF6tobfDb3MoVvDf4S/I8n0hCiGjPV8vvrH5DJ2rfCdzLsB1j+g/u/REcSWuoNk PbgX37b X-Received: by 2002:a05:600c:19d0:b0:492:6efc:7c60 with SMTP id 5b1f17b1804b1-49518308220mr36197365e9.28.1784030339968; Tue, 14 Jul 2026 04:58:59 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-95-248-227-210.retail.telecomitalia.it. [95.248.227.210]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-493fd3ccfd4sm180531655e9.2.2026.07.14.04.58.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 04:58:59 -0700 (PDT) From: Christian Marangi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 2/4] clk: en7523: add support for dedicated PCIe PERSTOUT reset Date: Tue, 14 Jul 2026 13:58:44 +0200 Message-ID: <20260714115848.8537-3-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260714115848.8537-1-ansuelsmth@gmail.com> References: <20260714115848.8537-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for resetting the PCIe lines with the PERSTOUT reset. These special reset are controlled by the PCIC register and are specific to each of the 3 PCIe lines. Notice that reset logic is inverted for these bit where 0 is assert and 1 deassert. This is intenrally handled in the reset function. PCI enable/disable are updated to drop PERSTOUT bits in favor dedicated reset handling. Signed-off-by: Christian Marangi --- drivers/clk/clk-en7523.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c index 1ab0e2eca5d3..c9b21d9bf2f3 100644 --- a/drivers/clk/clk-en7523.c +++ b/drivers/clk/clk-en7523.c @@ -338,6 +338,7 @@ static const struct en_clk_desc en7581_base_clks[] =3D { static const u16 en7581_rst_ofs[] =3D { REG_RST_CTRL2, REG_RST_CTRL1, + REG_NP_SCU_PCIC, }; =20 static const u16 en751221_rst_ofs[] =3D { @@ -450,6 +451,11 @@ static const u16 en7581_rst_map[] =3D { [EN7581_CPU_TIMER_RST] =3D RST_NR_PER_BANK + 28, [EN7581_PCIE_HB_RST] =3D RST_NR_PER_BANK + 29, [EN7581_XPON_MAC_RST] =3D RST_NR_PER_BANK + 31, + + /* RST_PCIC */ + [EN7581_PCIC_PERSTOUT0_RST] =3D 2 * RST_NR_PER_BANK + 29, + [EN7581_PCIC_PERSTOUT1_RST] =3D 2 * RST_NR_PER_BANK + 26, + [EN7581_PCIC_PERSTOUT2_RST] =3D 2 * RST_NR_PER_BANK + 16, }; =20 static const u16 en751221_rst_map[] =3D { @@ -635,9 +641,7 @@ static int en7581_pci_enable(struct clk_hw *hw) void __iomem *np_base =3D cg->base; u32 val, mask; =20 - mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | - REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | - REG_PCI_CONTROL_PERSTOUT; + mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; val =3D readl(np_base + REG_PCI_CONTROL); writel(val | mask, np_base + REG_PCI_CONTROL); =20 @@ -650,9 +654,7 @@ static void en7581_pci_disable(struct clk_hw *hw) void __iomem *np_base =3D cg->base; u32 val, mask; =20 - mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | - REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | - REG_PCI_CONTROL_PERSTOUT; + mask =3D REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; val =3D readl(np_base + REG_PCI_CONTROL); writel(val & ~mask, np_base + REG_PCI_CONTROL); usleep_range(1000, 2000); @@ -754,14 +756,21 @@ static int en7523_reset_update(struct reset_controlle= r_dev *rcdev, unsigned long id, bool assert) { struct en_rst_data *rst_data =3D container_of(rcdev, struct en_rst_data, = rcdev); - void __iomem *addr =3D rst_data->base + rst_data->bank_ofs[id / RST_NR_PE= R_BANK]; + u32 offset =3D rst_data->bank_ofs[id / RST_NR_PER_BANK]; + void __iomem *addr =3D rst_data->base + offset; + bool inverted =3D false; u32 val; =20 + /* For PCIC reset logic is inverted, 0:assert 1:deassert*/ + if (offset =3D=3D REG_NP_SCU_PCIC) + inverted =3D true; + val =3D readl(addr); + val &=3D ~BIT(id % RST_NR_PER_BANK); if (assert) - val |=3D BIT(id % RST_NR_PER_BANK); + val |=3D inverted ? 0 : BIT(id % RST_NR_PER_BANK); else - val &=3D ~BIT(id % RST_NR_PER_BANK); + val |=3D inverted ? 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[95.248.227.210]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-493fd3ccfd4sm180531655e9.2.2026.07.14.04.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 04:59:01 -0700 (PDT) From: Christian Marangi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/4] dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes Date: Tue, 14 Jul 2026 13:58:45 +0200 Message-ID: <20260714115848.8537-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260714115848.8537-1-ansuelsmth@gmail.com> References: <20260714115848.8537-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To permit proper documentation of required property to support PCIe configured for 2-lanes mode, split the Airoha schema part from the mediatek-gen3 schema to a dedicated schema. A PCIe configured for 2-lanes mode require an additional reg for the secondary PCIe to be configured and the airoha,scu phandle to correctly configure the PCIe MUX. Rework the mediatek-gen3 schema to drop any redundant constraint previsouly introduced for Airoha PCIe properties. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/airoha,en7581-pcie.yaml | 244 ++++++++++++++++++ .../bindings/pci/mediatek-pcie-gen3.yaml | 77 +----- 2 files changed, 249 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/airoha,en7581-pci= e.yaml diff --git a/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml = b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml new file mode 100644 index 000000000000..78a181a3b599 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml @@ -0,0 +1,244 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/airoha,en7581-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on Airoha SoCs + +maintainers: + - Christian Marangi + +description: |+ + PCIe Gen3 MAC controller for Airoha SoCs, it supports Gen3 speed + and compatible with Gen2, Gen1 speed. + + This PCIe controller supports up to 256 MSI vectors, the MSI hardware + block diagram is as follows: + + +-----+ + | GIC | + +-----+ + ^ + | + port->irq + | + +-+-+-+-+-+-+-+-+ + |0|1|2|3|4|5|6|7| (PCIe intc) + +-+-+-+-+-+-+-+-+ + ^ ^ ^ + | | ... | + +-------+ +------+ +-----------+ + | | | + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + | | | | | | | | | | | | (MSI vectors) + | | | | | | | | | | | | + + (MSI SET0) (MSI SET1) ... (MSI SET7) + + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, + each set has its own address for MSI message, and supports 32 MSI vectors + to generate interrupt. + +properties: + compatible: + const: airoha,en7581-pcie + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + ranges: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: sys-ck + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + num-lanes: + enum: [1, 2] + + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + + airoha,scu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to airoha SCU syscon + description: + Phandle to SCU syscon to configure PCIe MUX for 2 lines support. + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling INTx PCI interrupt= s. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + num-lanes: + const: 2 + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: pcie-mac + - const: sec-pcie-mac + + resets: + minItems: 4 + + reset-names: + items: + - const: phy-lane0 + - const: phy-lane1 + - const: perstout + - const: sec-perstout + + required: + - airoha,scu + + else: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - const: pcie-mac + + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + items: + - enum: [ phy-lane0, phy-lane1, phy-lane2 ] + - enum: [ phy-lane1, perstout ] + - const: phy-lane2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@1fc00000 { + compatible =3D "airoha,en7581-pcie"; + device_type =3D "pci"; + #address-cells =3D <3>; + #size-cells =3D <2>; + + reg =3D <0x0 0x1fc00000 0x0 0x1670>, + <0x0 0x1fc20000 0x0 0x1670>; + reg-names =3D "pcie-mac", "sec-pcie-mac"; + + clocks =3D <&scuclk 7>; + clock-names =3D "sys-ck"; + + phys =3D <&pciephy>; + phy-names =3D "pcie-phy"; + + ranges =3D <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000= >; + + resets =3D <&scuclk 48>, + <&scuclk 49>, + <&scuclk 53>, + <&scuclk 54>; + reset-names =3D "phy-lane0", "phy-lane1", + "perstout", "sec-perstout"; + + num-lanes =3D <2>; + + mediatek,pbus-csr =3D <&pbus_csr 0x0 0x4>; + + airoha,scu =3D <&scuclk>; + + interrupts =3D ; + bus-range =3D <0x00 0xff>; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells =3D <0>; + #interrupt-cells =3D <1>; + interrupt-controller; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml = b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 4db700fc36ba..510f1f2b1c5a 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -59,7 +59,6 @@ properties: - const: mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8196-pcie - - const: airoha,en7581-pcie =20 reg: maxItems: 1 @@ -83,20 +82,20 @@ properties: =20 resets: minItems: 1 - maxItems: 3 + maxItems: 2 =20 reset-names: minItems: 1 - maxItems: 3 + maxItems: 2 items: - enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ] + enum: [ phy, mac ] =20 clocks: - minItems: 1 + minItems: 4 maxItems: 6 =20 clock-names: - minItems: 1 + minItems: 4 maxItems: 6 =20 assigned-clocks: @@ -115,17 +114,6 @@ properties: power-domains: maxItems: 1 =20 - mediatek,pbus-csr: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to pbus-csr syscon - - description: offset of pbus-csr base address register - - description: offset of pbus-csr base address mask register - description: - Phandle with two arguments to the syscon node used to detect if - a given address is accessible on PCIe controller. - '#interrupt-cells': const: 1 =20 @@ -177,16 +165,6 @@ allOf: - const: peri_26m - const: top_133m =20 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -208,16 +186,6 @@ allOf: - const: peri_26m - const: peri_mem =20 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -246,8 +214,6 @@ allOf: - const: phy - const: mac =20 - mediatek,pbus-csr: false - - if: properties: compatible: @@ -257,7 +223,6 @@ allOf: then: properties: clocks: - minItems: 4 maxItems: 4 =20 clock-names: @@ -267,38 +232,6 @@ allOf: - const: peri_26m - const: top_133m =20 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - - if: - properties: - compatible: - const: airoha,en7581-pcie - then: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: sys-ck - - resets: - minItems: 3 - - reset-names: - items: - - const: phy-lane0 - - const: phy-lane1 - - const: phy-lane2 - unevaluatedProperties: false =20 examples: --=20 2.53.0 From nobody Sat Jul 25 19:28:28 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DA5038F92F for ; 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[95.248.227.210]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-493fd3ccfd4sm180531655e9.2.2026.07.14.04.59.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 04:59:02 -0700 (PDT) From: Christian Marangi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 4/4] PCI: mediatek-gen3: Add 2-lanes mode support for Airoha AN7581 Date: Tue, 14 Jul 2026 13:58:46 +0200 Message-ID: <20260714115848.8537-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260714115848.8537-1-ansuelsmth@gmail.com> References: <20260714115848.8537-1-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Airoha AN7581 SoC supports configuring the first PCIe0 lane to 2-lanes mode (2x link) by bonding it with the second PCIe lane (PCIe1). This is done by configuring the PCIe MUX in the SCU register. To correctly configure PCIe0 in 2x link, define in DT the following additional property: - additional reg, 'sec-pcie-mac' for the secondary PCIe. - PERSTOUT reset for both main and secondary PCIE0, called 'perstout' and 'sec-perstout' - airoha,scu property to correctly configure the SCU register for the PCIe MUX - 'num-lanes' set to '2' to enable PCIe0 in 2x link In such configuration the EQ preset are configured to the same values. To permit correct configuration of the PCIe line, additional logic is added to assert and deassert the PERSTOUT resets. Signed-off-by: Christian Marangi --- drivers/pci/controller/pcie-mediatek-gen3.c | 106 ++++++++++++++++---- 1 file changed, 89 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/cont= roller/pcie-mediatek-gen3.c index b0accd828589..764974045340 100644 --- a/drivers/pci/controller/pcie-mediatek-gen3.c +++ b/drivers/pci/controller/pcie-mediatek-gen3.c @@ -32,6 +32,11 @@ =20 #include "../pci.h" =20 +/* AN7581 SCU register */ +#define SCU_PCIC 0x88 +#define SCU_PCIC_PCIE_CTRL GENMASK(7, 0) + +/* PCIe register */ #define PCIE_BASE_CFG_REG 0x14 #define PCIE_BASE_CFG_SPEED GENMASK(15, 8) =20 @@ -131,6 +136,7 @@ #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) =20 #define MAX_NUM_PHY_RESETS 3 +#define MAX_NUM_PERSTOUT_RESETS 2 =20 #define PCIE_MTK_RESET_TIME_US 10 =20 @@ -203,9 +209,11 @@ struct mtk_msi_set { struct mtk_gen3_pcie { struct device *dev; void __iomem *base; + void __iomem *sec_base; phys_addr_t reg_base; struct reset_control *mac_reset; struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RESETS]; + struct reset_control_bulk_data perstout_resets[MAX_NUM_PERSTOUT_RESETS]; struct phy *phy; struct clk_bulk_data *clks; int num_clks; @@ -928,6 +936,14 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *p= cie) if (ret) return dev_err_probe(dev, ret, "failed to get PHY bulk reset\n"); =20 + pcie->perstout_resets[0].id =3D "perstout"; + pcie->perstout_resets[1].id =3D "sec-perstout"; + + ret =3D devm_reset_control_bulk_get_optional_exclusive(dev, MAX_NUM_PERST= OUT_RESETS, + pcie->perstout_resets); + if (ret) + return dev_err_probe(dev, ret, "failed to get PERSTOUT bulk reset\n"); + pcie->mac_reset =3D devm_reset_control_get_optional_exclusive(dev, "mac"); if (IS_ERR(pcie->mac_reset)) return dev_err_probe(dev, PTR_ERR(pcie->mac_reset), "failed to get MAC r= eset\n"); @@ -949,18 +965,38 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *= pcie) pcie->num_lanes =3D num_lanes; } =20 + /* Map secondary PCIe for 2-lanes mode for EN7581 */ + if (pcie->num_lanes =3D=3D 2 && device_is_compatible(dev, "airoha,en7581-= pcie")) { + regs =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec-pcie-ma= c"); + if (!regs) + return -EINVAL; + pcie->sec_base =3D devm_ioremap_resource(dev, regs); + if (IS_ERR(pcie->sec_base)) + return dev_err_probe(dev, PTR_ERR(pcie->sec_base), "failed to map secon= dary register base\n"); + } + return 0; } =20 static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie) { struct pci_host_bridge *host =3D pci_host_bridge_from_priv(pcie); + unsigned int num_lanes =3D max(1, pcie->num_lanes); + struct regmap *pbus_regmap, *scu; struct device *dev =3D pcie->dev; struct resource_entry *entry; - struct regmap *pbus_regmap; u32 val, args[2], size; resource_size_t addr; - int err; + int i, err; + + if (num_lanes > 2) + return dev_err_probe(dev, -EINVAL, "unsupported num-lanes, maximum 2 lan= es supported\n"); + + if (num_lanes =3D=3D 2) { + scu =3D syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu"); + if (IS_ERR(scu)) + return dev_err_probe(dev, PTR_ERR(scu), "failed to map SCU regmap\n"); + } =20 /* * The controller may have been left out of reset by the bootloader @@ -992,6 +1028,19 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_p= cie *pcie) size =3D lower_32_bits(resource_size(entry->res)); regmap_write(pbus_regmap, args[1], GENMASK(31, __fls(size))); =20 + /* Assert PERSTOUT for all relevant lines */ + err =3D reset_control_bulk_assert(MAX_NUM_PERSTOUT_RESETS, + pcie->perstout_resets); + if (err) { + dev_err(dev, "failed to assert PERSTOUTs\n"); + return err; + } + + /* Configure SCU MUX to disable PCIE1 for 2 lines mode */ + if (num_lanes =3D=3D 2) + regmap_update_bits(scu, SCU_PCIC, SCU_PCIC_PCIE_CTRL, + FIELD_PREP(SCU_PCIC_PCIE_CTRL, BIT(1))); + /* * Unlike the other MediaTek Gen3 controllers, the Airoha EN7581 * requires PHY initialization and power-on before PHY reset deassert. @@ -1024,18 +1073,6 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3_= pcie *pcie) pm_runtime_enable(dev); pm_runtime_get_sync(dev); =20 - val =3D FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | - FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | - FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | - FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); - writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG); - - val =3D PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | - FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | - FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | - FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); - writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG); - err =3D clk_bulk_prepare_enable(pcie->num_clks, pcie->clks); if (err) { dev_err(dev, "failed to prepare clock\n"); @@ -1043,14 +1080,47 @@ static int mtk_pcie_en7581_power_up(struct mtk_gen3= _pcie *pcie) } =20 /* - * Airoha EN7581 performs PCIe reset via clk callbacks since it has a - * hw issue with PCIE_PE_RSTB signal. Add wait for the time needed to - * complete the PCIe reset. + * Old Airoha EN7581 clock driver performed PCIe reset via + * clk callbacks since it has a hw issue with PCIE_PE_RSTB signal. + * This is now handled by dedicated PERSTOUT resets with clk + * driver only enabling the refclk. + * + * Wait is still needed for refclk to stabilize */ msleep(PCIE_T_PVPERL_MS); =20 + /* Configure all the lines to the same EQ config */ + for (i =3D 0; i < num_lanes; i++) { + void __iomem *base =3D pcie->base; + + if (i =3D=3D 1) + base =3D pcie->sec_base; + + val =3D FIELD_PREP(PCIE_VAL_LN0_DOWNSTREAM, 0x47) | + FIELD_PREP(PCIE_VAL_LN1_DOWNSTREAM, 0x47) | + FIELD_PREP(PCIE_VAL_LN0_UPSTREAM, 0x41) | + FIELD_PREP(PCIE_VAL_LN1_UPSTREAM, 0x41); + writel_relaxed(val, base + PCIE_EQ_PRESET_01_REG); + + val =3D PCIE_K_PHYPARAM_QUERY | PCIE_K_QUERY_TIMEOUT | + FIELD_PREP(PCIE_K_PRESET_TO_USE_16G, 0x80) | + FIELD_PREP(PCIE_K_PRESET_TO_USE, 0x2) | + FIELD_PREP(PCIE_K_FINETUNE_MAX, 0xf); + writel_relaxed(val, base + PCIE_PIPE4_PIE8_REG); + } + + /* Deassert PERSTOUT for all relevant lines */ + err =3D reset_control_bulk_deassert(MAX_NUM_PERSTOUT_RESETS, + pcie->perstout_resets); + if (err) { + dev_err(dev, "failed to deassert PERSTOUTs\n"); + goto err_perstout_deassert; + } + return 0; =20 +err_perstout_deassert: + clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks); err_clk_prepare_enable: pm_runtime_put_sync(dev); pm_runtime_disable(dev); @@ -1136,6 +1206,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie = *pcie) =20 phy_power_off(pcie->phy); phy_exit(pcie->phy); + reset_control_bulk_assert(MAX_NUM_PERSTOUT_RESETS, + pcie->perstout_resets); reset_control_bulk_assert(pcie->soc->phy_resets.num_resets, pcie->phy_resets); } --=20 2.53.0