From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01C6E37A83B; Tue, 14 Jul 2026 11:44:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029474; cv=none; b=HiAno2dwP/RCpehDTr3Wz9hWQkxV4WeGCqAqQtcg3S8HjIYrHsJGAccTVSFhPdj+8ZPo7gsSwdNrVWkVkcavMbD1cpj2FKuMAojlKxBKi7r6MC3h1UrXA6xUxzSneF4DzCRDn1Jj/TWB2B7714c10vYKY7FZ2QErYpqQHEjgD2Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029474; c=relaxed/simple; bh=Syavb1TDB0/uFM5ETGFncFvguzPZylk13cGK8Z1yBaw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gR2bb/QOlxb81RJT7gBzVuYIytwbgH5R2sawVEptpx8ro2DLmUuKkVVl4JmN8lGrO7FboXdte2qQu/aZBPaWqttz1OGyWmTYn5O8xMtqjEN+b6brIFFdSf9CIEqYzG2Tyucs7ulNj5uIlv0D2OMMemoJH6qF2+VuexNR2SZOA9s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=l8OQgMMv; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="l8OQgMMv" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029471; bh=Syavb1TDB0/uFM5ETGFncFvguzPZylk13cGK8Z1yBaw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l8OQgMMvekJOD5M0cFCl7g2xbCTK9sXKF1133smdV7nBPQ4wyy4e14WGdrG3zEZMz yEbFrb6GlKbowv2rXJ7gJy4i1M5SFYnndy6WspkoGRewMOO5OGsEf42Z/JhrKcmabQ 4MLxTNGIyU+knh0iehU0ZxwTWRCgOYbrdb+x+osKdhf+DKC2TCsUPCbbYvdhzwHEb8 eJUcs1CMMkberPHZPktjGpQEJ4+WGao72I6q904YiQe6DehbWCDB3D3ZE+Mro62pGI TAnfJOMOi0Zq3b/FeS6nQez8Vu+j7a4ztU18AzFSX9kZe2k+Szox3mhcIRHcFBfcFO 6lJpNga3dlyvg== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3446E17E010F; Tue, 14 Jul 2026 13:44:30 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com, Paul-pl Chen , CK Hu Subject: [PATCH v2 01/46] drm/mediatek: Rename OVL format naming Date: Tue, 14 Jul 2026 13:43:29 +0200 Message-ID: <20260714114414.184512-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul-pl Chen Rename format arrays from mt8173_formats[] to mt8173_ovl_formats[] to explicitly indicate that these format definitions are specific to OVL (Overlay) components. This naming improvement is necessary because MT8196 introduces new display components (EXDMA, BLENDER, OUTPROC) that support different format capabilities than OVL. Without clear naming, it becomes ambiguous which formats apply to which component type. Examples of format differences between components: - EXDMA supports 10-bit RGB formats that some OVL variants don't - BLENDER has different YUV handling requirements - Component-specific format conversion capabilities vary The explicit naming: - Prevents confusion when debugging format-related issues - Makes it immediately clear which component a format array belongs to - Improves code searchability (grep for "ovl_formats") - Follows consistent naming convention for component-specific definitions - Prepares for adding exdma_formats[], blender_formats[] arrays This is a preparatory patch for MT8196 component support, which requires clear distinction between OVL formats and EXDMA/BLENDER formats to avoid applying incorrect format configurations. Signed-off-by: Paul-pl Chen Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 36 ++++++++++++------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 97a899e4bd99..135bf5fedc8a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -101,7 +101,7 @@ static inline bool is_10bit_rgb(u32 fmt) return false; } =20 -static const u32 mt8173_formats[] =3D { +static const u32 mt8173_ovl_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_BGRX8888, @@ -115,7 +115,7 @@ static const u32 mt8173_formats[] =3D { DRM_FORMAT_YUYV, }; =20 -static const u32 mt8195_formats[] =3D { +static const u32 mt8195_ovl_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB2101010, @@ -667,8 +667,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver= _data =3D { .gmc_bits =3D 8, .layer_nr =3D 4, .fmt_rgb565_is_0 =3D false, - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8167_ovl_driver_data =3D { @@ -677,8 +677,8 @@ static const struct mtk_disp_ovl_data mt8167_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8173_ovl_driver_data =3D { @@ -686,8 +686,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver= _data =3D { .gmc_bits =3D 8, .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data =3D { @@ -695,8 +695,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver= _data =3D { .gmc_bits =3D 10, .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data =3D { @@ -704,8 +704,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dri= ver_data =3D { .gmc_bits =3D 10, .layer_nr =3D 2, .fmt_rgb565_is_0 =3D true, - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data =3D { @@ -717,8 +717,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data =3D { @@ -730,8 +730,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), - .formats =3D mt8173_formats, - .num_formats =3D ARRAY_SIZE(mt8173_formats), + .formats =3D mt8173_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), }; =20 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data =3D { @@ -744,8 +744,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), - .formats =3D mt8195_formats, - .num_formats =3D ARRAY_SIZE(mt8195_formats), + .formats =3D mt8195_ovl_formats, + .num_formats =3D ARRAY_SIZE(mt8195_ovl_formats), .supports_clrfmt_ext =3D true, }; =20 --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4647B381EAD; Tue, 14 Jul 2026 11:44:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029476; cv=none; b=HADmg82HHL5qm0R6qRzdQSmxzRWbxHsZ0o19+WcOqVj5ZwYtLBIB7m4+sb0wPPl+k4QgdvFoTwLhLuw/Kb85Q8O+lAoFCAomWxOho1nXTkSAyiw5S5P0sps6zwQ7iCwO3u6Mkj6cAhMkmPRKZn733daif08RladzSvMOyVDHbAs= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029472; bh=8OiVQ/Y/antXKCgdZsU2F6JKC0zWfdBF7J9KDfdME+0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SeuvzPuOf7w8Iw6e9bmh7qWeVOnQ1rV0bkYRuP8zKxbMpG+A3N85V6dLIxGJ0m6Tg 50lpM/VOLhP2xiJKe/M+jgdxoJKQL7BHzdOJlN/82vBp/cGPE4d1t5fapiWG2pIhp8 NLafxSN1Ja0PXl1lm2Szmqbktr1P1QMwowQVjYkrNbMCTOO6Pp/hXIxzG6qmKAqYuo Mksb7Mcnn7+kGmfK+DK32N2BGQZCDjF3NnAPOQz+YqL4sMcifzNjX6CjKZQV9ct6lp c5CYhDG01JxmNrJq0CQfQJgB5qKE8wNv1XZSKghAHhwynXTzLGvas4UGmGPtUqq3im yY96jpmjtB0iA== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 46A1D17E087B; Tue, 14 Jul 2026 13:44:31 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com, Nancy Lin , Paul-pl Chen Subject: [PATCH v2 02/46] drm/mediatek: Export OVL formats definitions and format conversion API Date: Tue, 14 Jul 2026 13:43:30 +0200 Message-ID: <20260714114414.184512-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Nancy Lin In upcoming SoCs, the OVL component will be divided into multiple smaller hardware units to enhance flexibility. To facilitate this transition, the OVL format definitions and format conversion API should be exported for reuse across these units. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 192 ++++++++++++++---------- drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 19 +++ 2 files changed, 132 insertions(+), 79 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_ovl.h diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 135bf5fedc8a..5cdaca8f68b2 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -4,7 +4,6 @@ */ =20 #include -#include #include =20 #include @@ -18,6 +17,7 @@ #include "mtk_crtc.h" #include "mtk_ddp_comp.h" #include "mtk_disp_drv.h" +#include "mtk_disp_ovl.h" #include "mtk_drm_drv.h" =20 #define DISP_REG_OVL_INTEN 0x0004 @@ -62,22 +62,16 @@ /* OVL_CON_RGB_SWAP works only if OVL_CON_CLRFMT_MAN is enabled */ #define OVL_CON_RGB_SWAP BIT(25) =20 -#define OVL_CON_CLRFMT_RGB (1 << 12) -#define OVL_CON_CLRFMT_ARGB8888 (2 << 12) -#define OVL_CON_CLRFMT_RGBA8888 (3 << 12) -#define OVL_CON_CLRFMT_ABGR8888 (OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SW= AP) -#define OVL_CON_CLRFMT_BGRA8888 (OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SW= AP) -#define OVL_CON_CLRFMT_UYVY (4 << 12) -#define OVL_CON_CLRFMT_YUYV (5 << 12) -#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) -#define OVL_CON_CLRFMT_PARGB8888 ((3 << 12) | OVL_CON_CLRFMT_MAN) -#define OVL_CON_CLRFMT_PABGR8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_RGB_S= WAP) -#define OVL_CON_CLRFMT_PBGRA8888 (OVL_CON_CLRFMT_PARGB8888 | OVL_CON_BYTE_= SWAP) -#define OVL_CON_CLRFMT_PRGBA8888 (OVL_CON_CLRFMT_PABGR8888 | OVL_CON_BYTE_= SWAP) -#define OVL_CON_CLRFMT_RGB565(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ - 0 : OVL_CON_CLRFMT_RGB) -#define OVL_CON_CLRFMT_RGB888(ovl) ((ovl)->data->fmt_rgb565_is_0 ? \ - OVL_CON_CLRFMT_RGB : 0) +#define OVL_CON_CLRFMT_SHIFT (12) +#define OVL_CON_CLRFMT_RGB565(shift) (0 << (shift)) +#define OVL_CON_CLRFMT_RGB888(shift) (1 << (shift)) +#define OVL_CON_CLRFMT_ARGB8888(shift) (2 << (shift)) +#define OVL_CON_CLRFMT_RGBA8888(shift) (3 << (shift)) +#define OVL_CON_CLRFMT_UYVY(shift) (4 << (shift)) +#define OVL_CON_CLRFMT_YUYV(shift) (5 << (shift)) +#define OVL_CON_MTX_YUV_TO_RGB (6 << 16) +#define OVL_CON_CLRFMT_PARGB8888(shift, man) ((3 << (shift)) | (man)) + #define OVL_CON_AEN BIT(8) #define OVL_CON_ALPHA 0xff #define OVL_CON_VIRT_FLIP BIT(9) @@ -85,21 +79,6 @@ =20 #define OVL_COLOR_ALPHA GENMASK(31, 24) =20 -static inline bool is_10bit_rgb(u32 fmt) -{ - switch (fmt) { - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: - case DRM_FORMAT_RGBX1010102: - case DRM_FORMAT_RGBA1010102: - case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: - case DRM_FORMAT_BGRX1010102: - case DRM_FORMAT_BGRA1010102: - return true; - } - return false; -} =20 static const u32 mt8173_ovl_formats[] =3D { DRM_FORMAT_XRGB8888, @@ -115,7 +94,9 @@ static const u32 mt8173_ovl_formats[] =3D { DRM_FORMAT_YUYV, }; =20 -static const u32 mt8195_ovl_formats[] =3D { +static const size_t mt8173_ovl_formats_len =3D ARRAY_SIZE(mt8173_ovl_forma= ts); + +const u32 mt8195_ovl_formats[] =3D { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB2101010, @@ -139,6 +120,8 @@ static const u32 mt8195_ovl_formats[] =3D { DRM_FORMAT_YUYV, }; =20 +const size_t mt8195_ovl_formats_len =3D ARRAY_SIZE(mt8195_ovl_formats); + struct mtk_disp_ovl_data { unsigned int addr; unsigned int gmc_bits; @@ -167,6 +150,22 @@ struct mtk_disp_ovl { void *vblank_cb_data; }; =20 +bool mtk_ovl_is_10bit_rgb(unsigned int fmt) +{ + switch (fmt) { + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + case DRM_FORMAT_RGBX1010102: + case DRM_FORMAT_RGBA1010102: + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + case DRM_FORMAT_BGRX1010102: + case DRM_FORMAT_BGRA1010102: + return true; + } + return false; +} + static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id) { struct mtk_disp_ovl *priv =3D dev_id; @@ -302,7 +301,7 @@ static void mtk_ovl_set_bit_depth(struct device *dev, i= nt idx, u32 format, if (!ovl->data->supports_clrfmt_ext) return; =20 - if (is_10bit_rgb(format)) + if (mtk_ovl_is_10bit_rgb(format)) bit_depth =3D OVL_CON_CLRFMT_10_BIT; =20 mtk_ddp_write_mask(cmdq_pkt, OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx), @@ -401,70 +400,97 @@ void mtk_ovl_layer_off(struct device *dev, unsigned i= nt idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 -static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl, - struct mtk_plane_state *state) +unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode, + bool fmt_rgb565_is_0, bool color_convert, + u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap) { - unsigned int fmt =3D state->pending.format; - unsigned int blend_mode =3D DRM_MODE_BLEND_COVERAGE; - - /* - * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware = data sheet - * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 8888. - * - * Check blend_modes in the driver data to see if premultiplied mode is s= upported. - * If not, use coverage mode instead to set it to the supported color for= mats. - * - * Current DRM assumption is that alpha is default premultiplied, so the = bitmask of - * blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_= plane_init() - * will get an error return from drm_plane_create_blend_mode_property() a= nd - * state->base.pixel_blend_mode should not be used. - */ - if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) - blend_mode =3D state->base.pixel_blend_mode; + unsigned int con =3D 0; + bool need_byte_swap =3D false, need_rgb_swap =3D false; =20 switch (fmt) { default: case DRM_FORMAT_RGB565: - return OVL_CON_CLRFMT_RGB565(ovl); + con =3D fmt_rgb565_is_0 ? + OVL_CON_CLRFMT_RGB565(clrfmt_shift) : OVL_CON_CLRFMT_RGB888(clrfmt_shif= t); + break; case DRM_FORMAT_BGR565: - return OVL_CON_CLRFMT_RGB565(ovl) | OVL_CON_BYTE_SWAP; + con =3D fmt_rgb565_is_0 ? + OVL_CON_CLRFMT_RGB565(clrfmt_shift) : OVL_CON_CLRFMT_RGB888(clrfmt_shif= t); + need_byte_swap =3D true; /* RGB565 -> BGR565 */ + break; case DRM_FORMAT_RGB888: - return OVL_CON_CLRFMT_RGB888(ovl); + con =3D fmt_rgb565_is_0 ? + OVL_CON_CLRFMT_RGB888(clrfmt_shift) : OVL_CON_CLRFMT_RGB565(clrfmt_shif= t); + break; case DRM_FORMAT_BGR888: - return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; + con =3D fmt_rgb565_is_0 ? + OVL_CON_CLRFMT_RGB888(clrfmt_shift) : OVL_CON_CLRFMT_RGB565(clrfmt_shif= t); + need_byte_swap =3D true; /* RGB888 -> BGR888 */ + break; case DRM_FORMAT_RGBX8888: case DRM_FORMAT_RGBA8888: case DRM_FORMAT_RGBX1010102: case DRM_FORMAT_RGBA1010102: - return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? - OVL_CON_CLRFMT_RGBA8888 : - OVL_CON_CLRFMT_PRGBA8888; + if (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE) { + con =3D OVL_CON_CLRFMT_RGBA8888(clrfmt_shift); + } else { + con =3D OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man); + need_byte_swap =3D true; /* PARGB8888 -> PBGRA8888 */ + need_rgb_swap =3D true; /* PBGRA8888 -> PRGBA8888 */ + } + break; case DRM_FORMAT_BGRX8888: case DRM_FORMAT_BGRA8888: case DRM_FORMAT_BGRX1010102: case DRM_FORMAT_BGRA1010102: - return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? - OVL_CON_CLRFMT_BGRA8888 : - OVL_CON_CLRFMT_PBGRA8888; + if (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE) { + con =3D OVL_CON_CLRFMT_RGBA8888(clrfmt_shift); + need_byte_swap =3D true; /* RGBA8888 -> BGRA8888 */ + } else { + con =3D OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man); + need_byte_swap =3D true; /* PARGB8888 -> PBGRA8888 */ + } + break; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? - OVL_CON_CLRFMT_ARGB8888 : - OVL_CON_CLRFMT_PARGB8888; + if (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE) + con =3D OVL_CON_CLRFMT_ARGB8888(clrfmt_shift); + else + con =3D OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man); + break; case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ABGR8888: case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - return blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE ? - OVL_CON_CLRFMT_ABGR8888 : - OVL_CON_CLRFMT_PABGR8888; + if (blend_mode =3D=3D DRM_MODE_BLEND_COVERAGE) { + con =3D OVL_CON_CLRFMT_ARGB8888(clrfmt_shift); + need_rgb_swap =3D true; /* ARGB8888 -> ABGR8888 */ + } else { + con =3D OVL_CON_CLRFMT_PARGB8888(clrfmt_shift, clrfmt_man); + need_rgb_swap =3D true; /* PARGB8888 -> PABGR8888 */ + } + break; case DRM_FORMAT_UYVY: - return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; + con =3D OVL_CON_CLRFMT_UYVY(clrfmt_shift); + if (color_convert) + con |=3D OVL_CON_MTX_YUV_TO_RGB; + break; case DRM_FORMAT_YUYV: - return OVL_CON_CLRFMT_YUYV | OVL_CON_MTX_YUV_TO_RGB; + con =3D OVL_CON_CLRFMT_YUYV(clrfmt_shift); + if (color_convert) + con |=3D OVL_CON_MTX_YUV_TO_RGB; + break; } + + if (need_byte_swap) + con |=3D byte_swap; + + if (need_rgb_swap) + con |=3D rgb_swap; + + return con; } =20 static void mtk_ovl_afbc_layer_config(struct mtk_disp_ovl *ovl, @@ -511,7 +537,15 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, return; } =20 - con =3D mtk_ovl_fmt_convert(ovl, state); + if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + con =3D mtk_ovl_fmt_convert(fmt, blend_mode, + ovl->data->fmt_rgb565_is_0, true, OVL_CON_CLRFMT_SHIFT, + OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP); + else + con =3D mtk_ovl_fmt_convert(fmt, DRM_MODE_BLEND_COVERAGE, + ovl->data->fmt_rgb565_is_0, true, OVL_CON_CLRFMT_SHIFT, + OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP); + if (state->base.fb) { con |=3D state->base.alpha & OVL_CON_ALPHA; =20 @@ -668,7 +702,7 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D false, .formats =3D mt8173_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), + .num_formats =3D mt8173_ovl_formats_len, }; =20 static const struct mtk_disp_ovl_data mt8167_ovl_driver_data =3D { @@ -687,7 +721,7 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), + .num_formats =3D mt8173_ovl_formats_len, }; =20 static const struct mtk_disp_ovl_data mt8183_ovl_driver_data =3D { @@ -696,7 +730,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), + .num_formats =3D mt8173_ovl_formats_len, }; =20 static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data =3D { @@ -705,7 +739,7 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_dri= ver_data =3D { .layer_nr =3D 2, .fmt_rgb565_is_0 =3D true, .formats =3D mt8173_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), + .num_formats =3D mt8173_ovl_formats_len, }; =20 static const struct mtk_disp_ovl_data mt8192_ovl_driver_data =3D { @@ -718,7 +752,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), + .num_formats =3D mt8173_ovl_formats_len, }; =20 static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data =3D { @@ -731,7 +765,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8173_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8173_ovl_formats), + .num_formats =3D mt8173_ovl_formats_len, }; =20 static const struct mtk_disp_ovl_data mt8195_ovl_driver_data =3D { @@ -745,7 +779,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { BIT(DRM_MODE_BLEND_COVERAGE) | BIT(DRM_MODE_BLEND_PIXEL_NONE), .formats =3D mt8195_ovl_formats, - .num_formats =3D ARRAY_SIZE(mt8195_ovl_formats), + .num_formats =3D mt8195_ovl_formats_len, .supports_clrfmt_ext =3D true, }; =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.h new file mode 100644 index 000000000000..919498496bb6 --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 MediaTek Inc. + */ + +#ifndef __MTK_DISP_OVL_H__ +#define __MTK_DISP_OVL_H__ + +#include + +extern const u32 mt8195_ovl_formats[]; +extern const size_t mt8195_ovl_formats_len; + +bool mtk_ovl_is_10bit_rgb(unsigned int fmt); +unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode, + bool fmt_rgb565_is_0, bool color_convert, + u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap); 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Tue, 14 Jul 2026 13:44:32 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com, Paul-pl Chen , Nancy Lin Subject: [PATCH v2 03/46] drm/mediatek: Export OVL Blend function Date: Tue, 14 Jul 2026 13:43:31 +0200 Message-ID: <20260714114414.184512-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Paul-pl Chen For the new BLENDER component, the OVL ignore pixel alpha logic should be exported as a function and reused it. Signed-off-by: Nancy Lin Signed-off-by: Paul-pl Chen Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 79 ++++++++++++++++--------- drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 8 +++ 2 files changed, 59 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 5cdaca8f68b2..8ef174987cb8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -214,6 +214,23 @@ void mtk_ovl_disable_vblank(struct device *dev) writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN); } =20 +bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned= int blend_mode) +{ + if (!state->base.fb) + return false; + + /* + * Although the alpha channel can be ignored, CONST_BLD must be enabled + * for XRGB format, otherwise OVL will still read the value from memory. + * For RGB888 related formats, whether CONST_BLD is enabled or not won't + * affect the result. Therefore we use !has_alpha as the condition. + */ + if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->forma= t->has_alpha) + return true; + + return false; +} + u32 mtk_ovl_get_blend_modes(struct device *dev) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); @@ -400,6 +417,29 @@ void mtk_ovl_layer_off(struct device *dev, unsigned in= t idx, DISP_REG_OVL_RDMA_CTRL(idx)); } =20 +unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigne= d int blend_modes) +{ + unsigned int blend_mode =3D DRM_MODE_BLEND_COVERAGE; + + /* + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware = data sheet + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 888 + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB= 8888. + * + * Check blend_modes in the driver data to see if premultiplied mode is s= upported. + * If not, use coverage mode instead to set it to the supported color for= mats. + * + * Current DRM assumption is that alpha is default premultiplied, so the = bitmask of + * blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_= plane_init() + * will get an error return from drm_plane_create_blend_mode_property() a= nd + * state->base.pixel_blend_mode should not be used. + */ + if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) + blend_mode =3D state->base.pixel_blend_mode; + + return blend_mode; +} + unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode, bool fmt_rgb565_is_0, bool color_convert, u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap) @@ -528,7 +568,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, unsigned int rotation =3D pending->rotation; unsigned int offset =3D (pending->y << 16) | pending->x; unsigned int src_size =3D (pending->height << 16) | pending->width; - unsigned int blend_mode =3D state->base.pixel_blend_mode; + unsigned int blend_mode =3D mtk_ovl_get_blend_mode(state, ovl->data->blen= d_modes); unsigned int ignore_pixel_alpha =3D 0; unsigned int con; =20 @@ -537,14 +577,9 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, return; } =20 - if (ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) - con =3D mtk_ovl_fmt_convert(fmt, blend_mode, - ovl->data->fmt_rgb565_is_0, true, OVL_CON_CLRFMT_SHIFT, - OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP); - else - con =3D mtk_ovl_fmt_convert(fmt, DRM_MODE_BLEND_COVERAGE, - ovl->data->fmt_rgb565_is_0, true, OVL_CON_CLRFMT_SHIFT, - OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP); + con =3D mtk_ovl_fmt_convert(fmt, blend_mode, + ovl->data->fmt_rgb565_is_0, true, OVL_CON_CLRFMT_SHIFT, + OVL_CON_CLRFMT_MAN, OVL_CON_BYTE_SWAP, OVL_CON_RGB_SWAP); =20 if (state->base.fb) { con |=3D state->base.alpha & OVL_CON_ALPHA; @@ -553,17 +588,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned= int idx, * For blend_modes supported SoCs, always enable alpha blending. * For blend_modes unsupported SoCs, enable alpha blending when has_alph= a is set. */ - if (blend_mode || state->base.fb->format->has_alpha) + if (state->base.pixel_blend_mode || state->base.fb->format->has_alpha) con |=3D OVL_CON_AEN; - - /* - * Although the alpha channel can be ignored, CONST_BLD must be enabled - * for XRGB format, otherwise OVL will still read the value from memory. - * For RGB888 related formats, whether CONST_BLD is enabled or not won't - * affect the result. Therefore we use !has_alpha as the condition. - */ - if (blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->form= at->has_alpha) - ignore_pixel_alpha =3D OVL_CONST_BLEND; } =20 /* @@ -589,6 +615,9 @@ void mtk_ovl_layer_config(struct device *dev, unsigned = int idx, =20 mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_CON(idx)); + + if (mtk_ovl_is_ignore_pixel_alpha(state, state->base.pixel_blend_mode)) + ignore_pixel_alpha =3D OVL_CONST_BLEND; mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx)); mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs, @@ -748,9 +777,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver= _data =3D { .layer_nr =3D 4, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, - .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE), + .blend_modes =3D MTK_OVL_SUPPORT_BLEND_MODES, .formats =3D mt8173_ovl_formats, .num_formats =3D mt8173_ovl_formats_len, }; @@ -761,9 +788,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_dri= ver_data =3D { .layer_nr =3D 2, .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, - .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE), + .blend_modes =3D MTK_OVL_SUPPORT_BLEND_MODES, .formats =3D mt8173_ovl_formats, .num_formats =3D mt8173_ovl_formats_len, }; @@ -775,9 +800,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver= _data =3D { .fmt_rgb565_is_0 =3D true, .smi_id_en =3D true, .supports_afbc =3D true, - .blend_modes =3D BIT(DRM_MODE_BLEND_PREMULTI) | - BIT(DRM_MODE_BLEND_COVERAGE) | - BIT(DRM_MODE_BLEND_PIXEL_NONE), + .blend_modes =3D MTK_OVL_SUPPORT_BLEND_MODES, .formats =3D mt8195_ovl_formats, .num_formats =3D mt8195_ovl_formats_len, .supports_clrfmt_ext =3D true, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.h index 919498496bb6..419c2136006c 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h @@ -6,12 +6,20 @@ #ifndef __MTK_DISP_OVL_H__ #define __MTK_DISP_OVL_H__ =20 +#include #include =20 +#define MTK_OVL_SUPPORT_BLEND_MODES \ + (BIT(DRM_MODE_BLEND_PREMULTI) | \ + BIT(DRM_MODE_BLEND_COVERAGE) | \ + BIT(DRM_MODE_BLEND_PIXEL_NONE)) + extern const u32 mt8195_ovl_formats[]; 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charset="utf-8" In preparation for a major refactoring of MMSYS, MUTEX and of mediatek-drm, move the mtk_ddp_comp_type enumeration to the mtk-mmsys.h header, as this will be shared between multiple MediaTek multimedia related drivers. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 25 --------------------- include/linux/soc/mediatek/mtk-mmsys.h | 29 +++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 99bf1e1015da..bbc66072fe6b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -22,31 +22,6 @@ struct mtk_plane_state; struct drm_crtc_state; struct drm_dsc_config; =20 -enum mtk_ddp_comp_type { - MTK_DISP_AAL, - MTK_DISP_BLS, - MTK_DISP_CCORR, - MTK_DISP_COLOR, - MTK_DISP_DITHER, - MTK_DISP_DSC, - MTK_DISP_GAMMA, - MTK_DISP_MERGE, - MTK_DISP_MUTEX, - MTK_DISP_OD, - MTK_DISP_OVL, - MTK_DISP_OVL_2L, - MTK_DISP_OVL_ADAPTOR, - MTK_DISP_POSTMASK, - MTK_DISP_PWM, - MTK_DISP_RDMA, - MTK_DISP_UFOE, - MTK_DISP_WDMA, - MTK_DPI, - MTK_DP_INTF, - MTK_DSI, - MTK_DDP_COMP_TYPE_MAX, -}; - struct mtk_ddp_comp; struct cmdq_pkt; struct mtk_ddp_comp_funcs { diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 4885b065b849..fb88202d100a 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -84,6 +84,35 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_ID_MAX, }; =20 +enum mtk_ddp_comp_type { + /* DISP Components */ + MTK_DISP_AAL, + MTK_DISP_BLS, + MTK_DISP_CCORR, + MTK_DISP_COLOR, + MTK_DISP_DITHER, + MTK_DISP_DSC, + MTK_DISP_GAMMA, + MTK_DISP_MERGE, + MTK_DISP_MUTEX, + MTK_DISP_OD, + MTK_DISP_OVL, + MTK_DISP_OVL_2L, + MTK_DISP_OVL_ADAPTOR, + MTK_DISP_POSTMASK, + MTK_DISP_PWM, + MTK_DISP_RDMA, + MTK_DISP_UFOE, + MTK_DISP_WDMA, + + /* Keep Display outputs at the end for readability */ + MTK_DPI, + MTK_DP_INTF, + MTK_DSI, + + MTK_DDP_COMP_TYPE_MAX +}; + void mtk_mmsys_ddp_connect(struct device *dev, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next); --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3122638D3F9; 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Tue, 14 Jul 2026 13:44:34 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 05/46] drm/mediatek: Add missing component types in mtk_ddp_comp_type Date: Tue, 14 Jul 2026 13:43:33 +0200 Message-ID: <20260714114414.184512-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation to remove the mtk_ddp_comp_id enumeration, add the missing component types ETHDR_MIXER, PADDING and MDP_RDMA in the mtk_ddp_comp_type enumeration. Signed-off-by: AngeloGioacchino Del Regno --- include/linux/soc/mediatek/mtk-mmsys.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index fb88202d100a..3ddfdeac658d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -92,6 +92,7 @@ enum mtk_ddp_comp_type { MTK_DISP_COLOR, MTK_DISP_DITHER, MTK_DISP_DSC, + MTK_DISP_ETHDR_MIXER, MTK_DISP_GAMMA, MTK_DISP_MERGE, MTK_DISP_MUTEX, @@ -99,12 +100,16 @@ enum mtk_ddp_comp_type { MTK_DISP_OVL, MTK_DISP_OVL_2L, MTK_DISP_OVL_ADAPTOR, + MTK_DISP_PADDING, MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, MTK_DISP_UFOE, MTK_DISP_WDMA, =20 + /* MDP Components */ + MTK_DISP_MDP_RDMA, + /* Keep Display outputs at the end for readability */ MTK_DPI, MTK_DP_INTF, --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A982938F62A; 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Tue, 14 Jul 2026 13:44:35 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com, CK Hu Subject: [PATCH v2 06/46] drm/mediatek: Rename all display component type to have DISP_ prefix Date: Tue, 14 Jul 2026 13:43:34 +0200 Message-ID: <20260714114414.184512-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mtk_ddp_comp_type enumeration will end up containing both the Display Controller and Media Data Path Controller components: this is because those can be interconnected together (as in, using MDP components in Display Controller paths is possible!) and because both MMSYS and MuteX are managing both of those in practically the same way. Rename all of the Display Controller related HW components in the list to always have a "DISP_" prefix. This includes components that are in the MDP Controller instead, and the strategy here is for some of those to also have the same DISP_ prefix, so that: - Display Controller specific components have a DISP_ prefix - Example: MTK_DISP_(NAME) - MDP Controller components that can be interconnected to the Display Controller will have both DISP_ and MDP_ prefixes - Example: MTK_DISP_MDP_(NAME) - MDP Controller components that are exclusive to MDP and can not be interconnected with Display Controller will only have an MDP_ prefix but not a DISP_ prefix - Example: MTK_MDP_(NAME). Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 28 +++++++++---------- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 36 ++++++++++++------------- include/linux/soc/mediatek/mtk-mmsys.h | 6 ++--- 3 files changed, 35 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 94b356da6de7..a6c1815ffa39 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -423,9 +423,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_RDMA] =3D "rdma", [MTK_DISP_UFOE] =3D "ufoe", [MTK_DISP_WDMA] =3D "wdma", - [MTK_DP_INTF] =3D "dp-intf", - [MTK_DPI] =3D "dpi", - [MTK_DSI] =3D "dsi", + [MTK_DISP_DP_INTF] =3D "dp-intf", + [MTK_DISP_DPI] =3D "dpi", + [MTK_DISP_DSI] =3D "dsi", }; =20 struct mtk_ddp_comp_match { @@ -442,17 +442,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matche= s[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_COLOR0] =3D { MTK_DISP_COLOR, 0, &ddp_color }, [DDP_COMPONENT_COLOR1] =3D { MTK_DISP_COLOR, 1, &ddp_color }, [DDP_COMPONENT_DITHER0] =3D { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DP_INTF0] =3D { MTK_DP_INTF, 0, &ddp_dpi }, - [DDP_COMPONENT_DP_INTF1] =3D { MTK_DP_INTF, 1, &ddp_dpi }, - [DDP_COMPONENT_DPI0] =3D { MTK_DPI, 0, &ddp_dpi }, - [DDP_COMPONENT_DPI1] =3D { MTK_DPI, 1, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF0] =3D { MTK_DISP_DP_INTF, 0, &ddp_dpi }, + [DDP_COMPONENT_DP_INTF1] =3D { MTK_DISP_DP_INTF, 1, &ddp_dpi }, + [DDP_COMPONENT_DPI0] =3D { MTK_DISP_DPI, 0, &ddp_dpi }, + [DDP_COMPONENT_DPI1] =3D { MTK_DISP_DPI, 1, &ddp_dpi }, [DDP_COMPONENT_DRM_OVL_ADAPTOR] =3D { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_a= daptor }, [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, - [DDP_COMPONENT_DSI0] =3D { MTK_DSI, 0, &ddp_dsi }, - [DDP_COMPONENT_DSI1] =3D { MTK_DSI, 1, &ddp_dsi }, - [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, - [DDP_COMPONENT_DSI3] =3D { MTK_DSI, 3, &ddp_dsi }, + [DDP_COMPONENT_DSI0] =3D { MTK_DISP_DSI, 0, &ddp_dsi }, + [DDP_COMPONENT_DSI1] =3D { MTK_DISP_DSI, 1, &ddp_dsi }, + [DDP_COMPONENT_DSI2] =3D { MTK_DISP_DSI, 2, &ddp_dsi }, + [DDP_COMPONENT_DSI3] =3D { MTK_DISP_DSI, 3, &ddp_dsi }, [DDP_COMPONENT_GAMMA] =3D { MTK_DISP_GAMMA, 0, &ddp_gamma }, [DDP_COMPONENT_MERGE0] =3D { MTK_DISP_MERGE, 0, &ddp_merge }, [DDP_COMPONENT_MERGE1] =3D { MTK_DISP_MERGE, 1, &ddp_merge }, @@ -659,9 +659,9 @@ int mtk_ddp_comp_init(struct device *dev, struct device= _node *node, struct mtk_d type =3D=3D MTK_DISP_PWM || type =3D=3D MTK_DISP_RDMA || type =3D=3D MTK_DISP_WDMA || - type =3D=3D MTK_DPI || - type =3D=3D MTK_DP_INTF || - type =3D=3D MTK_DSI) + type =3D=3D MTK_DISP_DPI || + type =3D=3D MTK_DISP_DP_INTF || + type =3D=3D MTK_DISP_DSI) return 0; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index e54f0654f2f9..9c6dfc1e384b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -801,35 +801,35 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[= ] =3D { { .compatible =3D "mediatek,mt8173-disp-wdma", .data =3D (void *)MTK_DISP_WDMA }, { .compatible =3D "mediatek,mt2701-dpi", - .data =3D (void *)MTK_DPI }, + .data =3D (void *)MTK_DISP_DPI }, { .compatible =3D "mediatek,mt8167-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { .compatible =3D "mediatek,mt8173-dpi", - .data =3D (void *)MTK_DPI }, + .data =3D (void *)MTK_DISP_DPI }, { .compatible =3D "mediatek,mt8183-dpi", - .data =3D (void *)MTK_DPI }, + .data =3D (void *)MTK_DISP_DPI }, { .compatible =3D "mediatek,mt8186-dpi", - .data =3D (void *)MTK_DPI }, + .data =3D (void *)MTK_DISP_DPI }, { .compatible =3D "mediatek,mt8188-dp-intf", - .data =3D (void *)MTK_DP_INTF }, + .data =3D (void *)MTK_DISP_DP_INTF }, { .compatible =3D "mediatek,mt8192-dpi", - .data =3D (void *)MTK_DPI }, + .data =3D (void *)MTK_DISP_DPI }, { .compatible =3D "mediatek,mt8195-dp-intf", - .data =3D (void *)MTK_DP_INTF }, + .data =3D (void *)MTK_DISP_DP_INTF }, { .compatible =3D "mediatek,mt8195-dpi", - .data =3D (void *)MTK_DPI }, + .data =3D (void *)MTK_DISP_DPI }, { .compatible =3D "mediatek,mt2701-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { .compatible =3D "mediatek,mt8173-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { .compatible =3D "mediatek,mt8183-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { .compatible =3D "mediatek,mt8186-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { .compatible =3D "mediatek,mt8188-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { .compatible =3D "mediatek,mt8196-dsi", - .data =3D (void *)MTK_DSI }, + .data =3D (void *)MTK_DISP_DSI }, { } }; =20 @@ -1176,9 +1176,9 @@ static int mtk_drm_probe(struct platform_device *pdev) comp_type =3D=3D MTK_DISP_OVL_ADAPTOR || comp_type =3D=3D MTK_DISP_RDMA || comp_type =3D=3D MTK_DISP_WDMA || - comp_type =3D=3D MTK_DP_INTF || - comp_type =3D=3D MTK_DPI || - comp_type =3D=3D MTK_DSI) { + comp_type =3D=3D MTK_DISP_DP_INTF || + comp_type =3D=3D MTK_DISP_DPI || + comp_type =3D=3D MTK_DISP_DSI) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, component_compare_of, diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index 3ddfdeac658d..bbdd0b01927d 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -111,9 +111,9 @@ enum mtk_ddp_comp_type { MTK_DISP_MDP_RDMA, =20 /* Keep Display outputs at the end for readability */ - MTK_DPI, - MTK_DP_INTF, - MTK_DSI, + MTK_DISP_DPI, + MTK_DISP_DP_INTF, + MTK_DISP_DSI, =20 MTK_DDP_COMP_TYPE_MAX }; --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0142E390990; 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Tue, 14 Jul 2026 13:44:37 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 07/46] drm/mediatek: Use hashtable for components discovery and registration Date: Tue, 14 Jul 2026 13:43:35 +0200 Message-ID: <20260714114414.184512-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As a preparation for refactoring the concept of hardware component identification, search, and final usage, remove the ddp_comp array of components and replace it with a hashtable, indexed by ID. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 44 ++++++++++++++++------- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 48 ++++++++++++++++++------- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 23 +++++++++++- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 ++-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +- 5 files changed, 94 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index d4be40b2574a..35cf5b4ab271 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -726,8 +726,12 @@ static void mtk_crtc_update_output(struct drm_crtc *cr= tc, crtc_state->connectors_changed, encoder_mask, crtc_index); =20 for (i =3D 0; i < mtk_crtc->num_conn_routes; i++) { - unsigned int comp_id =3D mtk_crtc->conn_routes[i].route_ddp; - struct mtk_ddp_comp *comp =3D &priv->ddp_comp[comp_id]; + const struct mtk_drm_route *conn_route =3D &mtk_crtc->conn_routes[i]; + struct mtk_ddp_comp *comp; + + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, conn_route->route_ddp); + if (!comp) + continue; =20 if (comp->encoder_index >=3D 0 && (encoder_mask & BIT(comp->encoder_index))) { @@ -1029,10 +1033,11 @@ int mtk_crtc_create(struct drm_device *drm_dev, con= st unsigned int *path, { struct mtk_drm_private *priv =3D drm_dev->dev_private; struct device *dev =3D drm_dev->dev; + struct mtk_ddp_comp *dma_comp; struct mtk_crtc *mtk_crtc; unsigned int num_comp_planes =3D 0; int ret; - int i; + int i, j; bool has_ctm =3D false; uint gamma_lut_size =3D 0; struct drm_crtc *tmp; @@ -1052,7 +1057,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const= unsigned int *path, struct mtk_ddp_comp *comp; =20 node =3D priv->comp_node[comp_id]; - comp =3D &priv->ddp_comp[comp_id]; + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_id); =20 /* Not all drm components have a DTS device node, such as ovl_adaptor, * which is the drm bring up sub driver @@ -1064,7 +1069,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const= unsigned int *path, return 0; } =20 - if (!comp->dev) { + if (!comp || !comp->dev) { dev_err(dev, "Component %pOF not initialized\n", node); return -ENODEV; } @@ -1086,12 +1091,17 @@ int mtk_crtc_create(struct drm_device *drm_dev, con= st unsigned int *path, return ret; } =20 - for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { + for (i =3D 0, j =3D 0; i < mtk_crtc->ddp_comp_nr; i++, j++) { unsigned int comp_id =3D path[i]; struct mtk_ddp_comp *comp; =20 - comp =3D &priv->ddp_comp[comp_id]; - mtk_crtc->ddp_comp[i] =3D comp; + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_id); + if (!comp) { + j--; + dev_dbg(dev, "Cannot find component %d.\n", comp_id); + continue; + } + mtk_crtc->ddp_comp[j] =3D comp; =20 if (comp->funcs) { if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) { @@ -1128,7 +1138,14 @@ int mtk_crtc_create(struct drm_device *drm_dev, cons= t unsigned int *path, * In the case of ovl_adaptor sub driver, it needs to use the * dma_dev_get function to get representative dma dev. */ - mtk_crtc->dma_dev =3D mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]); + dma_comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, path[0]); + if (dma_comp =3D=3D NULL) { + dev_err(dev, "Could not find appropriate DMA device!\n"); + return -EINVAL; + } + + mtk_crtc->dma_dev =3D mtk_ddp_comp_dma_dev_get(dma_comp); + dev_dbg(dev, "Using DMA device %pOF\n", mtk_crtc->dma_dev->of_node); =20 ret =3D mtk_crtc_init(drm_dev, mtk_crtc, crtc_i); if (ret < 0) @@ -1185,17 +1202,18 @@ int mtk_crtc_create(struct drm_device *drm_dev, con= st unsigned int *path, for (i =3D 0; i < num_conn_routes; i++) { unsigned int comp_id =3D conn_routes[i].route_ddp; struct device_node *node =3D priv->comp_node[comp_id]; - struct mtk_ddp_comp *comp =3D &priv->ddp_comp[comp_id]; + struct mtk_ddp_comp *comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, com= p_id); =20 - if (!comp->dev) { + if (!comp || !comp->dev) { dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n", comp_id, node); /* mark encoder_index to -1, if route comp device is not enabled */ - comp->encoder_index =3D -1; + if (comp) + comp->encoder_index =3D -1; continue; } =20 - mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]); + mtk_ddp_comp_encoder_index_set(comp); } =20 mtk_crtc->num_conn_routes =3D num_conn_routes; diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index a6c1815ffa39..d716fd9f8a70 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -480,10 +480,24 @@ static const struct mtk_ddp_comp_match mtk_ddp_matche= s[DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_WDMA1] =3D { MTK_DISP_WDMA, 1, &ddp_wdma }, }; =20 +static bool mtk_ddp_find_comp_dev_in_table(const struct mtk_drm_comp_list = *hlist, + const unsigned int comp_id, + struct device *dev) +{ + struct mtk_ddp_comp *ddp_comp; + + hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_id) { + if (ddp_comp->dev =3D=3D dev) + return true; + } + + return false; +} + static bool mtk_ddp_comp_find(struct device *dev, const unsigned int *path, unsigned int path_len, - struct mtk_ddp_comp *ddp_comp) + const struct mtk_drm_comp_list *hlist) { unsigned int i; =20 @@ -491,7 +505,7 @@ static bool mtk_ddp_comp_find(struct device *dev, return false; =20 for (i =3D 0U; i < path_len; i++) - if (dev =3D=3D ddp_comp[path[i]].dev) + if (mtk_ddp_find_comp_dev_in_table(hlist, path[i], dev)) return true; =20 return false; @@ -500,7 +514,7 @@ static bool mtk_ddp_comp_find(struct device *dev, static int mtk_ddp_comp_find_in_route(struct device *dev, const struct mtk_drm_route *routes, unsigned int num_routes, - struct mtk_ddp_comp *ddp_comp) + const struct mtk_drm_comp_list *hlist) { unsigned int i; =20 @@ -508,7 +522,7 @@ static int mtk_ddp_comp_find_in_route(struct device *de= v, return -EINVAL; =20 for (i =3D 0; i < num_routes; i++) - if (dev =3D=3D ddp_comp[routes[i].route_ddp].dev) + if (mtk_ddp_find_comp_dev_in_table(hlist, routes[i].route_ddp, dev)) return BIT(routes[i].crtc_id); =20 return -ENODEV; @@ -566,7 +580,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, str= uct device *dev) priv_n->comp_node)) { if (mtk_ddp_comp_find(dev, data->main_path, data->main_len, - priv_n->ddp_comp)) + &priv_n->hlist)) return BIT(i); i++; } @@ -575,7 +589,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, str= uct device *dev) priv_n->comp_node)) { if (mtk_ddp_comp_find(dev, data->ext_path, data->ext_len, - priv_n->ddp_comp)) + &priv_n->hlist)) return BIT(i); i++; } @@ -584,7 +598,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, str= uct device *dev) priv_n->comp_node)) { if (mtk_ddp_comp_find(dev, data->third_path, data->third_len, - priv_n->ddp_comp)) + &priv_n->hlist)) return BIT(i); i++; } @@ -593,7 +607,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, str= uct device *dev) ret =3D mtk_ddp_comp_find_in_route(dev, private->data->conn_routes, private->data->num_conn_routes, - private->ddp_comp); + &private->hlist); =20 if (ret < 0) DRM_INFO("Failed to find comp in ddp table, ret =3D %d\n", ret); @@ -615,10 +629,12 @@ static void mtk_ddp_comp_clk_put(void *_clk) clk_put(clk); } =20 -int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct= mtk_ddp_comp *comp, +int mtk_ddp_comp_init(struct device *dev, struct device_node *node, + struct mtk_drm_comp_list *hlist, unsigned int comp_id) { struct platform_device *comp_pdev; + struct mtk_ddp_comp *comp; enum mtk_ddp_comp_type type; struct mtk_ddp_comp_dev *priv; int ret; @@ -626,6 +642,10 @@ int mtk_ddp_comp_init(struct device *dev, struct devic= e_node *node, struct mtk_d if (comp_id >=3D DDP_COMPONENT_DRM_ID_MAX) return -EINVAL; =20 + comp =3D devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); + if (!comp) + return -ENOMEM; + type =3D mtk_ddp_matches[comp_id].type; =20 comp->id =3D comp_id; @@ -633,8 +653,10 @@ int mtk_ddp_comp_init(struct device *dev, struct devic= e_node *node, struct mtk_d /* Not all drm components have a DTS device node, such as ovl_adaptor, * which is the drm bring up sub driver */ - if (!node) - return 0; + if (!node) { + comp->dev =3D dev; + goto end; + } =20 comp_pdev =3D of_find_device_by_node(node); if (!comp_pdev) { @@ -662,7 +684,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device= _node *node, struct mtk_d type =3D=3D MTK_DISP_DPI || type =3D=3D MTK_DISP_DP_INTF || type =3D=3D MTK_DISP_DSI) - return 0; + goto end; =20 priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -687,6 +709,8 @@ int mtk_ddp_comp_init(struct device *dev, struct device= _node *node, struct mtk_d #endif =20 platform_set_drvdata(comp_pdev, priv); +end: + hash_add(hlist->ddp_list, &comp->lnode, comp->id); =20 return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index bbc66072fe6b..4203eecb2a7b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -6,6 +6,7 @@ #ifndef MTK_DDP_COMP_H #define MTK_DDP_COMP_H =20 +#include #include #include #include @@ -24,6 +25,11 @@ struct drm_dsc_config; =20 struct mtk_ddp_comp; struct cmdq_pkt; + +struct mtk_drm_comp_list { + DECLARE_HASHTABLE(ddp_list, 8); +}; + struct mtk_ddp_comp_funcs { int (*power_on)(struct device *dev); void (*power_off)(struct device *dev); @@ -75,6 +81,8 @@ struct mtk_ddp_comp { unsigned int id; int encoder_index; const struct mtk_ddp_comp_funcs *funcs; + + struct hlist_node lnode; }; =20 static inline int mtk_ddp_comp_power_on(struct mtk_ddp_comp *comp) @@ -331,10 +339,23 @@ static inline void mtk_ddp_comp_encoder_index_set(str= uct mtk_ddp_comp *comp) comp->encoder_index =3D (int)comp->funcs->encoder_index(comp->dev); } =20 +static inline struct mtk_ddp_comp +*mtk_ddp_comp_find_by_id(struct mtk_drm_comp_list *hlist, + const unsigned int id) +{ + struct mtk_ddp_comp *ddp_comp; + + hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, id) + return ddp_comp; + + return NULL; +} + int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev); -int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, s= truct mtk_ddp_comp *comp, +int mtk_ddp_comp_init(struct device *dev, struct device_node *node, + struct mtk_drm_comp_list *hlist, unsigned int comp_id); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 9c6dfc1e384b..e956e1966b86 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -1086,6 +1086,8 @@ static int mtk_drm_probe(struct platform_device *pdev) if (!mtk_drm_data) return -EINVAL; =20 + hash_init(private->hlist.ddp_list); + /* Try to build the display pipeline from devicetree graphs */ if (of_graph_is_present(phandle)) { dev_dbg(dev, "Building display pipeline for MMSYS %u\n", @@ -1116,8 +1118,7 @@ static int mtk_drm_probe(struct platform_device *pdev) PLATFORM_DEVID_AUTO, (void *)private->mmsys_dev, sizeof(*private->mmsys_dev)); - private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev =3D &ovl_adaptor->d= ev; - mtk_ddp_comp_init(dev, NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_AD= APTOR], + mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &private->hlist, DDP_COMPONENT_DRM_OVL_ADAPTOR); component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); } @@ -1185,7 +1186,7 @@ static int mtk_drm_probe(struct platform_device *pdev) node); } =20 - ret =3D mtk_ddp_comp_init(dev, node, &private->ddp_comp[comp_id], comp_i= d); + ret =3D mtk_ddp_comp_init(dev, node, &private->hlist, comp_id); if (ret) { of_node_put(node); goto err_node; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 8b5c51d93f72..a171126d580e 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -60,8 +60,8 @@ struct mtk_drm_private { struct device_node *mutex_node; struct device *mutex_dev; struct device *mmsys_dev; + struct mtk_drm_comp_list hlist; struct device_node *comp_node[DDP_COMPONENT_DRM_ID_MAX]; - struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_DRM_ID_MAX]; struct mtk_mmsys_driver_data *data; struct drm_atomic_commit *suspend_state; unsigned int mbox_index; --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C60D53914E2; Tue, 14 Jul 2026 11:44:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029491; cv=none; b=Xg6vbpV8XWSqIgTojz9cjkWcKubhYko2RJbOkbXLkuYfA1JLZJmaw96GLD+hBmVohquAcy2e+sKCj1KvMKOSFP3w4JpNTwv130KnHo8gPtG8hEFZeC3+tJ9yJ4U48+8Xm6BJmmjPkEC+EkRKuH1cnBIRt7vEJKSWaSPrZUh+F64= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029479; bh=a3Zk9VtwjzQZ0fQ39QCCtxiwLry/La2QPCCPr/aNPEs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mgwGgJXCRzEOdwC7wAnqJJ7sLRdNLOHiObE/1iZpQOdcG6n4pJfi6iEKexkOQjxq+ i8e8psG6eMH5lVecw5Nr8KhpUq+f2zjRf1A+3Wm1JJ5BHocNWmkmf60VpO22yjdQRX I6lNxyVTEpEPx1Lk27kOJaFJsRgDKF4DxaGY6LYzJR8BjBqc5UCajlkcTfaKRuPP8p 2GwzFEb26cMPTcQke3Gqlib1mMClMDhGlx19H3ygr+NHOlhnCn9ZDgdXMMqtKJwcIv 3+M64jqq7dw9yhabTlAb3/U5PfJftdueXyGJPePhQQW8U16GPB7Iis6Vu2D+cf8Bp6 NsTfA0h0uYY2Q== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 54F1317E010F; Tue, 14 Jul 2026 13:44:38 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com, CK Hu Subject: [PATCH v2 08/46] drm/mediatek: ddp_comp: Move internal component register in function Date: Tue, 14 Jul 2026 13:43:36 +0200 Message-ID: <20260714114414.184512-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding an helper serving the purpose of finally removing duplicated code to check for internal/simple components, and for improving human readability in the up coming refactoring, move the internal/simple component registration logic to its own mtk_ddp_comp_init_internal_comp() function. This brings no functional changes. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 55 +++++++++++++++---------- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index d716fd9f8a70..2ba2123238b3 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -629,6 +629,38 @@ static void mtk_ddp_comp_clk_put(void *_clk) clk_put(clk); } =20 +static int mtk_ddp_comp_init_internal_comp(struct device *dev, struct devi= ce *comp_dev) +{ + struct device_node *comp_node =3D comp_dev->of_node; + struct mtk_ddp_comp_dev *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->regs =3D devm_of_iomap(dev, comp_node, 0, NULL); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + priv->clk =3D of_clk_get(comp_node, 0); + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + ret =3D devm_add_action_or_reset(dev, mtk_ddp_comp_clk_put, priv->clk); + if (ret) + return ret; + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + ret =3D cmdq_dev_get_client_reg(comp_dev, &priv->cmdq_reg, 0); + if (ret) + dev_dbg(comp_dev, "get mediatek,gce-client-reg fail!\n"); +#endif + dev_set_drvdata(comp_dev, priv); + + return 0; +}; + int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_drm_comp_list *hlist, unsigned int comp_id) @@ -636,7 +668,6 @@ int mtk_ddp_comp_init(struct device *dev, struct device= _node *node, struct platform_device *comp_pdev; struct mtk_ddp_comp *comp; enum mtk_ddp_comp_type type; - struct mtk_ddp_comp_dev *priv; int ret; =20 if (comp_id >=3D DDP_COMPONENT_DRM_ID_MAX) @@ -686,29 +717,9 @@ int mtk_ddp_comp_init(struct device *dev, struct devic= e_node *node, type =3D=3D MTK_DISP_DSI) goto end; =20 - priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); - if (!priv) - return -ENOMEM; - - priv->regs =3D devm_of_iomap(dev, node, 0, NULL); - if (IS_ERR(priv->regs)) - return PTR_ERR(priv->regs); - - priv->clk =3D of_clk_get(node, 0); - if (IS_ERR(priv->clk)) - return PTR_ERR(priv->clk); - - ret =3D devm_add_action_or_reset(dev, mtk_ddp_comp_clk_put, priv->clk); + ret =3D mtk_ddp_comp_init_internal_comp(dev, comp->dev); if (ret) return ret; - -#if IS_REACHABLE(CONFIG_MTK_CMDQ) - ret =3D cmdq_dev_get_client_reg(comp->dev, &priv->cmdq_reg, 0); - if (ret) - dev_dbg(comp->dev, "get mediatek,gce-client-reg fail!\n"); -#endif - - platform_set_drvdata(comp_pdev, priv); end: hash_add(hlist->ddp_list, &comp->lnode, comp->id); =20 --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0B4E38D3F2; Tue, 14 Jul 2026 11:44:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029490; 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Tue, 14 Jul 2026 13:44:39 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 09/46] drm/mediatek: De-duplicate internal component checks Date: Tue, 14 Jul 2026 13:43:37 +0200 Message-ID: <20260714114414.184512-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both mtk_ddp_comp and mtk_drm_drv are performing similar checks to distinguish components that have an external driver from ones that don't - with the exception of mtk_ddp_comp also checking if the component is related to a backlight driver. Create helper functions in the main component management driver mtk_ddp_comp, one to check if the currently checked component is internal/simple, and one (static, internal to mtk_ddp_comp only) to check if it is a backlight related one. Since the amount of internal/simple components is lower than the amount of ones having a specific driver, and since it is expected that most of (if not all) of any new hardware support will need a specific driver as well, the helpers are doing an inverted check compared to what the code was doing before, as both mtk_ddp_comp and mtk_drm_drv were checking for external component explicitly, while now they're doing the same, but checking if NOT internal. Also, while at it, for the OVL_ADAPTOR components case, instead of checking for MTK_DISP_OVL_ADAPTOR, call the already provided mtk_ovl_adaptor_is_comp_present() function to check for this type of component. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 46 ++++++++++++++----------- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 16 ++------- 3 files changed, 29 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 2ba2123238b3..a9c3e29fb340 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -629,6 +629,26 @@ static void mtk_ddp_comp_clk_put(void *_clk) clk_put(clk); } =20 +static bool mtk_ddp_comp_is_backlight_comp(enum mtk_ddp_comp_type type) +{ + return type =3D=3D MTK_DISP_BLS || type =3D=3D MTK_DISP_PWM; +} + +bool mtk_ddp_comp_is_internal_comp(enum mtk_ddp_comp_type type) +{ + switch (type) { + case MTK_DISP_DITHER: + case MTK_DISP_OD: + case MTK_DISP_POSTMASK: + case MTK_DISP_UFOE: + return true; + default: + break; + }; + + return false; +} + static int mtk_ddp_comp_init_internal_comp(struct device *dev, struct devi= ce *comp_dev) { struct device_node *comp_node =3D comp_dev->of_node; @@ -700,26 +720,12 @@ int mtk_ddp_comp_init(struct device *dev, struct devi= ce_node *node, if (ret) return ret; =20 - if (type =3D=3D MTK_DISP_AAL || - type =3D=3D MTK_DISP_BLS || - type =3D=3D MTK_DISP_CCORR || - type =3D=3D MTK_DISP_COLOR || - type =3D=3D MTK_DISP_DSC || - type =3D=3D MTK_DISP_GAMMA || - type =3D=3D MTK_DISP_MERGE || - type =3D=3D MTK_DISP_OVL || - type =3D=3D MTK_DISP_OVL_2L || - type =3D=3D MTK_DISP_PWM || - type =3D=3D MTK_DISP_RDMA || - type =3D=3D MTK_DISP_WDMA || - type =3D=3D MTK_DISP_DPI || - type =3D=3D MTK_DISP_DP_INTF || - type =3D=3D MTK_DISP_DSI) - goto end; - - ret =3D mtk_ddp_comp_init_internal_comp(dev, comp->dev); - if (ret) - return ret; + /* If there's no external driver for this component, allocate and init no= w */ + if (mtk_ddp_comp_is_internal_comp(type) || mtk_ddp_comp_is_backlight_comp= (type)) { + ret =3D mtk_ddp_comp_init_internal_comp(dev, comp->dev); + if (ret) + return ret; + } end: hash_add(hlist->ddp_list, &comp->lnode, comp->id); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 4203eecb2a7b..58a06add1368 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -351,6 +351,7 @@ static inline struct mtk_ddp_comp return NULL; } =20 +bool mtk_ddp_comp_is_internal_comp(enum mtk_ddp_comp_type type); int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type); int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index e956e1966b86..18683aee61ff 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -1166,20 +1166,8 @@ static int mtk_drm_probe(struct platform_device *pde= v) * blocks have separate component platform drivers and initialize their = own * DDP component structure. The others are initialized here. */ - if (comp_type =3D=3D MTK_DISP_AAL || - comp_type =3D=3D MTK_DISP_CCORR || - comp_type =3D=3D MTK_DISP_COLOR || - comp_type =3D=3D MTK_DISP_DSC || - comp_type =3D=3D MTK_DISP_GAMMA || - comp_type =3D=3D MTK_DISP_MERGE || - comp_type =3D=3D MTK_DISP_OVL || - comp_type =3D=3D MTK_DISP_OVL_2L || - comp_type =3D=3D MTK_DISP_OVL_ADAPTOR || - comp_type =3D=3D MTK_DISP_RDMA || - comp_type =3D=3D MTK_DISP_WDMA || - comp_type =3D=3D MTK_DISP_DP_INTF || - comp_type =3D=3D MTK_DISP_DPI || - comp_type =3D=3D MTK_DISP_DSI) { + if (!mtk_ddp_comp_is_internal_comp(comp_type) && + !mtk_ovl_adaptor_is_comp_present(node)) { dev_info(dev, "Adding component match for %pOF\n", node); drm_of_component_match_add(dev, &match, component_compare_of, --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A3DD3815E8; Tue, 14 Jul 2026 11:44:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029492; cv=none; b=HLBpuUsu8i0hJ5ltNQzxzdibubvGLqeyIdi+yXztrJjw9fBToxiz8LbYtLcc0Nh6BGpcqBcaminfSrRgPM6DsGlcgps5naa3SbdcgBQjq6rSz+7Df0Ezrm2UxFfGEDkp2Pjczj6X8fisAZtBEq6QAfs4p1Hfk7O05LRgTWF5ejA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029492; c=relaxed/simple; bh=sYj8SE1PeCUe7saKTnrONKQe/AoFoWh2n4vLGNFWoXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TZ56hi+0etrbvSEfVeg9nwEWWzk6K3/QCZBbPvSg7/MIcU/XHpHyo5dnjSsLWvbgAGY59Z5J4N4iNAwUxHu38/ZgzFIJL55+7vQFpScymBEMNGFH8OJIcQ2XIC1WLBE/V/2LaiMBKAX+BSIM11LgpDzg9EcvKX7ZUrA/owfoltQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=c0XpjIaU; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="c0XpjIaU" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029482; bh=sYj8SE1PeCUe7saKTnrONKQe/AoFoWh2n4vLGNFWoXU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=c0XpjIaUUAZXfMi8xRHUlVebz+tziEI8sU/yAp8uKwPQOf+LblkDsouRN8Ag9NQeO bP7NBT6tvU6ogRB4AfBZlqjcHLPACiQyh0F9awvkUTGVLsi2BXXIvtt9R1LHuhhKnM 8yDCEwxg5b6chZ8rlgCQyQWYcYQ9RtAcMCSKk59V13jqh+y8vSuqn7neuX8Rmx2pGb Whns1HlDYgm/prx1ktfdLTD1PJLGb6IiVjHU8lfJkTibx7YmBYMJ26WdKpk+8A5A4u YmhkT6aLLTYtk5pELyiiMq9Rpg3srCF4JTSgXm0y8B+AVAu1bF4ZNP2bQyIs1voOUG ZEnpAouILg1jQ== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 3AF3417E087B; Tue, 14 Jul 2026 13:44:40 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 10/46] drm/mediatek: Introduce and use path/comp definition structures Date: Tue, 14 Jul 2026 13:43:38 +0200 Message-ID: <20260714114414.184512-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for a bigger restructuring of Display Controller HW sub-component handing and path building, introduce two new mtk_drm_comp_definition and mtk_drm_path definition structures, meant to replace all of the {main,ext,third}_path pointers and supportive length variables. Obviously, also change all of the functions that were previously using the old path array pointers to use the new structures. This made possible to loop through the path definition structures, shortening various code paths and hence improving readability but, as a nice side effect, now it is possible to easily extend the maximum number of outputs that are supported by the driver. Of course, even though that could be done by simply extending the already present mtk_crtc_path enumeration (which now also indexes the mtk_drm_path_definition array in mtk_mmsys_driver_data), doing so will increase the memory footprint for all platforms (even the ones with a single output): this is currently left unresolved, but this change makes performing a future optimization to add dynamic CRTC output indexing(/numbers) way easier than before. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 24 +- drivers/gpu/drm/mediatek/mtk_crtc.h | 4 +- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 51 +-- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 2 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 573 +++++++++++++----------- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 17 +- 6 files changed, 361 insertions(+), 310 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 35cf5b4ab271..3eab78a72b8b 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2015 MediaTek Inc. + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -1026,12 +1028,13 @@ struct device *mtk_crtc_dma_dev_get(struct drm_crtc= *crtc) return mtk_crtc->dma_dev; } =20 -int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path, - unsigned int path_len, int priv_data_index, +int mtk_crtc_create(struct drm_device *drm_dev, + enum mtk_crtc_path path_sel, int priv_data_index, const struct mtk_drm_route *conn_routes, unsigned int num_conn_routes) { struct mtk_drm_private *priv =3D drm_dev->dev_private; + const struct mtk_drm_path_definition *output_path; struct device *dev =3D drm_dev->dev; struct mtk_ddp_comp *dma_comp; struct mtk_crtc *mtk_crtc; @@ -1043,16 +1046,14 @@ int mtk_crtc_create(struct drm_device *drm_dev, con= st unsigned int *path, struct drm_crtc *tmp; int crtc_i =3D 0; =20 - if (!path) - return 0; - priv =3D priv->all_drm_private[priv_data_index]; + output_path =3D &priv->data->output_paths[path_sel]; =20 drm_for_each_crtc(tmp, drm_dev) crtc_i++; =20 - for (i =3D 0; i < path_len; i++) { - enum mtk_ddp_comp_id comp_id =3D path[i]; + for (i =3D 0; i < output_path[i].len; i++) { + enum mtk_ddp_comp_id comp_id =3D output_path->comp[i].type; struct device_node *node; struct mtk_ddp_comp *comp; =20 @@ -1076,12 +1077,13 @@ int mtk_crtc_create(struct drm_device *drm_dev, con= st unsigned int *path, } =20 mtk_crtc =3D devm_kzalloc(dev, - struct_size(mtk_crtc, ddp_comp, path_len + (conn_routes ? 1 : 0)), + struct_size(mtk_crtc, ddp_comp, + output_path->len + (conn_routes ? 1 : 0)), GFP_KERNEL); if (!mtk_crtc) return -ENOMEM; =20 - mtk_crtc->ddp_comp_nr =3D path_len; + mtk_crtc->ddp_comp_nr =3D output_path->len; mtk_crtc->mmsys_dev =3D priv->mmsys_dev; =20 mtk_crtc->mutex =3D mtk_mutex_get(priv->mutex_dev); @@ -1092,7 +1094,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const= unsigned int *path, } =20 for (i =3D 0, j =3D 0; i < mtk_crtc->ddp_comp_nr; i++, j++) { - unsigned int comp_id =3D path[i]; + unsigned int comp_id =3D output_path->comp[i].type; struct mtk_ddp_comp *comp; =20 comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_id); @@ -1138,7 +1140,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const= unsigned int *path, * In the case of ovl_adaptor sub driver, it needs to use the * dma_dev_get function to get representative dma dev. */ - dma_comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, path[0]); + dma_comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, output_path->comp[0].t= ype); if (dma_comp =3D=3D NULL) { dev_err(dev, "Could not find appropriate DMA device!\n"); return -EINVAL; diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h b/drivers/gpu/drm/mediatek= /mtk_crtc.h index a6b8697cca97..5a18b6bfa06b 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_crtc.h @@ -15,8 +15,8 @@ #define MTK_MIN_BPC 3 =20 void mtk_crtc_commit(struct drm_crtc *crtc); -int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path, - unsigned int path_len, int priv_data_index, +int mtk_crtc_create(struct drm_device *drm_dev, + enum mtk_crtc_path path_sel, int priv_data_index, const struct mtk_drm_route *conn_routes, unsigned int num_conn_routes); int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index a9c3e29fb340..8ba75da0bf2d 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -495,17 +495,13 @@ static bool mtk_ddp_find_comp_dev_in_table(const stru= ct mtk_drm_comp_list *hlist } =20 static bool mtk_ddp_comp_find(struct device *dev, - const unsigned int *path, - unsigned int path_len, + const struct mtk_drm_path_definition *output_path, const struct mtk_drm_comp_list *hlist) { unsigned int i; =20 - if (path =3D=3D NULL) - return false; - - for (i =3D 0U; i < path_len; i++) - if (mtk_ddp_find_comp_dev_in_table(hlist, path[i], dev)) + for (i =3D 0U; i < output_path->len; i++) + if (mtk_ddp_find_comp_dev_in_table(hlist, output_path->comp[i].type, dev= )) return true; =20 return false; @@ -528,21 +524,17 @@ static int mtk_ddp_comp_find_in_route(struct device *= dev, return -ENODEV; } =20 -static bool mtk_ddp_path_available(const unsigned int *path, - unsigned int path_len, +static bool mtk_ddp_path_available(const struct mtk_drm_path_definition *o= utput_path, struct device_node **comp_node) { unsigned int i; =20 - if (!path || !path_len) - return false; - - for (i =3D 0U; i < path_len; i++) { + for (i =3D 0U; i < output_path->len; i++) { /* OVL_ADAPTOR doesn't have a device node */ - if (path[i] =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) + if (output_path->comp[i].type =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) continue; =20 - if (!comp_node[path[i]]) + if (!comp_node[output_path->comp[i].type]) return false; } =20 @@ -576,31 +568,14 @@ int mtk_find_possible_crtcs(struct drm_device *drm, s= truct device *dev) priv_n =3D private->all_drm_private[j]; data =3D priv_n->data; =20 - if (mtk_ddp_path_available(data->main_path, data->main_len, - priv_n->comp_node)) { - if (mtk_ddp_comp_find(dev, data->main_path, - data->main_len, - &priv_n->hlist)) - return BIT(i); - i++; - } - - if (mtk_ddp_path_available(data->ext_path, data->ext_len, - priv_n->comp_node)) { - if (mtk_ddp_comp_find(dev, data->ext_path, - data->ext_len, - &priv_n->hlist)) - return BIT(i); - i++; - } + for (i =3D 0; i < MAX_CRTC; i++) { + if (!data->output_paths[i].len) + continue; =20 - if (mtk_ddp_path_available(data->third_path, data->third_len, - priv_n->comp_node)) { - if (mtk_ddp_comp_find(dev, data->third_path, - data->third_len, - &priv_n->hlist)) + ret =3D mtk_ddp_comp_find(dev, &data->output_paths[i], + &priv_n->hlist); + if (ret) return BIT(i); - i++; } } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 58a06add1368..76a2b649516d 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -15,6 +15,8 @@ =20 #include =20 +#define MTK_DISP_CONTROLLER_MAX_COMP_PER_PATH 24 + struct device; struct device_node; struct drm_crtc; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 18683aee61ff..09c7d038348d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -2,6 +2,10 @@ /* * Copyright (c) 2015 MediaTek Inc. * Author: YT SHEN + * + * Major rework + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -59,239 +63,326 @@ static const struct drm_mode_config_funcs mtk_drm_mod= e_config_funcs =3D { .atomic_commit =3D drm_atomic_helper_commit, }; =20 -static const unsigned int mt2701_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_BLS, - DDP_COMPONENT_DSI0, +static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_BLS }, + { DDP_COMPONENT_DSI0 }, }; =20 -static const unsigned int mt2701_mtk_ddp_ext[] =3D { - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DPI0, +static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, }; =20 -static const unsigned int mt7623_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_BLS, - DDP_COMPONENT_DPI0, +struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt2701_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt2701_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt2701_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt2701_mtk_ddp_ext), + }, }; =20 -static const unsigned int mt7623_mtk_ddp_ext[] =3D { - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DSI0, +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_OD0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_DPI0 }, + { DDP_COMPONENT_PWM0 }, }; =20 -static const unsigned int mt2712_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_OD0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_DPI0, - DDP_COMPONENT_PWM0, +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL1 }, + { DDP_COMPONENT_COLOR1 }, + { DDP_COMPONENT_AAL1 }, + { DDP_COMPONENT_OD1 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI1 }, + { DDP_COMPONENT_PWM1 }, }; =20 -static const unsigned int mt2712_mtk_ddp_ext[] =3D { - DDP_COMPONENT_OVL1, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_AAL1, - DDP_COMPONENT_OD1, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DPI1, - DDP_COMPONENT_PWM1, +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] =3D { + { DDP_COMPONENT_RDMA2 }, + { DDP_COMPONENT_DSI3 }, + { DDP_COMPONENT_PWM2 }, }; =20 -static const unsigned int mt2712_mtk_ddp_third[] =3D { - DDP_COMPONENT_RDMA2, - DDP_COMPONENT_DSI3, - DDP_COMPONENT_PWM2, +struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt2712_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt2712_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt2712_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt2712_mtk_ddp_ext), + }, + [CRTC_THIRD] =3D { + .comp =3D mt2712_mtk_ddp_third, + .len =3D ARRAY_SIZE(mt2712_mtk_ddp_third), + }, }; =20 -static unsigned int mt8167_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_DSI0, +static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_BLS }, + { DDP_COMPONENT_DPI0 }, }; =20 -static const unsigned int mt8173_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_OD0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_UFOE, - DDP_COMPONENT_DSI0, - DDP_COMPONENT_PWM0, +static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DSI0 }, }; =20 -static const unsigned int mt8173_mtk_ddp_ext[] =3D { - DDP_COMPONENT_OVL1, - DDP_COMPONENT_COLOR1, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DPI0, +struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt7623_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt7623_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt7623_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt7623_mtk_ddp_ext), + }, }; =20 -static const unsigned int mt8183_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_DSI0, +static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_DSI0 }, }; =20 -static const unsigned int mt8183_mtk_ddp_ext[] =3D { - DDP_COMPONENT_OVL_2L1, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DPI0, +struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8167_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8167_mtk_ddp_main), + }, }; =20 -static const unsigned int mt8186_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_POSTMASK0, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_DSI0, +static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_OD0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_UFOE }, + { DDP_COMPONENT_DSI0 }, + { DDP_COMPONENT_PWM0 }, }; =20 -static const unsigned int mt8186_mtk_ddp_ext[] =3D { - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_RDMA1, - DDP_COMPONENT_DPI0, +static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL1 }, + { DDP_COMPONENT_COLOR1 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, }; =20 -static const unsigned int mt8188_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_POSTMASK0, - DDP_COMPONENT_DITHER0, +struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8173_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8173_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8173_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8173_mtk_ddp_ext), + }, }; =20 -static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] =3D { - {0, DDP_COMPONENT_DP_INTF0}, - {0, DDP_COMPONENT_DSI0}, +static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL_2L1 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8183_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8183_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8183_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8183_mtk_ddp_ext), + }, }; =20 -static const unsigned int mt8192_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_OVL_2L0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_POSTMASK0, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_DSI0, +static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, }; =20 -static const unsigned int mt8192_mtk_ddp_ext[] =3D { - DDP_COMPONENT_OVL_2L2, - DDP_COMPONENT_RDMA4, - DDP_COMPONENT_DPI0, +static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, }; =20 -static const unsigned int mt8195_mtk_ddp_main[] =3D { - DDP_COMPONENT_OVL0, - DDP_COMPONENT_RDMA0, - DDP_COMPONENT_COLOR0, - DDP_COMPONENT_CCORR, - DDP_COMPONENT_AAL0, - DDP_COMPONENT_GAMMA, - DDP_COMPONENT_DITHER0, - DDP_COMPONENT_DSC0, - DDP_COMPONENT_MERGE0, - DDP_COMPONENT_DP_INTF0, +struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8186_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8186_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8186_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8186_mtk_ddp_ext), + }, }; =20 -static const unsigned int mt8195_mtk_ddp_ext[] =3D { - DDP_COMPONENT_DRM_OVL_ADAPTOR, - DDP_COMPONENT_MERGE5, - DDP_COMPONENT_DP_INTF1, +static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, +}; + +struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8188_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8188_mtk_ddp_main), + }, +}; + +static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL_2L2 }, + { DDP_COMPONENT_RDMA4 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8192_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8192_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8192_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8192_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSC0 }, + { DDP_COMPONENT_MERGE0 }, + { DDP_COMPONENT_DP_INTF0 }, +}; + +static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_DRM_OVL_ADAPTOR }, + { DDP_COMPONENT_MERGE5 }, + { DDP_COMPONENT_DP_INTF1 }, +}; + +struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8195_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), + }, +}; + +struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[MAX_CRTC] =3D { + [CRTC_EXT] =3D { + .comp =3D mt8195_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), + }, }; =20 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =3D { - .main_path =3D mt2701_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt2701_mtk_ddp_main), - .ext_path =3D mt2701_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt2701_mtk_ddp_ext), + .output_paths =3D mt2701_legacy_paths, .shadow_register =3D true, .mmsys_dev_num =3D 1, }; =20 -static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data =3D { - .main_path =3D mt7623_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt7623_mtk_ddp_main), - .ext_path =3D mt7623_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt7623_mtk_ddp_ext), - .shadow_register =3D true, +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data =3D { + .output_paths =3D mt2712_legacy_paths, .mmsys_dev_num =3D 1, }; =20 -static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data =3D { - .main_path =3D mt2712_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt2712_mtk_ddp_main), - .ext_path =3D mt2712_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt2712_mtk_ddp_ext), - .third_path =3D mt2712_mtk_ddp_third, - .third_len =3D ARRAY_SIZE(mt2712_mtk_ddp_third), +static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data =3D { + .output_paths =3D mt7623_legacy_paths, + .shadow_register =3D true, .mmsys_dev_num =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data =3D { - .main_path =3D mt8167_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8167_mtk_ddp_main), + .output_paths =3D mt8167_legacy_paths, .mmsys_dev_num =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data =3D { - .main_path =3D mt8173_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8173_mtk_ddp_main), - .ext_path =3D mt8173_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt8173_mtk_ddp_ext), + .output_paths =3D mt8173_legacy_paths, .mmsys_dev_num =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data =3D { - .main_path =3D mt8183_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8183_mtk_ddp_main), - .ext_path =3D mt8183_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt8183_mtk_ddp_ext), + .output_paths =3D mt8183_legacy_paths, .mmsys_dev_num =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data =3D { - .main_path =3D mt8186_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8186_mtk_ddp_main), - .ext_path =3D mt8186_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt8186_mtk_ddp_ext), + .output_paths =3D mt8186_legacy_paths, .mmsys_dev_num =3D 1, }; =20 +static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] =3D { + { 0, DDP_COMPONENT_DP_INTF0 }, + { 0, DDP_COMPONENT_DSI0 }, +}; + static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data =3D { - .main_path =3D mt8188_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8188_mtk_ddp_main), + .output_paths =3D mt8188_legacy_paths, .conn_routes =3D mt8188_mtk_ddp_main_routes, .num_conn_routes =3D ARRAY_SIZE(mt8188_mtk_ddp_main_routes), .mmsys_dev_num =3D 2, @@ -301,16 +392,12 @@ static const struct mtk_mmsys_driver_data mt8188_vdos= ys0_driver_data =3D { }; =20 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data =3D { - .main_path =3D mt8192_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8192_mtk_ddp_main), - .ext_path =3D mt8192_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt8192_mtk_ddp_ext), + .output_paths =3D mt8192_legacy_paths, .mmsys_dev_num =3D 1, }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data =3D { - .main_path =3D mt8195_mtk_ddp_main, - .main_len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), + .output_paths =3D mt8195_vdo0_legacy_paths, .mmsys_dev_num =3D 2, .max_width =3D 8191, .min_width =3D 1, @@ -318,8 +405,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys= 0_driver_data =3D { }; =20 static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data =3D { - .ext_path =3D mt8195_mtk_ddp_ext, - .ext_len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), + .output_paths =3D mt8195_vdo1_legacy_paths, .mmsys_id =3D 1, .mmsys_dev_num =3D 2, .max_width =3D 8191, @@ -384,6 +470,7 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev) int i, j; =20 for_each_child_of_node(phandle->parent, node) { + const struct mtk_drm_path_definition *output_path; struct platform_device *pdev; =20 of_id =3D of_match_node(mtk_drm_of_ids, node); @@ -404,12 +491,14 @@ static bool mtk_drm_get_all_drm_priv(struct device *d= ev) if (!temp_drm_priv) continue; =20 - if (temp_drm_priv->data->main_len) - all_drm_priv[CRTC_MAIN] =3D temp_drm_priv; - else if (temp_drm_priv->data->ext_len) - all_drm_priv[CRTC_EXT] =3D temp_drm_priv; - else if (temp_drm_priv->data->third_len) - all_drm_priv[CRTC_THIRD] =3D temp_drm_priv; + for (i =3D 0; i < MAX_CRTC; i++) { + output_path =3D &temp_drm_priv->data->output_paths[i]; + + if (!output_path->len) + continue; + + all_drm_priv[i] =3D temp_drm_priv; + } =20 if (temp_drm_priv->mtk_drm_bound) cnt++; @@ -433,27 +522,23 @@ static bool mtk_drm_get_all_drm_priv(struct device *d= ev) =20 static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int c= omp_id) { - const struct mtk_mmsys_driver_data *drv_data =3D private->data; - int i; + const struct mtk_mmsys_driver_data *data =3D private->data; + int i, j; =20 - if (drv_data->main_path) - for (i =3D 0; i < drv_data->main_len; i++) - if (drv_data->main_path[i] =3D=3D comp_id) - return true; + for (i =3D 0; i < MAX_CRTC; i++) { + const struct mtk_drm_path_definition *output_path =3D &data->output_path= s[i]; =20 - if (drv_data->ext_path) - for (i =3D 0; i < drv_data->ext_len; i++) - if (drv_data->ext_path[i] =3D=3D comp_id) - return true; + for (j =3D 0; j < output_path->len; j++) { + if (output_path->comp[j].type !=3D comp_id) + continue; =20 - if (drv_data->third_path) - for (i =3D 0; i < drv_data->third_len; i++) - if (drv_data->third_path[i] =3D=3D comp_id) - return true; + return true; + } + } =20 - if (drv_data->num_conn_routes) - for (i =3D 0; i < drv_data->num_conn_routes; i++) - if (drv_data->conn_routes[i].route_ddp =3D=3D comp_id) + if (data->num_conn_routes) + for (i =3D 0; i < data->num_conn_routes; i++) + if (data->conn_routes[i].route_ddp =3D=3D comp_id) return true; =20 return false; @@ -525,30 +610,15 @@ static int mtk_drm_kms_init(struct drm_device *drm) if (priv_n->data->min_height) drm->mode_config.min_height =3D priv_n->data->min_height; =20 - if (i =3D=3D CRTC_MAIN && priv_n->data->main_len) { - ret =3D mtk_crtc_create(drm, priv_n->data->main_path, - priv_n->data->main_len, j, - priv_n->data->conn_routes, - priv_n->data->num_conn_routes); - if (ret) - goto err_component_unbind; - + if (!priv_n->data->output_paths[i].len) continue; - } else if (i =3D=3D CRTC_EXT && priv_n->data->ext_len) { - ret =3D mtk_crtc_create(drm, priv_n->data->ext_path, - priv_n->data->ext_len, j, NULL, 0); - if (ret) - goto err_component_unbind; =20 - continue; - } else if (i =3D=3D CRTC_THIRD && priv_n->data->third_len) { - ret =3D mtk_crtc_create(drm, priv_n->data->third_path, - priv_n->data->third_len, j, NULL, 0); - if (ret) - goto err_component_unbind; + ret =3D mtk_crtc_create(drm, i, j, + priv_n->data->conn_routes, + priv_n->data->num_conn_routes); =20 - continue; - } + if (ret) + goto err_component_unbind; } } =20 @@ -847,7 +917,8 @@ static int mtk_drm_of_get_ddp_comp_type(struct device_n= ode *node, enum mtk_ddp_c =20 static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, int output_port, enum mtk_crtc_path crtc_path, - struct device_node **next, unsigned int *cid) + struct device_node **next, + struct mtk_drm_comp_definition *comp_def) { struct device_node *ep_dev_node, *ep_out; enum mtk_ddp_comp_type comp_type; @@ -875,7 +946,7 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_node= *node, ret =3D mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); if (ret) { if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { - *cid =3D (unsigned int)DDP_COMPONENT_DRM_OVL_ADAPTOR; + comp_def->type =3D DDP_COMPONENT_DRM_OVL_ADAPTOR; return 0; } return ret; @@ -886,7 +957,7 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_node= *node, return ret; =20 /* All ok! Pass the Component ID to the caller. */ - *cid =3D (unsigned int)ret; + comp_def->type =3D ret; =20 return 0; } @@ -895,8 +966,7 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_node= *node, * mtk_drm_of_ddp_path_build_one - Build a Display HW Pipeline for a CRTC = Path * @dev: The mediatek-drm device * @cpath: CRTC Path relative to a VDO or MMSYS - * @out_path: Pointer to an array that will contain the new pipeline - * @out_path_len: Number of entries in the pipeline array + * @out_path: Pointer to the structure that will contain the new pipel= ine * * MediaTek SoCs can use different DDP hardware pipelines (or paths) depen= ding * on the board-specific desired display configuration; this function walks @@ -910,20 +980,19 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_no= de *node, * * %-ENOMEM - Failure to allocate pipeline array to pass to the caller */ static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc= _path cpath, - const unsigned int **out_path, - unsigned int *out_path_len) + struct mtk_drm_path_definition *out_path) { + struct mtk_drm_comp_definition temp_path[MTK_DISP_CONTROLLER_MAX_COMP_PER= _PATH]; struct device_node *next =3D NULL, *prev, *vdo =3D dev->parent->of_node; - unsigned int temp_path[DDP_COMPONENT_DRM_ID_MAX] =3D { 0 }; - unsigned int *final_ddp_path; - unsigned short int idx =3D 0; bool ovl_adaptor_comp_added =3D false; + unsigned short int idx =3D 0; + size_t final_comp_sz; int ret; =20 /* Get the first entry for the temp_path array */ ret =3D mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); if (ret) { - if (next && temp_path[idx] =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { + if (next && temp_path[idx].type =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); ovl_adaptor_comp_added =3D true; } else { @@ -957,7 +1026,7 @@ static int mtk_drm_of_ddp_path_build_one(struct device= *dev, enum mtk_crtc_path * to probe that component master driver of which only one instance * is needed and possible. */ - if (temp_path[idx] =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { + if (temp_path[idx].type =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { if (!ovl_adaptor_comp_added) ovl_adaptor_comp_added =3D true; else @@ -973,7 +1042,7 @@ static int mtk_drm_of_ddp_path_build_one(struct device= *dev, enum mtk_crtc_path return ret; =20 /* If the last entry is not a final display output, the configuration is = wrong */ - switch (temp_path[idx - 1]) { + switch (temp_path[idx - 1].type) { case DDP_COMPONENT_DP_INTF0: case DDP_COMPONENT_DP_INTF1: case DDP_COMPONENT_DPI0: @@ -985,30 +1054,31 @@ static int mtk_drm_of_ddp_path_build_one(struct devi= ce *dev, enum mtk_crtc_path break; default: dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=3D%d)= \n", - temp_path[idx - 1], ret); + temp_path[idx - 1].type, ret); return -EINVAL; } =20 - final_ddp_path =3D devm_kmemdup(dev, temp_path, idx * sizeof(temp_path[0]= ), GFP_KERNEL); - if (!final_ddp_path) + /* Pipeline built! */ + out_path->len =3D idx; + final_comp_sz =3D out_path->len * sizeof(out_path->comp[0]); + out_path->comp =3D devm_kmemdup(dev, temp_path, final_comp_sz, GFP_KERNEL= ); + if (!out_path->comp) return -ENOMEM; =20 dev_dbg(dev, "Display HW Pipeline built with %d components.\n", idx); =20 - /* Pipeline built! */ - *out_path =3D final_ddp_path; - *out_path_len =3D idx; - return 0; } =20 static int mtk_drm_of_ddp_path_build(struct device *dev, struct device_nod= e *node, struct mtk_mmsys_driver_data *data) { + struct mtk_drm_path_definition *output_paths; struct device_node *ep_node; struct of_endpoint of_ep; bool output_present[MAX_CRTC] =3D { false }; - int ret; + u8 num_outputs_present =3D 0; + int i, ret; =20 for_each_endpoint_of_node(node, ep_node) { ret =3D of_graph_parse_endpoint(ep_node, &of_ep); @@ -1024,33 +1094,30 @@ static int mtk_drm_of_ddp_path_build(struct device = *dev, struct device_node *nod } =20 output_present[of_ep.id] =3D true; + num_outputs_present++; } + if (ret =3D=3D 0 && num_outputs_present =3D=3D 0) + ret =3D dev_err_probe(dev, -ENXIO, "No display outputs found.\n"); =20 if (ret) { of_node_put(ep_node); return ret; } =20 - if (output_present[CRTC_MAIN]) { - ret =3D mtk_drm_of_ddp_path_build_one(dev, CRTC_MAIN, - &data->main_path, &data->main_len); - if (ret && ret !=3D -ENODEV) - return ret; - } + /* This can be optimized after making CRTC numbers dynamic */ + output_paths =3D devm_kcalloc(dev, MAX_CRTC, sizeof(*output_paths), GFP_K= ERNEL); + if (!output_paths) + return -ENOMEM; =20 - if (output_present[CRTC_EXT]) { - ret =3D mtk_drm_of_ddp_path_build_one(dev, CRTC_EXT, - &data->ext_path, &data->ext_len); - if (ret && ret !=3D -ENODEV) - return ret; - } + for (i =3D 0; i < MAX_CRTC; i++) { + if (!output_present[i]) + continue; =20 - if (output_present[CRTC_THIRD]) { - ret =3D mtk_drm_of_ddp_path_build_one(dev, CRTC_THIRD, - &data->third_path, &data->third_len); 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Tue, 14 Jul 2026 13:44:42 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 11/46] drm/mediatek: Create new mtk_drm_legacy and move deprecated code Date: Tue, 14 Jul 2026 13:43:39 +0200 Message-ID: <20260714114414.184512-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since mediatek-drm shifted from hardcoded per-SoC-per-Board path definitions for the display controller to devicetree graph based path building, the first ones are used less and less, and those are also decreasing ease of code browsability (hence, readability) in the mtk_drm_drv.c file. This means that those big arrays are almost irrelevant now (for modern code, of course). Seen the need to keep compatibility with older devicetrees, then, move all of the deprecated arrays in new mtk_drm_legacy files and add a big warning to those, explaining that no new SoCs must be implemented like so, and making it clear that it shall exclusively contain legacy and deprecated code. Also, especially with the restructuring work that is currently in progress (with MuteX finally getting trigger-sources support and other changes that will follow), it is expected to see more code being moved in the mtk_drm_legacy territory. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 277 +------------------ drivers/gpu/drm/mediatek/mtk_drm_legacy.c | 309 ++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_legacy.h | 28 ++ 4 files changed, 339 insertions(+), 276 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_legacy.c create mode 100644 drivers/gpu/drm/mediatek/mtk_drm_legacy.h diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index 8079962597c8..f40ad5565716 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -13,6 +13,7 @@ mediatek-drm-y :=3D mtk_crtc.o \ mtk_disp_rdma.o \ mtk_disp_wdma.o \ mtk_drm_drv.o \ + mtk_drm_legacy.o \ mtk_dsi.o \ mtk_dpi.o \ mtk_ethdr.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 09c7d038348d..1396cbc65627 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -35,6 +35,7 @@ #include "mtk_ddp_comp.h" #include "mtk_disp_drv.h" #include "mtk_drm_drv.h" +#include "mtk_drm_legacy.h" =20 #define DRIVER_NAME "mediatek" #define DRIVER_DESC "Mediatek SoC DRM" @@ -63,282 +64,6 @@ static const struct drm_mode_config_funcs mtk_drm_mode_= config_funcs =3D { .atomic_commit =3D drm_atomic_helper_commit, }; =20 -static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_BLS }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt2701_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt2701_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt2701_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt2701_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_OD0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_DPI0 }, - { DDP_COMPONENT_PWM0 }, -}; - -static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL1 }, - { DDP_COMPONENT_COLOR1 }, - { DDP_COMPONENT_AAL1 }, - { DDP_COMPONENT_OD1 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI1 }, - { DDP_COMPONENT_PWM1 }, -}; - -static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] =3D { - { DDP_COMPONENT_RDMA2 }, - { DDP_COMPONENT_DSI3 }, - { DDP_COMPONENT_PWM2 }, -}; - -struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt2712_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt2712_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt2712_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt2712_mtk_ddp_ext), - }, - [CRTC_THIRD] =3D { - .comp =3D mt2712_mtk_ddp_third, - .len =3D ARRAY_SIZE(mt2712_mtk_ddp_third), - }, -}; - -static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_BLS }, - { DDP_COMPONENT_DPI0 }, -}; - -static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DSI0 }, -}; - -struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt7623_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt7623_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt7623_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt7623_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_DSI0 }, -}; - -struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8167_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8167_mtk_ddp_main), - }, -}; - -static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_OD0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_UFOE }, - { DDP_COMPONENT_DSI0 }, - { DDP_COMPONENT_PWM0 }, -}; - -static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL1 }, - { DDP_COMPONENT_COLOR1 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8173_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8173_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt8173_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt8173_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL_2L1 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8183_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8183_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt8183_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt8183_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8186_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8186_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt8186_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt8186_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, -}; - -struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8188_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8188_mtk_ddp_main), - }, -}; - -static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, -}; - -static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL_2L2 }, - { DDP_COMPONENT_RDMA4 }, - { DDP_COMPONENT_DPI0 }, -}; - -struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8192_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8192_mtk_ddp_main), - }, - [CRTC_EXT] =3D { - .comp =3D mt8192_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt8192_mtk_ddp_ext), - }, -}; - -static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSC0 }, - { DDP_COMPONENT_MERGE0 }, - { DDP_COMPONENT_DP_INTF0 }, -}; - -static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_DRM_OVL_ADAPTOR }, - { DDP_COMPONENT_MERGE5 }, - { DDP_COMPONENT_DP_INTF1 }, -}; - -struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] =3D { - [CRTC_MAIN] =3D { - .comp =3D mt8195_mtk_ddp_main, - .len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), - }, -}; - -struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[MAX_CRTC] =3D { - [CRTC_EXT] =3D { - .comp =3D mt8195_mtk_ddp_ext, - .len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), - }, -}; - static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data =3D { .output_paths =3D mt2701_legacy_paths, .shadow_register =3D true, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c b/drivers/gpu/drm/me= diatek/mtk_drm_legacy.c new file mode 100644 index 000000000000..623e510de9ff --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Compatibility layer for legacy mediatek-drm + * + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + * + * All (or most of) MediaTek SoCs released since around year 2014 onwards + * have got a new Multimedia System (and Display Controller) architecture, + * featuring an extreme flexibility on the connection of all of the various + * multimedia-related hardware components (or sub-IPs). + * + * Many different boards based on those SoCs are using different displays, + * different outputs, hence wildly different display pipelines: for this, + * a solution based on a devicetree graph (OF Graph) was chosen for setting + * up the correct pipeline for each device. + * + * However, removing the hardcoded display controller paths would break all + * of the devices using the new display driver on an old devicetree. + * + * This compatibility layer makes possible to keep the display controller + * functionality working when a board/device: + * - Uses an old devicetree with no OF Graph; and + * - Uses a new kernel with the new mediatek-drm graph-based pipeline + * building code. + * + * ** WARNING ** + * This exists only to avoid ABI breakages and no new SoC should ever be + * added to this file. + */ + +#include "mtk_drm_drv.h" +#include "mtk_drm_legacy.h" + +static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_BLS }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt2701_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt2701_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt2701_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt2701_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_OD0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_DPI0 }, + { DDP_COMPONENT_PWM0 }, +}; + +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL1 }, + { DDP_COMPONENT_COLOR1 }, + { DDP_COMPONENT_AAL1 }, + { DDP_COMPONENT_OD1 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI1 }, + { DDP_COMPONENT_PWM1 }, +}; + +static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] =3D { + { DDP_COMPONENT_RDMA2 }, + { DDP_COMPONENT_DSI3 }, + { DDP_COMPONENT_PWM2 }, +}; + +struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt2712_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt2712_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt2712_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt2712_mtk_ddp_ext), + }, + [CRTC_THIRD] =3D { + .comp =3D mt2712_mtk_ddp_third, + .len =3D ARRAY_SIZE(mt2712_mtk_ddp_third), + }, +}; + +static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_BLS }, + { DDP_COMPONENT_DPI0 }, +}; + +static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DSI0 }, +}; + +struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt7623_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt7623_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt7623_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt7623_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_DSI0 }, +}; + +struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8167_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8167_mtk_ddp_main), + }, +}; + +static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_OD0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_UFOE }, + { DDP_COMPONENT_DSI0 }, + { DDP_COMPONENT_PWM0 }, +}; + +static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL1 }, + { DDP_COMPONENT_COLOR1 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8173_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8173_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8173_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8173_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL_2L1 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8183_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8183_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8183_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8183_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA1 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8186_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8186_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8186_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8186_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, +}; + +struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8188_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8188_mtk_ddp_main), + }, +}; + +static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_OVL_2L0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_POSTMASK0 }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSI0 }, +}; + +static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_OVL_2L2 }, + { DDP_COMPONENT_RDMA4 }, + { DDP_COMPONENT_DPI0 }, +}; + +struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8192_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8192_mtk_ddp_main), + }, + [CRTC_EXT] =3D { + .comp =3D mt8192_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8192_mtk_ddp_ext), + }, +}; + +static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] =3D { + { DDP_COMPONENT_OVL0 }, + { DDP_COMPONENT_RDMA0 }, + { DDP_COMPONENT_COLOR0 }, + { DDP_COMPONENT_CCORR }, + { DDP_COMPONENT_AAL0 }, + { DDP_COMPONENT_GAMMA }, + { DDP_COMPONENT_DITHER0 }, + { DDP_COMPONENT_DSC0 }, + { DDP_COMPONENT_MERGE0 }, + { DDP_COMPONENT_DP_INTF0 }, +}; + +static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] =3D { + { DDP_COMPONENT_DRM_OVL_ADAPTOR }, + { DDP_COMPONENT_MERGE5 }, + { DDP_COMPONENT_DP_INTF1 }, +}; + +struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] =3D { + [CRTC_MAIN] =3D { + .comp =3D mt8195_mtk_ddp_main, + .len =3D ARRAY_SIZE(mt8195_mtk_ddp_main), + }, +}; + +struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[MAX_CRTC] =3D { + [CRTC_EXT] =3D { + .comp =3D mt8195_mtk_ddp_ext, + .len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), + }, +}; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.h b/drivers/gpu/drm/me= diatek/mtk_drm_legacy.h new file mode 100644 index 000000000000..a87741ec0dcd --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Support for legacy mediatek-drm display paths + * + * Please read mtk_drm_legacy.c for more information. + * + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#ifndef MTK_DRM_LEGACY_H +#define MTK_DRM_LEGACY_H + +struct mtk_drm_path_definition; + +extern struct mtk_drm_path_definition mt2701_legacy_paths[]; +extern struct mtk_drm_path_definition mt2712_legacy_paths[]; +extern struct mtk_drm_path_definition mt7623_legacy_paths[]; +extern struct mtk_drm_path_definition mt8167_legacy_paths[]; +extern struct mtk_drm_path_definition mt8173_legacy_paths[]; +extern struct mtk_drm_path_definition mt8183_legacy_paths[]; +extern struct mtk_drm_path_definition mt8186_legacy_paths[]; +extern struct mtk_drm_path_definition mt8188_legacy_paths[]; +extern struct mtk_drm_path_definition mt8192_legacy_paths[]; +extern struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[]; +extern struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[]; + +#endif /* MTK_DRM_LEGACY_H */ --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CA0F38A700; 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Tue, 14 Jul 2026 13:44:44 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 12/46] dt-bindings: soc: mediatek: mutex: Allow #trigger-source-cells Date: Tue, 14 Jul 2026 13:43:40 +0200 Message-ID: <20260714114414.184512-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This hardware controls trigger sources, and there's even a generic binding just for that: allow #trigger-source-cells in MuteX, so that this is allowed to provide triggers to external HW. Acked-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Acked-by: Rob Herring (Arm) --- .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.= yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 5267cfe92572..886e6f904b78 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -54,6 +54,9 @@ properties: items: - description: MUTEX Clock =20 + '#trigger-source-cells': + const: 1 + mediatek,gce-events: description: The event id which is mapping to the specific hardware event signal @@ -116,6 +119,7 @@ examples: interrupts =3D ; power-domains =3D <&spm MT8173_POWER_DOMAIN_MM>; clocks =3D <&mmsys CLK_MM_MUTEX_32K>; + #trigger-source-cells =3D <1>; mediatek,gce-events =3D , ; }; --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F15838E11C; Tue, 14 Jul 2026 11:44:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029492; cv=none; b=txhP+La/p+DR56MRYxJVE5ez7ssvfEi7cH8HEx3hV3O1va64GubzQ7ZMp2qNQUFy7+Ysh8KDrnJbZ2I2c6s5072e8UjToDn70rkREdyF3KQELxVcmQvjX2JzWY5xcWPSI4rh2fLkDjQ3YOkYFdrrnTHzcrTFCMKUOlD4olvYsZQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029492; c=relaxed/simple; bh=njLxOOznKc5yQL0JX7H38LNUKds5ZGY/et86Ey7DB10=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TGufYVL402buDC8iVt0xWAZ89BKcyF9A3qs5ZxQarDT46gkRxyQmqCwyMb5/x+eFmvg0PI/Fvp/yC9FrEF9lUKW5Jd7q3Waanq51XFTQGgUFIJ+eNqe2PJNJRTJIM21xyq87TQqkexSISixuu4czm0yJWVuNIkbZgD6AKGXthNQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=KzZzZuon; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="KzZzZuon" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029486; bh=njLxOOznKc5yQL0JX7H38LNUKds5ZGY/et86Ey7DB10=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KzZzZuonqPHRU9Ta+a050YiquhVzTijJnQM/OJyhyQgINt6CTrn3ra5Zp1IEhsGyo ofE7AMFvhS8w8br/45hWmhyRq6grtRlCMiq3UxLHkYv6olQ7noiqt/0u0Gb/tOuEsa 7AnrPMFSBRHHEN7jBXwCyOqPexoSkNZiYmHw+46vXsi4Me2r4z1in2ueV6FfSmol4g Ddd4+4xb3Ui9y8z5qcY0TL7SWGziGPAnlQIiQflTZn4C4mWJcumlnFcuUV/GASDCup I6tFYbXnPp/gCgXTb/n61Zzt/u4C/wDCx2kTnnTtHPZpHcEU03nsd+7r5bJa3YbvCt IvWhFz/nGT22Q== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id F13A117E0DE9; Tue, 14 Jul 2026 13:44:44 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com, Krzysztof Kozlowski Subject: [PATCH v2 13/46] dt-bindings: display: mediatek: Allow trigger-sources on relevant HW Date: Tue, 14 Jul 2026 13:43:41 +0200 Message-ID: <20260714114414.184512-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Most of the MediaTek Display Controller hardware sub-IPs need a specific (and reserved to them) MuteX trigger. Since now MuteX is a trigger source, allow specifying trigger sources in all of the display IPs that support one. Reviewed-by: Krzysztof Kozlowski Signed-off-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,dp.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,dpi.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,dsc.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,ethdr.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,od.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,padding.yaml | 3 +++ .../bindings/display/mediatek/mediatek,postmask.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,split.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,ufoe.yaml | 3 +++ .../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 3 +++ 20 files changed, 60 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aa= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.ya= ml index 4bbea72b292a..41d60a3d8007 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -55,6 +55,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: AAL Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,cc= orr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccor= r.yaml index 5c5068128d0c..e148aa57b1b9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml @@ -47,6 +47,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: CCORR Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,co= lor.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,colo= r.yaml index 5564f4063317..7c0985d0f9ea 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -57,6 +57,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: COLOR Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,di= ther.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dit= her.yaml index 891c95be15b9..85a1746965b9 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.ya= ml @@ -45,6 +45,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: DITHER Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml index 8f4bd9fb560b..0bb808874839 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml @@ -39,6 +39,9 @@ properties: power-domains: maxItems: 1 =20 + trigger-sources: + maxItems: 1 + interrupts: maxItems: 1 =20 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.ya= ml index eb4f276e8dc4..f5be6c1e4b0e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -109,6 +109,9 @@ properties: items: - const: dpi =20 + trigger-sources: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= c.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.ya= ml index c8b3e86943e4..4863db6aba6e 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml @@ -43,6 +43,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + mediatek,gce-client-reg: description: The register of client driver can be configured by gce with 4 argume= nts diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ds= i.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.ya= ml index b5cdfe0eaca4..a9793b274070 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml @@ -73,6 +73,9 @@ properties: items: - const: dphy =20 + trigger-sources: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,et= hdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethd= r.yaml index 98db47894eeb..89370690ee71 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml @@ -100,6 +100,9 @@ properties: - const: gfx_fe1_async - const: vdo_be_async =20 + trigger-sources: + maxItems: 1 + mediatek,gce-client-reg: $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ga= mma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamm= a.yaml index ec1054bb06d4..4d06085e6014 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml @@ -54,6 +54,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: GAMMA Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,me= rge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merg= e.yaml index 3798a25402d3..656df51335b5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -47,6 +47,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od= .yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml index 930c088a722a..c912ae2493c3 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -60,6 +60,9 @@ properties: - port@0 - port@1 =20 + trigger-sources: + maxItems: 1 + mediatek,gce-client-reg: $ref: /schemas/types.yaml#/definitions/phandle-array description: describes how to locate the GCE client register diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ov= l-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl= -2l.yaml index ac0d924a451b..326223b36112 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.ya= ml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.ya= ml @@ -40,6 +40,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: OVL-2L Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ov= l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.ya= ml index 4df5c7b410c6..dc200068d617 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -61,6 +61,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: OVL Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,pa= dding.yaml index 86787866ced0..9dac0319dd60 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y= aml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.y= aml @@ -34,6 +34,9 @@ properties: power-domains: maxItems: 1 =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: Padding's clocks diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,po= stmask.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,p= ostmask.yaml index fb6fe4742624..caef5194371f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.= yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,postmask.= yaml @@ -40,6 +40,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: POSTMASK Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rd= ma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.= yaml index d914c06640df..13deb7c87ee6 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -60,6 +60,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: RDMA Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,sp= lit.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,spli= t.yaml index 4b6ff546757e..7307a50fa30f 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -40,6 +40,9 @@ properties: Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. maxItems: 1 =20 + trigger-sources: + maxItems: 1 + mediatek,gce-client-reg: description: The register of display function block to be set by gce. There are 4= arguments, diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,uf= oe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.= yaml index 036a66ed42e7..31e0863dd815 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -39,6 +39,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: UFOe Clock diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wd= ma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.= yaml index c3ed867d058d..3e6b346baa11 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml @@ -45,6 +45,9 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for detail= s. =20 + trigger-sources: + maxItems: 1 + clocks: items: - description: WDMA Clock --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85CCD38E5D4; Tue, 14 Jul 2026 11:44:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029494; cv=none; b=iB3IxjWiMdPyMe2Mwh0f5gkndCABWvxxxVdMWlKwNxF4Mz9bXd1RzCYSkXw6pTEU3uwRfcIs3qzMxUSbNXzSLk0FIrT4b1fAGRnhQVxR0RyswT6vAPboGt/aHCbv6Zp/YvvJ+ILjQMYh1LQASIoLNunh8dj3lwU96jXHoJ8nsc0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029494; c=relaxed/simple; bh=ic5kCf3eig7EBX5BW1mJVoLUBYjv8x987nVuR3uAENg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CuHopG9SNtgtqB9YLnYDD7TM00XPKKJaRNQkzX+JzfFGj9Fwd8rtDUOdtqP8P8CXKiCgtAc9eV0QNfWfUA8bJqyTYQRT6ZFkKzrOmWPs5V7rif1ZqxObRydNV+Wxu7uggfIe0aZKvjRphvVRdVoQZ8ocbweGXW6bAXWtR46wtzo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=p66kdi1H; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="p66kdi1H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029487; bh=ic5kCf3eig7EBX5BW1mJVoLUBYjv8x987nVuR3uAENg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=p66kdi1HaDGJ3C5kKy+2iclvBXWP9JBvWNfQb6t252KOEXsrawIRETHDSGh/BihcN qkBwzvJ8fEvssSjAN2SCXLDdOt+7SHV4awTnGJ/760PzRzorYERleV08L+XQz6HBRg hpHgezzKm7Tj75FnsDoJgiFrVoX624lS0gEm0SUQiWrQfOsvLpgZ+bDxEbaCAZOAtW Z9/6IaoTk6F10AtO5BglD4069xYmc3ShaaJi0qBbb0sN/lyVN0EF6lxdbmKDqbJEUa yzHFkJXaXA83r223xKGYJnWDwFm01X1zYA0GflF3sc/L5GG9BD46S0kyqdZL16gDL8 ULWSCLlh+O6NA== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 2E88917E0E1C; Tue, 14 Jul 2026 13:44:46 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 14/46] drm/mediatek: Add support for MuteX trigger-sources parsing Date: Tue, 14 Jul 2026 13:43:42 +0200 Message-ID: <20260714114414.184512-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for getting the Mute-X trigger source ID from the devicetree of each component requiring one. In order to retain compatibility with older devicetrees that are not specifying one, add a hardcoded table of Mute-X IDs in the mtk_drm_legacy code, and inject all of the hardcoded identifiers during initialization in mtk_drm_drv if the MediaTek Mute-X node does not have #trigger-source-cells as this implies that the driver is surely dealing with an old devicetree. While at it, also migrate the mtk_disp_ovl_adaptor registration mechanism to mtk_drm_legacy and change its platform data to get a struct mtk_drm_private instead of mmsys_dev: this is done in order to get a handle to the MuteX node in OVL_ADAPTOR, which purpose is to get the legacy trigger IDs through, again, tables in mtk_drm_legacy. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 19 + drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 2 + .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 17 +- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 +- drivers/gpu/drm/mediatek/mtk_drm_legacy.c | 567 ++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_drm_legacy.h | 8 + 6 files changed, 621 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 8ba75da0bf2d..ee8d12dd9968 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -604,6 +604,21 @@ static void mtk_ddp_comp_clk_put(void *_clk) clk_put(clk); } =20 +int mtk_ddp_comp_get_mutex_trigger(struct device_node *node, unsigned int = index) +{ + struct fwnode_reference_args mutex_trigger; + int ret; + + ret =3D fwnode_property_get_reference_args(of_fwnode_handle(node), + "trigger-sources", + "#trigger-source-cells", + 0, index, &mutex_trigger); + if (ret < 0) + return ret; + + return mutex_trigger.args[0]; +} + static bool mtk_ddp_comp_is_backlight_comp(enum mtk_ddp_comp_type type) { return type =3D=3D MTK_DISP_BLS || type =3D=3D MTK_DISP_PWM; @@ -695,6 +710,10 @@ int mtk_ddp_comp_init(struct device *dev, struct devic= e_node *node, if (ret) return ret; =20 + ret =3D mtk_ddp_comp_get_mutex_trigger(node, 0); + if (ret >=3D 0) + comp->mtx_trig_id =3D ret; + /* If there's no external driver for this component, allocate and init no= w */ if (mtk_ddp_comp_is_internal_comp(type) || mtk_ddp_comp_is_backlight_comp= (type)) { ret =3D mtk_ddp_comp_init_internal_comp(dev, comp->dev); diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 76a2b649516d..5206445b7157 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -81,6 +81,7 @@ struct mtk_ddp_comp { struct device *dev; int irq; unsigned int id; + u8 mtx_trig_id; int encoder_index; const struct mtk_ddp_comp_funcs *funcs; =20 @@ -360,6 +361,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, str= uct device *dev); int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_drm_comp_list *hlist, unsigned int comp_id); +int mtk_ddp_comp_get_mutex_trigger(struct device_node *node, unsigned int = index); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, struct cmdq_client_reg *cmdq_reg, void __iomem *regs, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index c0af3e3b51d5..ed9a2e35ba8a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -20,6 +20,7 @@ #include "mtk_ddp_comp.h" #include "mtk_disp_drv.h" #include "mtk_drm_drv.h" +#include "mtk_drm_legacy.h" #include "mtk_ethdr.h" =20 #define MTK_OVL_ADAPTOR_RDMA_MAX_WIDTH 1920 @@ -68,6 +69,7 @@ struct ovl_adaptor_comp_match { struct mtk_disp_ovl_adaptor { struct device *ovl_adaptor_comp[OVL_ADAPTOR_ID_MAX]; struct device *mmsys_dev; + u8 mtx_trig_ids[OVL_ADAPTOR_ID_MAX]; bool children_bound; }; =20 @@ -534,7 +536,8 @@ static void ovl_adaptor_put_device(void *_dev) put_device(dev); } =20 -static int ovl_adaptor_comp_init(struct device *dev, struct component_matc= h **match) +static int ovl_adaptor_comp_init(struct device *dev, struct device_node *m= utex_node, + struct component_match **match) { struct mtk_disp_ovl_adaptor *priv =3D dev_get_drvdata(dev); struct device_node *parent; @@ -544,7 +547,9 @@ static int ovl_adaptor_comp_init(struct device *dev, st= ruct component_match **ma =20 for_each_child_of_node_scoped(parent, node) { enum mtk_ovl_adaptor_comp_type type; + enum mtk_ddp_comp_id ddp_type; int id, ret; + u8 mtx_id; =20 ret =3D ovl_adaptor_of_get_ddp_comp_type(node, &type); if (ret) @@ -563,6 +568,10 @@ static int ovl_adaptor_comp_init(struct device *dev, s= truct component_match **ma continue; } =20 + ddp_type =3D comp_matches[id].comp_id; + mtx_id =3D mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(ddp_type, + mutex_node); + comp_pdev =3D of_find_device_by_node(node); if (!comp_pdev) return -EPROBE_DEFER; @@ -573,6 +582,7 @@ static int ovl_adaptor_comp_init(struct device *dev, st= ruct component_match **ma return ret; =20 priv->ovl_adaptor_comp[id] =3D &comp_pdev->dev; + priv->mtx_trig_ids[id] =3D mtx_id; =20 drm_of_component_match_add(dev, match, component_compare_of, node); dev_dbg(dev, "Adding component match for %pOF\n", node); @@ -634,6 +644,7 @@ static const struct component_master_ops mtk_disp_ovl_a= daptor_master_ops =3D { =20 static int mtk_disp_ovl_adaptor_probe(struct platform_device *pdev) { + struct mtk_drm_private *drm_private =3D pdev->dev.platform_data; struct mtk_disp_ovl_adaptor *priv; struct device *dev =3D &pdev->dev; struct component_match *match =3D NULL; @@ -645,11 +656,11 @@ static int mtk_disp_ovl_adaptor_probe(struct platform= _device *pdev) =20 platform_set_drvdata(pdev, priv); =20 - ret =3D ovl_adaptor_comp_init(dev, &match); + ret =3D ovl_adaptor_comp_init(dev, drm_private->mutex_node, &match); if (ret < 0) return ret; =20 - priv->mmsys_dev =3D pdev->dev.platform_data; + priv->mmsys_dev =3D drm_private->mmsys_dev; =20 component_master_add_with_match(dev, &mtk_disp_ovl_adaptor_master_ops, ma= tch); =20 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 1396cbc65627..cdff5edd09da 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -409,11 +409,6 @@ static const struct drm_driver mtk_drm_driver =3D { .minor =3D DRIVER_MINOR, }; =20 -static int compare_dev(struct device *dev, void *data) -{ - return dev =3D=3D (struct device *)data; -} - static int mtk_drm_bind(struct device *dev) { struct mtk_drm_private *private =3D dev_get_drvdata(dev); @@ -856,7 +851,6 @@ static int mtk_drm_probe(struct platform_device *pdev) struct mtk_mmsys_driver_data *mtk_drm_data; struct device_node *node; struct component_match *match =3D NULL; - struct platform_device *ovl_adaptor; int ret; int i; =20 @@ -904,17 +898,6 @@ static int mtk_drm_probe(struct platform_device *pdev) if (!private->all_drm_private) return -ENOMEM; =20 - /* Bringup ovl_adaptor */ - if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) { - ovl_adaptor =3D platform_device_register_data(dev, "mediatek-disp-ovl-ad= aptor", - PLATFORM_DEVID_AUTO, - (void *)private->mmsys_dev, - sizeof(*private->mmsys_dev)); - mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &private->hlist, - DDP_COMPONENT_DRM_OVL_ADAPTOR); - component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev); - } - /* Iterate over sibling DISP function blocks */ for_each_child_of_node(phandle->parent, node) { enum mtk_ddp_comp_type comp_type; @@ -979,6 +962,17 @@ static int mtk_drm_probe(struct platform_device *pdev) goto err_node; } =20 + /* If mtk-mutex is not a trigger source, this is an old devicetree */ + if (!of_property_present(private->mutex_node, "#trigger-source-cells")) { + ret =3D mtk_drm_legacy_inject_mutex_trig_ids(&private->hlist, private->m= utex_node); + if (ret) + return ret; + } + + /* Bringup ovl_adaptor */ + if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) + mtk_drm_legacy_ovl_adaptor_probe(dev, private, &match); + pm_runtime_enable(dev); =20 platform_set_drvdata(pdev, private); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c b/drivers/gpu/drm/me= diatek/mtk_drm_legacy.c index 623e510de9ff..d6e3ab7e08ba 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c @@ -29,9 +29,224 @@ * added to this file. */ =20 +#include +#include + #include "mtk_drm_drv.h" #include "mtk_drm_legacy.h" =20 +#define MT2701_MUTEX_MOD_DISP_OVL 3 +#define MT2701_MUTEX_MOD_DISP_WDMA 6 +#define MT2701_MUTEX_MOD_DISP_COLOR 7 +#define MT2701_MUTEX_MOD_DISP_BLS 9 +#define MT2701_MUTEX_MOD_DISP_RDMA0 10 +#define MT2701_MUTEX_MOD_DISP_RDMA1 12 + +#define MT2712_MUTEX_MOD_DISP_PWM2 10 +#define MT2712_MUTEX_MOD_DISP_OVL0 11 +#define MT2712_MUTEX_MOD_DISP_OVL1 12 +#define MT2712_MUTEX_MOD_DISP_RDMA0 13 +#define MT2712_MUTEX_MOD_DISP_RDMA1 14 +#define MT2712_MUTEX_MOD_DISP_RDMA2 15 +#define MT2712_MUTEX_MOD_DISP_WDMA0 16 +#define MT2712_MUTEX_MOD_DISP_WDMA1 17 +#define MT2712_MUTEX_MOD_DISP_COLOR0 18 +#define MT2712_MUTEX_MOD_DISP_COLOR1 19 +#define MT2712_MUTEX_MOD_DISP_AAL0 20 +#define MT2712_MUTEX_MOD_DISP_UFOE 22 +#define MT2712_MUTEX_MOD_DISP_PWM0 23 +#define MT2712_MUTEX_MOD_DISP_PWM1 24 +#define MT2712_MUTEX_MOD_DISP_OD0 25 +#define MT2712_MUTEX_MOD2_DISP_AAL1 33 +#define MT2712_MUTEX_MOD2_DISP_OD1 34 + +#define MT6893_MUTEX_MOD_DISP_OVL0 0 +#define MT6893_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT6893_MUTEX_MOD_DISP_RDMA0 2 +#define MT6893_MUTEX_MOD_DISP_WDMA0 3 +#define MT6893_MUTEX_MOD_DISP_COLOR0 4 +#define MT6893_MUTEX_MOD_DISP_CCORR0 5 +#define MT6893_MUTEX_MOD_DISP_AAL0 6 +#define MT6893_MUTEX_MOD_DISP_GAMMA0 7 +#define MT6893_MUTEX_MOD_DISP_DITHER0 8 +#define MT6893_MUTEX_MOD_DISP_DSI0 9 +#define MT6893_MUTEX_MOD_DISP_PWM0 11 +#define MT6893_MUTEX_MOD_DISP_OVL1 12 +#define MT6893_MUTEX_MOD_DISP_OVL1_2L 13 +#define MT6893_MUTEX_MOD_DISP_RDMA1 14 +#define MT6893_MUTEX_MOD_DISP_WDMA1 15 +#define MT6893_MUTEX_MOD_DISP_COLOR1 16 +#define MT6893_MUTEX_MOD_DISP_AAL1 18 +#define MT6893_MUTEX_MOD_DISP_DITHER1 20 +#define MT6893_MUTEX_MOD_DISP_DSI1 21 +#define MT6893_MUTEX_MOD_DISP_OVL2 23 +#define MT6893_MUTEX_MOD_DISP_POSTMASK0 25 +#define MT6893_MUTEX_MOD_DISP_MERGE0 27 +#define MT6893_MUTEX_MOD_DISP_MERGE1 28 +#define MT6893_MUTEX_MOD_DISP_DSC0 29 +#define MT6893_MUTEX_MOD_DISP_DP 31 +#define MT6893_MUTEX_MOD_DISP_RDMA4 34 + +#define MT8167_MUTEX_MOD_DISP_PWM 1 +#define MT8167_MUTEX_MOD_DISP_OVL0 6 +#define MT8167_MUTEX_MOD_DISP_OVL1 7 +#define MT8167_MUTEX_MOD_DISP_RDMA0 8 +#define MT8167_MUTEX_MOD_DISP_RDMA1 9 +#define MT8167_MUTEX_MOD_DISP_WDMA0 10 +#define MT8167_MUTEX_MOD_DISP_CCORR 11 +#define MT8167_MUTEX_MOD_DISP_COLOR 12 +#define MT8167_MUTEX_MOD_DISP_AAL 13 +#define MT8167_MUTEX_MOD_DISP_GAMMA 14 +#define MT8167_MUTEX_MOD_DISP_DITHER 15 +#define MT8167_MUTEX_MOD_DISP_UFOE 16 + +#define MT8173_MUTEX_MOD_DISP_OVL0 11 +#define MT8173_MUTEX_MOD_DISP_OVL1 12 +#define MT8173_MUTEX_MOD_DISP_RDMA0 13 +#define MT8173_MUTEX_MOD_DISP_RDMA1 14 +#define MT8173_MUTEX_MOD_DISP_RDMA2 15 +#define MT8173_MUTEX_MOD_DISP_WDMA0 16 +#define MT8173_MUTEX_MOD_DISP_WDMA1 17 +#define MT8173_MUTEX_MOD_DISP_COLOR0 18 +#define MT8173_MUTEX_MOD_DISP_COLOR1 19 +#define MT8173_MUTEX_MOD_DISP_AAL 20 +#define MT8173_MUTEX_MOD_DISP_GAMMA 21 +#define MT8173_MUTEX_MOD_DISP_UFOE 22 +#define MT8173_MUTEX_MOD_DISP_PWM0 23 +#define MT8173_MUTEX_MOD_DISP_PWM1 24 +#define MT8173_MUTEX_MOD_DISP_OD 25 + +#define MT8183_MUTEX_MOD_DISP_RDMA0 0 +#define MT8183_MUTEX_MOD_DISP_RDMA1 1 +#define MT8183_MUTEX_MOD_DISP_OVL0 9 +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10 +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11 +#define MT8183_MUTEX_MOD_DISP_WDMA0 12 +#define MT8183_MUTEX_MOD_DISP_COLOR0 13 +#define MT8183_MUTEX_MOD_DISP_CCORR0 14 +#define MT8183_MUTEX_MOD_DISP_AAL0 15 +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16 +#define MT8183_MUTEX_MOD_DISP_DITHER0 17 + +#define MT8186_MUTEX_MOD_DISP_OVL0 0 +#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8186_MUTEX_MOD_DISP_RDMA0 2 +#define MT8186_MUTEX_MOD_DISP_COLOR0 4 +#define MT8186_MUTEX_MOD_DISP_CCORR0 5 +#define MT8186_MUTEX_MOD_DISP_AAL0 7 +#define MT8186_MUTEX_MOD_DISP_GAMMA0 8 +#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9 +#define MT8186_MUTEX_MOD_DISP_DITHER0 10 +#define MT8186_MUTEX_MOD_DISP_RDMA1 17 + +#define MT8188_MUTEX_MOD_DISP_OVL0 0 +#define MT8188_MUTEX_MOD_DISP_WDMA0 1 +#define MT8188_MUTEX_MOD_DISP_RDMA0 2 +#define MT8188_MUTEX_MOD_DISP_COLOR0 3 +#define MT8188_MUTEX_MOD_DISP_CCORR0 4 +#define MT8188_MUTEX_MOD_DISP_AAL0 5 +#define MT8188_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8188_MUTEX_MOD_DISP_DITHER0 7 +#define MT8188_MUTEX_MOD_DISP_DSI0 8 +#define MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8188_MUTEX_MOD_DISP_VPP_MERGE 20 +#define MT8188_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8188_MUTEX_MOD_DISP_POSTMASK0 24 +#define MT8188_MUTEX_MOD2_DISP_PWM0 33 + +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8188_MUTEX_MOD_DISP1_PADDING0 8 +#define MT8188_MUTEX_MOD_DISP1_PADDING1 9 +#define MT8188_MUTEX_MOD_DISP1_PADDING2 10 +#define MT8188_MUTEX_MOD_DISP1_PADDING3 11 +#define MT8188_MUTEX_MOD_DISP1_PADDING4 12 +#define MT8188_MUTEX_MOD_DISP1_PADDING5 13 +#define MT8188_MUTEX_MOD_DISP1_PADDING6 14 +#define MT8188_MUTEX_MOD_DISP1_PADDING7 15 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 20 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 21 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 22 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 23 +#define MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 24 +#define MT8188_MUTEX_MOD_DISP1_DISP_MIXER 30 +#define MT8188_MUTEX_MOD_DISP1_DPI1 38 +#define MT8188_MUTEX_MOD_DISP1_DP_INTF1 39 + +#define MT8192_MUTEX_MOD_DISP_OVL0 0 +#define MT8192_MUTEX_MOD_DISP_OVL0_2L 1 +#define MT8192_MUTEX_MOD_DISP_RDMA0 2 +#define MT8192_MUTEX_MOD_DISP_COLOR0 4 +#define MT8192_MUTEX_MOD_DISP_CCORR0 5 +#define MT8192_MUTEX_MOD_DISP_AAL0 6 +#define MT8192_MUTEX_MOD_DISP_GAMMA0 7 +#define MT8192_MUTEX_MOD_DISP_POSTMASK0 8 +#define MT8192_MUTEX_MOD_DISP_DITHER0 9 +#define MT8192_MUTEX_MOD_DISP_OVL2_2L 16 +#define MT8192_MUTEX_MOD_DISP_RDMA4 17 + +#define MT8195_MUTEX_MOD_DISP_OVL0 0 +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 +#define MT8195_MUTEX_MOD_DISP_AAL0 5 +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 +#define MT8195_MUTEX_MOD_DISP_DSI0 8 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8195_MUTEX_MOD_DISP_PWM0 27 + +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 0 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 1 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 2 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 3 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 4 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 5 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 6 +#define MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 7 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 8 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 9 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 10 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 11 +#define MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 12 +#define MT8195_MUTEX_MOD_DISP1_DISP_MIXER 18 +#define MT8195_MUTEX_MOD_DISP1_DPI0 25 +#define MT8195_MUTEX_MOD_DISP1_DPI1 26 +#define MT8195_MUTEX_MOD_DISP1_DP_INTF0 27 + +#define MT8365_MUTEX_MOD_DISP_OVL0 7 +#define MT8365_MUTEX_MOD_DISP_OVL0_2L 8 +#define MT8365_MUTEX_MOD_DISP_RDMA0 9 +#define MT8365_MUTEX_MOD_DISP_RDMA1 10 +#define MT8365_MUTEX_MOD_DISP_WDMA0 11 +#define MT8365_MUTEX_MOD_DISP_COLOR0 12 +#define MT8365_MUTEX_MOD_DISP_CCORR 13 +#define MT8365_MUTEX_MOD_DISP_AAL 14 +#define MT8365_MUTEX_MOD_DISP_GAMMA 15 +#define MT8365_MUTEX_MOD_DISP_DITHER 16 +#define MT8365_MUTEX_MOD_DISP_DSI0 17 +#define MT8365_MUTEX_MOD_DISP_PWM0 20 +#define MT8365_MUTEX_MOD_DISP_DPI0 22 + +struct mtk_drm_legacy_mtx_pairs { + struct mtk_drm_comp_definition comp; + u8 mtx_trig_id; +}; + +struct mtk_drm_legacy_mtx_data { + const struct mtk_drm_legacy_mtx_pairs *pairs; + u8 num_pairs; +}; + static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] =3D { { DDP_COMPONENT_OVL0 }, { DDP_COMPONENT_RDMA0 }, @@ -307,3 +522,355 @@ struct mtk_drm_path_definition mt8195_vdo1_legacy_pat= hs[MAX_CRTC] =3D { .len =3D ARRAY_SIZE(mt8195_mtk_ddp_ext), }, }; + +static const struct mtk_drm_legacy_mtx_pairs mt2701_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_BLS }, MT2701_MUTEX_MOD_DISP_BLS }, + { { DDP_COMPONENT_COLOR0 }, MT2701_MUTEX_MOD_DISP_COLOR }, + { { DDP_COMPONENT_OVL0 }, MT2701_MUTEX_MOD_DISP_OVL }, + { { DDP_COMPONENT_RDMA0 }, MT2701_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT2701_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_WDMA0 }, MT2701_MUTEX_MOD_DISP_WDMA }, +}; + +const struct mtk_drm_legacy_mtx_data mt2701_legacy_mtx_data =3D { + .pairs =3D mt2701_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt2701_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt2712_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT2712_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_AAL1 }, MT2712_MUTEX_MOD2_DISP_AAL1 }, + { { DDP_COMPONENT_COLOR0 }, MT2712_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_COLOR1 }, MT2712_MUTEX_MOD_DISP_COLOR1 }, + { { DDP_COMPONENT_OD0 }, MT2712_MUTEX_MOD_DISP_OD0 }, + { { DDP_COMPONENT_OD1 }, MT2712_MUTEX_MOD2_DISP_OD1 }, + { { DDP_COMPONENT_OVL0 }, MT2712_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL1 }, MT2712_MUTEX_MOD_DISP_OVL1 }, + { { DDP_COMPONENT_PWM0 }, MT2712_MUTEX_MOD_DISP_PWM0 }, + { { DDP_COMPONENT_PWM1 }, MT2712_MUTEX_MOD_DISP_PWM1 }, + { { DDP_COMPONENT_PWM2 }, MT2712_MUTEX_MOD_DISP_PWM2 }, + { { DDP_COMPONENT_RDMA0 }, MT2712_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT2712_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_RDMA2 }, MT2712_MUTEX_MOD_DISP_RDMA2 }, + { { DDP_COMPONENT_UFOE }, MT2712_MUTEX_MOD_DISP_UFOE }, + { { DDP_COMPONENT_WDMA0 }, MT2712_MUTEX_MOD_DISP_WDMA0 }, + { { DDP_COMPONENT_WDMA1 }, MT2712_MUTEX_MOD_DISP_WDMA1 }, +}; + +const struct mtk_drm_legacy_mtx_data mt2712_legacy_mtx_data =3D { + .pairs =3D mt2712_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt2712_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt6893_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT6893_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_AAL1 }, MT6893_MUTEX_MOD_DISP_AAL1 }, + { { DDP_COMPONENT_CCORR }, MT6893_MUTEX_MOD_DISP_CCORR0 }, + { { DDP_COMPONENT_COLOR0 }, MT6893_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_COLOR1 }, MT6893_MUTEX_MOD_DISP_COLOR1 }, + { { DDP_COMPONENT_DITHER0 }, MT6893_MUTEX_MOD_DISP_DITHER0 }, + { { DDP_COMPONENT_DITHER1 }, MT6893_MUTEX_MOD_DISP_DITHER1 }, + { { DDP_COMPONENT_DP_INTF0 }, MT6893_MUTEX_MOD_DISP_DP }, + { { DDP_COMPONENT_DSC0 }, MT6893_MUTEX_MOD_DISP_DSC0 }, + { { DDP_COMPONENT_DSI0 }, MT6893_MUTEX_MOD_DISP_DSI0 }, + { { DDP_COMPONENT_DSI1 }, MT6893_MUTEX_MOD_DISP_DSI1 }, + { { DDP_COMPONENT_GAMMA }, MT6893_MUTEX_MOD_DISP_GAMMA0 }, + { { DDP_COMPONENT_MERGE1 }, MT6893_MUTEX_MOD_DISP_MERGE1 }, + { { DDP_COMPONENT_OVL0 }, MT6893_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL1 }, MT6893_MUTEX_MOD_DISP_OVL1 }, + { { DDP_COMPONENT_OVL_2L0 }, MT6893_MUTEX_MOD_DISP_OVL0_2L }, + { { DDP_COMPONENT_OVL_2L1 }, MT6893_MUTEX_MOD_DISP_OVL1_2L }, + { { DDP_COMPONENT_OVL_2L2 }, MT6893_MUTEX_MOD_DISP_OVL2 }, + { { DDP_COMPONENT_POSTMASK0 }, MT6893_MUTEX_MOD_DISP_POSTMASK0 }, + { { DDP_COMPONENT_PWM0 }, MT6893_MUTEX_MOD_DISP_PWM0 }, + { { DDP_COMPONENT_RDMA0 }, MT6893_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT6893_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_RDMA4 }, MT6893_MUTEX_MOD_DISP_RDMA4 }, + { { DDP_COMPONENT_WDMA0 }, MT6893_MUTEX_MOD_DISP_WDMA0 }, + { { DDP_COMPONENT_WDMA1 }, MT6893_MUTEX_MOD_DISP_WDMA1 }, +}; + +const struct mtk_drm_legacy_mtx_data mt6893_legacy_mtx_data =3D { + .pairs =3D mt6893_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt6893_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8167_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT8167_MUTEX_MOD_DISP_AAL }, + { { DDP_COMPONENT_CCORR }, MT8167_MUTEX_MOD_DISP_CCORR }, + { { DDP_COMPONENT_COLOR0 }, MT8167_MUTEX_MOD_DISP_COLOR }, + { { DDP_COMPONENT_DITHER0 }, MT8167_MUTEX_MOD_DISP_DITHER }, + { { DDP_COMPONENT_GAMMA }, MT8167_MUTEX_MOD_DISP_GAMMA }, + { { DDP_COMPONENT_OVL0 }, MT8167_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL1 }, MT8167_MUTEX_MOD_DISP_OVL1 }, + { { DDP_COMPONENT_PWM0 }, MT8167_MUTEX_MOD_DISP_PWM }, + { { DDP_COMPONENT_RDMA0 }, MT8167_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT8167_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_UFOE }, MT8167_MUTEX_MOD_DISP_UFOE }, + { { DDP_COMPONENT_WDMA0 }, MT8167_MUTEX_MOD_DISP_WDMA0 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8167_legacy_mtx_data =3D { + .pairs =3D mt8167_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8167_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8173_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT8173_MUTEX_MOD_DISP_AAL }, + { { DDP_COMPONENT_COLOR0 }, MT8173_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_COLOR1 }, MT8173_MUTEX_MOD_DISP_COLOR1 }, + { { DDP_COMPONENT_GAMMA }, MT8173_MUTEX_MOD_DISP_GAMMA }, + { { DDP_COMPONENT_OD0 }, MT8173_MUTEX_MOD_DISP_OD }, + { { DDP_COMPONENT_OVL0 }, MT8173_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL1 }, MT8173_MUTEX_MOD_DISP_OVL1 }, + { { DDP_COMPONENT_PWM0 }, MT8173_MUTEX_MOD_DISP_PWM0 }, + { { DDP_COMPONENT_PWM1 }, MT8173_MUTEX_MOD_DISP_PWM1 }, + { { DDP_COMPONENT_RDMA0 }, MT8173_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT8173_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_RDMA2 }, MT8173_MUTEX_MOD_DISP_RDMA2 }, + { { DDP_COMPONENT_UFOE }, MT8173_MUTEX_MOD_DISP_UFOE }, + { { DDP_COMPONENT_WDMA0 }, MT8173_MUTEX_MOD_DISP_WDMA0 }, + { { DDP_COMPONENT_WDMA1 }, MT8173_MUTEX_MOD_DISP_WDMA1 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8173_legacy_mtx_data =3D { + .pairs =3D mt8173_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8173_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8183_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT8183_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_CCORR }, MT8183_MUTEX_MOD_DISP_CCORR0 }, + { { DDP_COMPONENT_COLOR0 }, MT8183_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_DITHER0 }, MT8183_MUTEX_MOD_DISP_DITHER0 }, + { { DDP_COMPONENT_GAMMA }, MT8183_MUTEX_MOD_DISP_GAMMA0 }, + { { DDP_COMPONENT_OVL0 }, MT8183_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL_2L0 }, MT8183_MUTEX_MOD_DISP_OVL0_2L }, + { { DDP_COMPONENT_OVL_2L1 }, MT8183_MUTEX_MOD_DISP_OVL1_2L }, + { { DDP_COMPONENT_RDMA0 }, MT8183_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT8183_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_WDMA0 }, MT8183_MUTEX_MOD_DISP_WDMA0 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8183_legacy_mtx_data =3D { + .pairs =3D mt8183_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8183_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8186_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT8186_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_CCORR }, MT8186_MUTEX_MOD_DISP_CCORR0 }, + { { DDP_COMPONENT_COLOR0 }, MT8186_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_DITHER0 }, MT8186_MUTEX_MOD_DISP_DITHER0 }, + { { DDP_COMPONENT_GAMMA }, MT8186_MUTEX_MOD_DISP_GAMMA0 }, + { { DDP_COMPONENT_OVL0 }, MT8186_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL_2L0 }, MT8186_MUTEX_MOD_DISP_OVL0_2L }, + { { DDP_COMPONENT_POSTMASK0 }, MT8186_MUTEX_MOD_DISP_POSTMASK0 }, + { { DDP_COMPONENT_RDMA0 }, MT8186_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT8186_MUTEX_MOD_DISP_RDMA1 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8186_legacy_mtx_data =3D { + .pairs =3D mt8186_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8186_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8188_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_OVL0 }, MT8188_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_WDMA0 }, MT8188_MUTEX_MOD_DISP_WDMA0 }, + { { DDP_COMPONENT_RDMA0 }, MT8188_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_COLOR0 }, MT8188_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_CCORR }, MT8188_MUTEX_MOD_DISP_CCORR0 }, + { { DDP_COMPONENT_AAL0 }, MT8188_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_GAMMA }, MT8188_MUTEX_MOD_DISP_GAMMA0 }, + { { DDP_COMPONENT_POSTMASK0 }, MT8188_MUTEX_MOD_DISP_POSTMASK0 }, + { { DDP_COMPONENT_DITHER0 }, MT8188_MUTEX_MOD_DISP_DITHER0 }, + { { DDP_COMPONENT_MERGE0 }, MT8188_MUTEX_MOD_DISP_VPP_MERGE }, + { { DDP_COMPONENT_DSC0 }, MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 }, + { { DDP_COMPONENT_DSI0 }, MT8188_MUTEX_MOD_DISP_DSI0 }, + { { DDP_COMPONENT_PWM0 }, MT8188_MUTEX_MOD2_DISP_PWM0 }, + { { DDP_COMPONENT_DP_INTF0 }, MT8188_MUTEX_MOD_DISP_DP_INTF0 }, + { { DDP_COMPONENT_DP_INTF1 }, MT8188_MUTEX_MOD_DISP1_DP_INTF1 }, + { { DDP_COMPONENT_DPI1 }, MT8188_MUTEX_MOD_DISP1_DPI1 }, + { { DDP_COMPONENT_ETHDR_MIXER }, MT8188_MUTEX_MOD_DISP1_DISP_MIXER }, + { { DDP_COMPONENT_MDP_RDMA0 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 }, + { { DDP_COMPONENT_MDP_RDMA1 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 }, + { { DDP_COMPONENT_MDP_RDMA2 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 }, + { { DDP_COMPONENT_MDP_RDMA3 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 }, + { { DDP_COMPONENT_MDP_RDMA4 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 }, + { { DDP_COMPONENT_MDP_RDMA5 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 }, + { { DDP_COMPONENT_MDP_RDMA6 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 }, + { { DDP_COMPONENT_MDP_RDMA7 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 }, + { { DDP_COMPONENT_PADDING0 }, MT8188_MUTEX_MOD_DISP1_PADDING0 }, + { { DDP_COMPONENT_PADDING1 }, MT8188_MUTEX_MOD_DISP1_PADDING1 }, + { { DDP_COMPONENT_PADDING2 }, MT8188_MUTEX_MOD_DISP1_PADDING2 }, + { { DDP_COMPONENT_PADDING3 }, MT8188_MUTEX_MOD_DISP1_PADDING3 }, + { { DDP_COMPONENT_PADDING4 }, MT8188_MUTEX_MOD_DISP1_PADDING4 }, + { { DDP_COMPONENT_PADDING5 }, MT8188_MUTEX_MOD_DISP1_PADDING5 }, + { { DDP_COMPONENT_PADDING6 }, MT8188_MUTEX_MOD_DISP1_PADDING6 }, + { { DDP_COMPONENT_PADDING7 }, MT8188_MUTEX_MOD_DISP1_PADDING7 }, + { { DDP_COMPONENT_MERGE1 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 }, + { { DDP_COMPONENT_MERGE2 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 }, + { { DDP_COMPONENT_MERGE3 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 }, + { { DDP_COMPONENT_MERGE4 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 }, + { { DDP_COMPONENT_MERGE5 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8188_legacy_mtx_data =3D { + .pairs =3D mt8188_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8188_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8192_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT8192_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_CCORR }, MT8192_MUTEX_MOD_DISP_CCORR0 }, + { { DDP_COMPONENT_COLOR0 }, MT8192_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_DITHER0 }, MT8192_MUTEX_MOD_DISP_DITHER0 }, + { { DDP_COMPONENT_GAMMA }, MT8192_MUTEX_MOD_DISP_GAMMA0 }, + { { DDP_COMPONENT_POSTMASK0 }, MT8192_MUTEX_MOD_DISP_POSTMASK0 }, + { { DDP_COMPONENT_OVL0 }, MT8192_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL_2L0 }, MT8192_MUTEX_MOD_DISP_OVL0_2L }, + { { DDP_COMPONENT_OVL_2L2 }, MT8192_MUTEX_MOD_DISP_OVL2_2L }, + { { DDP_COMPONENT_RDMA0 }, MT8192_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA4 }, MT8192_MUTEX_MOD_DISP_RDMA4 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8192_legacy_mtx_data =3D { + .pairs =3D mt8192_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8192_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8195_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_OVL0 }, MT8195_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_WDMA0 }, MT8195_MUTEX_MOD_DISP_WDMA0 }, + { { DDP_COMPONENT_RDMA0 }, MT8195_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_COLOR0 }, MT8195_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_CCORR }, MT8195_MUTEX_MOD_DISP_CCORR0 }, + { { DDP_COMPONENT_AAL0 }, MT8195_MUTEX_MOD_DISP_AAL0 }, + { { DDP_COMPONENT_GAMMA }, MT8195_MUTEX_MOD_DISP_GAMMA0 }, + { { DDP_COMPONENT_DITHER0 }, MT8195_MUTEX_MOD_DISP_DITHER0 }, + { { DDP_COMPONENT_MERGE0 }, MT8195_MUTEX_MOD_DISP_VPP_MERGE }, + { { DDP_COMPONENT_DSC0 }, MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 }, + { { DDP_COMPONENT_DSI0 }, MT8195_MUTEX_MOD_DISP_DSI0 }, + { { DDP_COMPONENT_PWM0 }, MT8195_MUTEX_MOD_DISP_PWM0 }, + { { DDP_COMPONENT_DP_INTF0 }, MT8195_MUTEX_MOD_DISP_DP_INTF0 }, + { { DDP_COMPONENT_MDP_RDMA0 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 }, + { { DDP_COMPONENT_MDP_RDMA1 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 }, + { { DDP_COMPONENT_MDP_RDMA2 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 }, + { { DDP_COMPONENT_MDP_RDMA3 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 }, + { { DDP_COMPONENT_MDP_RDMA4 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 }, + { { DDP_COMPONENT_MDP_RDMA5 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 }, + { { DDP_COMPONENT_MDP_RDMA6 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 }, + { { DDP_COMPONENT_MDP_RDMA7 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 }, + { { DDP_COMPONENT_MERGE1 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 }, + { { DDP_COMPONENT_MERGE2 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 }, + { { DDP_COMPONENT_MERGE3 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 }, + { { DDP_COMPONENT_MERGE4 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 }, + { { DDP_COMPONENT_ETHDR_MIXER }, MT8195_MUTEX_MOD_DISP1_DISP_MIXER }, + { { DDP_COMPONENT_MERGE5 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 }, + { { DDP_COMPONENT_DP_INTF1 }, MT8195_MUTEX_MOD_DISP1_DP_INTF0 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8195_legacy_mtx_data =3D { + .pairs =3D mt8195_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8195_legacy_mtx_trig_ids) +}; + +static const struct mtk_drm_legacy_mtx_pairs mt8365_legacy_mtx_trig_ids[] = =3D { + { { DDP_COMPONENT_AAL0 }, MT8365_MUTEX_MOD_DISP_AAL }, + { { DDP_COMPONENT_CCORR }, MT8365_MUTEX_MOD_DISP_CCORR }, + { { DDP_COMPONENT_COLOR0 }, MT8365_MUTEX_MOD_DISP_COLOR0 }, + { { DDP_COMPONENT_DITHER0 }, MT8365_MUTEX_MOD_DISP_DITHER }, + { { DDP_COMPONENT_DPI0 }, MT8365_MUTEX_MOD_DISP_DPI0 }, + { { DDP_COMPONENT_DSI0 }, MT8365_MUTEX_MOD_DISP_DSI0 }, + { { DDP_COMPONENT_GAMMA }, MT8365_MUTEX_MOD_DISP_GAMMA }, + { { DDP_COMPONENT_OVL0 }, MT8365_MUTEX_MOD_DISP_OVL0 }, + { { DDP_COMPONENT_OVL_2L0 }, MT8365_MUTEX_MOD_DISP_OVL0_2L }, + { { DDP_COMPONENT_PWM0 }, MT8365_MUTEX_MOD_DISP_PWM0 }, + { { DDP_COMPONENT_RDMA0 }, MT8365_MUTEX_MOD_DISP_RDMA0 }, + { { DDP_COMPONENT_RDMA1 }, MT8365_MUTEX_MOD_DISP_RDMA1 }, + { { DDP_COMPONENT_WDMA0 }, MT8365_MUTEX_MOD_DISP_WDMA0 }, +}; + +const struct mtk_drm_legacy_mtx_data mt8365_legacy_mtx_data =3D { + .pairs =3D mt8365_legacy_mtx_trig_ids, + .num_pairs =3D ARRAY_SIZE(mt8365_legacy_mtx_trig_ids) +}; + +static const struct of_device_id mtk_drm_legacy_mtk_mutex_match[] =3D { + { .compatible =3D "mediatek,mt2701-disp-mutex", .data =3D &mt2701_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt2712-disp-mutex", .data =3D &mt2712_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt6795-disp-mutex", .data =3D &mt8173_legacy_= mtx_data }, + { .compatible =3D "mediatek.mt6893-disp-mutex", .data =3D &mt6893_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8167-disp-mutex", .data =3D &mt8167_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8173-disp-mutex", .data =3D &mt8173_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8183-disp-mutex", .data =3D &mt8183_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8186-disp-mutex", .data =3D &mt8186_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8188-disp-mutex", .data =3D &mt8188_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8192-disp-mutex", .data =3D &mt8192_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8195-disp-mutex", .data =3D &mt8195_legacy_= mtx_data }, + { .compatible =3D "mediatek,mt8365-disp-mutex", .data =3D &mt8365_legacy_= mtx_data }, + { /* sentinel */ }, +}; + +int mtk_drm_legacy_inject_mutex_trig_ids(struct mtk_drm_comp_list *hlist, + struct device_node *mutex_node) +{ + struct mtk_drm_legacy_mtx_data *data; + const struct of_device_id *of_id; + struct mtk_ddp_comp *ddp_comp; + int i; + + of_id =3D of_match_node(mtk_drm_legacy_mtk_mutex_match, mutex_node); + if (!of_id) + return -ENODEV; + + data =3D (struct mtk_drm_legacy_mtx_data *)of_id->data; + + for (i =3D 0; i < data->num_pairs; i++) { + const struct mtk_drm_comp_definition *comp =3D &data->pairs[i].comp; + + hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp->type) + ddp_comp->mtx_trig_id =3D data->pairs[i].mtx_trig_id; + } + + return 0; +} + +u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_id ddp_t= ype, + struct device_node *mutex_node) +{ + struct mtk_drm_legacy_mtx_data *data; + const struct of_device_id *of_id; + int i; + + of_id =3D of_match_node(mtk_drm_legacy_mtk_mutex_match, mutex_node); + if (!of_id) + return 0; + + data =3D (struct mtk_drm_legacy_mtx_data *)of_id->data; + + for (i =3D 0; i < data->num_pairs; i++) { + const struct mtk_drm_comp_definition *comp =3D &data->pairs[i].comp; + + if (ddp_type !=3D comp->type) + continue; + + return data->pairs[i].mtx_trig_id; + } + + return 0; +} + +void mtk_drm_legacy_ovl_adaptor_probe(struct device *dev, struct mtk_drm_p= rivate *priv, + struct component_match **match) +{ + struct platform_device *ovl_adaptor; + + ovl_adaptor =3D platform_device_register_data(dev, "mediatek-disp-ovl-ada= ptor", + PLATFORM_DEVID_AUTO, + (void *)priv, sizeof(*priv)); + + mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &priv->hlist, DDP_COMPONENT_DR= M_OVL_ADAPTOR); + component_match_add(dev, match, component_compare_dev, &ovl_adaptor->dev); +} diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.h b/drivers/gpu/drm/me= diatek/mtk_drm_legacy.h index a87741ec0dcd..45bcf2674628 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_legacy.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.h @@ -25,4 +25,12 @@ extern struct mtk_drm_path_definition mt8192_legacy_path= s[]; extern struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[]; extern struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[]; =20 +int mtk_drm_legacy_inject_mutex_trig_ids(struct mtk_drm_comp_list *hlist, + struct device_node *mutex_node); +u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_id ddp_t= ype, + struct device_node *mutex_node); + +void mtk_drm_legacy_ovl_adaptor_probe(struct device *dev, struct mtk_drm_p= rivate *priv, + struct component_match **match); + #endif /* MTK_DRM_LEGACY_H */ --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6051A374169; Tue, 14 Jul 2026 11:44:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029493; cv=none; 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(Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id E381B17E07A2; Tue, 14 Jul 2026 13:44:47 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 15/46] drm/mediatek: ovl_adaptor: Add special MERGE component check Date: Tue, 14 Jul 2026 13:43:43 +0200 Message-ID: <20260714114414.184512-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On the legacy ovl_adaptor for MT8195 and MT8188, four MERGE IPs from VPPSYS are used, and those shall be exclusive to the OVL Adaptor driver. For this reason, add a branch in mtk_ovl_adaptor_is_comp_present() to check if the component that is being checked is MERGE and, if so, iterate through the list of component matches to understand if it is one of those that must be exclusive to OVL Adaptor. This resolves a corner case happening when mediatek-drm retries to probe after a probe deferral, where all MERGE components would get added to both "normal" and OVL Adaptor pipelines. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index ed9a2e35ba8a..bbf1d8ccda05 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -519,6 +519,17 @@ bool mtk_ovl_adaptor_is_comp_present(struct device_nod= e *node) if (type >=3D OVL_ADAPTOR_TYPE_NUM) return false; =20 + /* Check if this is one of the MERGE components used in OVL Adaptor */ + if (type =3D=3D OVL_ADAPTOR_TYPE_MERGE) { + int id =3D of_alias_get_id(node, private_comp_stem[type]); + + for (int i =3D OVL_ADAPTOR_MERGE0; i <=3D OVL_ADAPTOR_MERGE3; i++) + if (comp_matches[i].alias_id =3D=3D id) + return true; + + return false; + } + /* * In the context of mediatek-drm, ETHDR, MDP_RDMA and Padding are * used exclusively by OVL Adaptor: if this component is not one of --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 604C238F654; Tue, 14 Jul 2026 11:44:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029493; cv=none; b=fya7/E9f4p2zFFDym9G5JtCaZwREoafi8BwTrHGGBWuuKL7b++w/e+8z39T3j9Ok63FTz9jhpT2Tyhe1OexXWkSvmHnWbHlB8iXei2Dciv2DnBYTuGIdHKNLhG1Z8qhYSKd4UAfhQpnt0FtEdeA35vGbmV1UUb+mnnmO4nJ+Hg0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029493; c=relaxed/simple; bh=ydoTSNpvbYYrQu7+7L4wOkYZ6e235H5lyowps7msh+o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Hi1S2AHEzQRz3q6oKa4rr3zDw6Lw1ensNuyrjHt2k/7Q8RSIMZOA+KzgN3mZ12CbI2VoMOMcaPl6j03VlXqhsQgMcPnkiwf4Ch5sW3yUmQjfNKSRvpoVzTyzct84MFJdsftm4Y0ebnUp9ULkDY1HScA+uGywzGwXexGwRh+Mieo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=agqwkmL0; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="agqwkmL0" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029489; bh=ydoTSNpvbYYrQu7+7L4wOkYZ6e235H5lyowps7msh+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=agqwkmL0ZbtE/MF6tJ+RYet4e7DMhoyxhLJWbwJCrFR45hQOVv0jcvSD2PwPNglx7 FR6RNYivoo6sVQ9+RoAyo6UUPoD60l+bgufTlxv5nryf2pN6bWfRrqGFbFV3O80NQi wqzBkVBnX9OeXuCpuUThnqon8Koo2b5p5raJlu2ZnZlI25zJ6gULig42tYXIJV0zDY xsdByrT3pSA+X/VB8oWSSlnTwj84dXyUAVAzMbxnHMX+zR3HkKLnsvEQJiDnvA0x0A khQWg75rckOUjQ0Oke7UtGmYgrLMxstrgGHclRLiJGiBP5jzA75/PvFJIQsLvezbB0 KcHp4LHU6Fcvw== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id C848817E0E6C; Tue, 14 Jul 2026 13:44:48 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 16/46] drm/mediatek: mtk_hdmi_v2: Don't warn on RPM active during detach Date: Tue, 14 Jul 2026 13:43:44 +0200 Message-ID: <20260714114414.184512-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Runtime PM may be active during bridge .detach() and this happens especially at boot, when probe deferrals in the display controller driver happen. Even though it looks safe to assume that RPM has to be inactive at that time, this happens to be true only if the DDC was to be handled internally (like before .hpd_{en,dis}able() existed). At this point in time, this driver uses HPD callbacks, and for HPD to actually work it is necessary to raise the RPM refcount to wake up the entire HDMI IP: since it's not granted that the HPD or other children of the HDMI node are disabled during the display controller probe sequence, the WARN at bridge .detach() time may trigger (and will do that when mediatek-drm defers), unnecessarily bloating the kernel log, as the RPM refcount will be decreased anyway when removing the driver. This is why the WARN(pm_runtime_active()) check during detach is simply a development stage leftover: remove it! Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_hdmi_v2.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c b/drivers/gpu/drm/media= tek/mtk_hdmi_v2.c index d9316d30fd5f..b4c09a70c427 100644 --- a/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_v2.c @@ -995,8 +995,6 @@ static void mtk_hdmi_v2_bridge_detach(struct drm_bridge= *bridge) { struct mtk_hdmi *hdmi =3D hdmi_ctx_from_bridge(bridge); =20 - WARN_ON(pm_runtime_active(hdmi->dev)); - /* The controller is already powered off, just disable irq here */ disable_irq(hdmi->irq); } --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4718C394498; Tue, 14 Jul 2026 11:44:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029497; cv=none; b=SluJe4UCKTF80J0m7hZn6Ujj55iM1yQnL1VjuHZvVV38gDiX4Ge/fNLbDXdobCT6uBi8Fhnv1Y8X1Q4H9hcA3Zk8MDV1LgRLrJ8WfKk+yUUzPH54c7v19lZeIjwrLko4Tl3UkKGnLxDduCnNrcCuWAZKuzkfVOzeoHIUF3Ws2Vo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029497; c=relaxed/simple; bh=KjoGSvmkC2txuD4NLVgZH41P9WDeEoHtgJU+38VDoBc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d2cLjysrqZTUnON1Z44ZO8EqaMdbMwnsDJGpPOhCoWpOTjStmyE2xP6w//5pYzBk6WJq1ql97vpAM4f+rkdibVsP7R7fL7dkm9seigeGY/sD1N+Ct6gvSwRcusPVoEI19UdXT0Pfobi8J6Q0yixr28PbKZxyjcE3H+T9r68pBUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=DLemDdEm; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="DLemDdEm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029491; bh=KjoGSvmkC2txuD4NLVgZH41P9WDeEoHtgJU+38VDoBc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DLemDdEmOZXhsKTCGZ5U5N4fOhBPaqI5DmbTT8mF5BozUVdzgaYXPaU+U0VvjqUaO cpxQTwukfYbcPoXqdBi3PDAzwamUrCvhy6tDmRBiJvyg1tmQGEMYwOqPaDBrR0s4qH ujImTyLOmwKVtpY++TZcvqOYxwQRxp3R8aJm6ryysjFeVMggpUPt7MmlgR5cmXWifY SOltfP0U5db96Kmd80xataVa1qb+dGZ04RsJFzpyg75SlWGKJdJ5QRg2MAefzSS3hu uuh30oNIydNMdqxCMWN98SH2t2aj7LSKBoEC6pbFZ+gZwfCPIhf5/T7x+aKH3Ub87M IaKZRDDLkCDUQ== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id AA24817E0FC9; Tue, 14 Jul 2026 13:44:49 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 17/46] drm/mediatek: Add support for hardware multi-stage layers Date: Tue, 14 Jul 2026 13:43:45 +0200 Message-ID: <20260714114414.184512-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for newer, more complex, display controllers like the ones found in the MediaTek Kompanio Ultra and Genio Pro 5100 (MT8196/MT8894), add support for multi-stage layers as in newer hardware, there is a special strategy using multiple hardware components of one (or multiple) display controller(s) to form one single layer. Multi-stage layers are one more step towards extra flexibility of the Display Subsystem, making it possible to change capabilities of Display Controller Pipelines depending on the final application of a board: for example, one board may choose to use fewer layers per pipeline to achieve more pipelines (more concurrent outputs), or more layers to achieve less, but more capable (as in offloading and in achievable bandwidth) concurrent outputs. This currently adds boilerplate to support this hardware, but does not yet implement the IP-specific support for MT8196/8894, which will be done after all preparation is done. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 304 ++++++++++++------ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 15 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 12 +- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 +- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 9 +- drivers/gpu/drm/mediatek/mtk_disp_wdma.c | 2 +- 7 files changed, 246 insertions(+), 110 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 3eab78a72b8b..28c0269c3424 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -28,12 +29,24 @@ #include "mtk_drm_drv.h" #include "mtk_plane.h" =20 +/* + * struct mtk_crtc_hw_layer - MediaTek specific layer structure + * @plane: DRM Plane + * @layer_stages: HW Components layer stage indices to form one full la= yer/plane + * @layer_stages_nr: Number of layer stages in array + */ +struct mtk_crtc_hw_layer { + struct drm_plane plane; + u8 *layer_stages; + u8 layer_stages_nr; +}; + /* * struct mtk_crtc - MediaTek specific crtc structure. * @base: crtc object. * @enabled: records whether crtc_enable succeeded - * @planes: array of 4 drm_plane structures, one for each overlay plane - * @pending_planes: whether any plane has pending changes to be applied + * @hwlayers: Array of mtk_crtc_hw_layer structures, one for each o= verlay plane + * @hwlayer_nr: Number of hwlayers * @mmsys_dev: pointer to the mmsys device for configuration registers * @mutex: handle to one of the ten disp_mutex streams * @ddp_comp_nr: number of components in ddp_comp @@ -48,8 +61,8 @@ struct mtk_crtc { bool pending_needs_vblank; struct drm_pending_vblank_event *event; =20 - struct drm_plane *planes; - unsigned int layer_nr; + struct mtk_crtc_hw_layer *hwlayers; + unsigned int hwlayer_nr; bool pending_planes; bool pending_async_planes; =20 @@ -255,29 +268,6 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *= mtk_crtc) mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]); } =20 -static -struct mtk_ddp_comp *mtk_ddp_comp_for_plane(struct drm_crtc *crtc, - struct drm_plane *plane, - unsigned int *local_layer) -{ - struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp; - int i, count =3D 0; - unsigned int local_index =3D plane - mtk_crtc->planes; - - for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { - comp =3D mtk_crtc->ddp_comp[i]; - if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) { - *local_layer =3D local_index - count; - return comp; - } - count +=3D mtk_ddp_comp_layer_nr(comp); - } - - WARN(1, "Failed to find component for plane %d\n", plane->index); - return NULL; -} - #if IS_REACHABLE(CONFIG_MTK_CMDQ) static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg) { @@ -304,8 +294,8 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *m= ssg) state->pending_config =3D false; =20 if (mtk_crtc->pending_planes) { - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; =20 plane_state =3D to_mtk_plane_state(plane->state); @@ -316,8 +306,8 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *m= ssg) } =20 if (mtk_crtc->pending_async_planes) { - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; =20 plane_state =3D to_mtk_plane_state(plane->state); @@ -341,6 +331,21 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *= mssg) } #endif =20 +static void mtk_crtc_config_layer(struct mtk_crtc *mtk_crtc, + struct mtk_plane_state *plane_state, + int layer_num, struct cmdq_pkt *cmdq_pkt) +{ + u8 *layer_stages =3D mtk_crtc->hwlayers[layer_num].layer_stages; + u8 i =3D 0; + + do { + mtk_ddp_comp_layer_config(mtk_crtc->ddp_comp[layer_stages[i]], + layer_num, plane_state, cmdq_pkt); + } while (++i < mtk_crtc->hwlayers[layer_num].layer_stages_nr); + + return; +} + static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc) { struct drm_crtc *crtc =3D &mtk_crtc->base; @@ -437,20 +442,16 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_= crtc) } =20 /* Initially configure all planes */ - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; - struct mtk_ddp_comp *comp; - unsigned int local_layer; =20 plane_state =3D to_mtk_plane_state(plane->state); =20 /* should not enable layer before crtc enabled */ plane_state->pending.enable =3D false; - comp =3D mtk_ddp_comp_for_plane(crtc, plane, &local_layer); - if (comp) - mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, NULL); + + mtk_crtc_config_layer(mtk_crtc, plane_state, i, NULL); } =20 return 0; @@ -512,7 +513,6 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, struct mtk_crtc_state *state =3D to_mtk_crtc_state(mtk_crtc->base.state); struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; unsigned int i; - unsigned int local_layer; =20 /* * TODO: instead of updating the registers here, we should prepare @@ -530,8 +530,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, } =20 if (mtk_crtc->pending_planes) { - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; =20 plane_state =3D to_mtk_plane_state(plane->state); @@ -539,12 +539,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, if (!plane_state->pending.config) continue; =20 - comp =3D mtk_ddp_comp_for_plane(crtc, plane, &local_layer); + mtk_crtc_config_layer(mtk_crtc, plane_state, i, cmdq_handle); =20 - if (comp) - mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, - cmdq_handle); if (!cmdq_handle) plane_state->pending.config =3D false; } @@ -554,8 +550,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, } =20 if (mtk_crtc->pending_async_planes) { - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; =20 plane_state =3D to_mtk_plane_state(plane->state); @@ -563,12 +559,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, if (!plane_state->pending.async_config) continue; =20 - comp =3D mtk_ddp_comp_for_plane(crtc, plane, &local_layer); + mtk_crtc_config_layer(mtk_crtc, plane_state, i, cmdq_handle); =20 - if (comp) - mtk_ddp_comp_layer_config(comp, local_layer, - plane_state, - cmdq_handle); if (!cmdq_handle) plane_state->pending.async_config =3D false; } @@ -598,8 +590,8 @@ static void mtk_crtc_update_config(struct mtk_crtc *mtk= _crtc, bool needs_vblank) if (needs_vblank) mtk_crtc->pending_needs_vblank =3D true; =20 - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; =20 plane_state =3D to_mtk_plane_state(plane->state); @@ -748,12 +740,19 @@ static void mtk_crtc_update_output(struct drm_crtc *c= rtc, int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane, struct mtk_plane_state *state) { - unsigned int local_layer; - struct mtk_ddp_comp *comp; + struct mtk_crtc_hw_layer *hwlayer =3D container_of(plane, struct mtk_crtc= _hw_layer, plane); + struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); + u8 *layer_stages =3D hwlayer->layer_stages; + int i, ret; + + for (i =3D 0; i < hwlayer->layer_stages_nr; i++) { + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[layer_stages[i]]; + + ret =3D mtk_ddp_comp_layer_check(comp, 0, state); + if (ret) + return ret; + } =20 - comp =3D mtk_ddp_comp_for_plane(crtc, plane, &local_layer); - if (comp) - return mtk_ddp_comp_layer_check(comp, local_layer, state); return 0; } =20 @@ -772,8 +771,8 @@ void mtk_crtc_plane_disable(struct drm_crtc *crtc, stru= ct drm_plane *plane) return; =20 /* set pending plane state to disabled */ - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *mtk_plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *mtk_plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *mtk_plane_state =3D to_mtk_plane_state(mtk_plane= ->state); =20 if (mtk_plane->index =3D=3D plane->index) { @@ -842,8 +841,8 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *cr= tc, return; =20 /* Set all pending plane state to disabled */ - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - struct drm_plane *plane =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + struct drm_plane *plane =3D &mtk_crtc->hwlayers[i].plane; struct mtk_plane_state *plane_state; =20 plane_state =3D to_mtk_plane_state(plane->state); @@ -937,11 +936,11 @@ static int mtk_crtc_init(struct drm_device *drm, stru= ct mtk_crtc *mtk_crtc, struct drm_plane *cursor =3D NULL; int i, ret; =20 - for (i =3D 0; i < mtk_crtc->layer_nr; i++) { - if (mtk_crtc->planes[i].type =3D=3D DRM_PLANE_TYPE_PRIMARY) - primary =3D &mtk_crtc->planes[i]; - else if (mtk_crtc->planes[i].type =3D=3D DRM_PLANE_TYPE_CURSOR) - cursor =3D &mtk_crtc->planes[i]; + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + if (mtk_crtc->hwlayers[i].plane.type =3D=3D DRM_PLANE_TYPE_PRIMARY) + primary =3D &mtk_crtc->hwlayers[i].plane; + else if (mtk_crtc->hwlayers[i].plane.type =3D=3D DRM_PLANE_TYPE_CURSOR) + cursor =3D &mtk_crtc->hwlayers[i].plane; } =20 ret =3D drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor, @@ -958,23 +957,6 @@ static int mtk_crtc_init(struct drm_device *drm, struc= t mtk_crtc *mtk_crtc, return ret; } =20 -static int mtk_crtc_num_comp_planes(struct mtk_crtc *mtk_crtc, int comp_id= x) -{ - struct mtk_ddp_comp *comp; - - if (comp_idx > 1) - return 0; - - comp =3D mtk_crtc->ddp_comp[comp_idx]; - if (!comp->funcs) - return 0; - - if (comp_idx =3D=3D 1 && !comp->funcs->bgclr_in_on) - return 0; - - return mtk_ddp_comp_layer_nr(comp); -} - static inline enum drm_plane_type mtk_crtc_plane_type(unsigned int plane_idx, unsigned int num_planes) @@ -992,15 +974,15 @@ static int mtk_crtc_init_comp_planes(struct drm_devic= e *drm_dev, struct mtk_crtc *mtk_crtc, int comp_idx, int pipe) { - int num_planes =3D mtk_crtc_num_comp_planes(mtk_crtc, comp_idx); struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[comp_idx]; + unsigned int num_planes =3D mtk_ddp_comp_layer_nr(comp, comp_idx); int i, ret; =20 for (i =3D 0; i < num_planes; i++) { - ret =3D mtk_plane_init(drm_dev, - &mtk_crtc->planes[mtk_crtc->layer_nr], - BIT(pipe), - mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes), + struct mtk_crtc_hw_layer *hwlayer =3D &mtk_crtc->hwlayers[mtk_crtc->hwla= yer_nr]; + + ret =3D mtk_plane_init(drm_dev, &hwlayer->plane, BIT(pipe), + mtk_crtc_plane_type(mtk_crtc->hwlayer_nr, num_planes), mtk_ddp_comp_supported_rotations(comp), mtk_ddp_comp_get_blend_modes(comp), mtk_ddp_comp_get_formats(comp), @@ -1009,7 +991,98 @@ static int mtk_crtc_init_comp_planes(struct drm_devic= e *drm_dev, if (ret) return ret; =20 - mtk_crtc->layer_nr++; + hwlayer->layer_stages[hwlayer->layer_stages_nr] =3D comp_idx; + hwlayer->layer_stages_nr++; + + mtk_crtc->hwlayer_nr++; + } + return 0; +} + +static struct mtk_crtc_hw_layer +*mtk_crtc_find_hwlayer_with_comp(struct mtk_crtc *mtk_crtc, int comp) +{ + struct mtk_crtc_hw_layer *hwlayer; + int i, j; + + for (i =3D 0; i < mtk_crtc->hwlayer_nr; i++) { + hwlayer =3D &mtk_crtc->hwlayers[i]; + + for (j =3D 0; j < hwlayer->layer_stages_nr; j++) { + if (hwlayer->layer_stages[j] =3D=3D comp) + return hwlayer; + } + } + + return NULL; +} + +static int mtk_crtc_init_layer_stages(struct mtk_crtc *mtk_crtc) +{ + unsigned int prev_master_layer_component =3D UINT_MAX; + unsigned int master_layer_component =3D 0; + unsigned int comp_idx; + + for (comp_idx =3D 0; comp_idx < mtk_crtc->ddp_comp_nr; comp_idx++) { + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[comp_idx]; + struct mtk_crtc_hw_layer *hwlayer =3D NULL; + + /* + * A hardware IP represented as a component with layer_nr > 0 + * is the master (and also the first layer stage), which may + * then be composed of other multiple hardware-configurable + * layer stages that are directly connected to it. + * + * Only quirk here is that, in some cases, some layer stages + * may be connected together and hence not directly connected + * to the master: this corner case is not getting a perfectly + * accurate representation in the following code, as it treats + * all of the additional layer stages as if they are directly + * connected to the master. + * That doesn't matter, because any special configuration for + * this corner case is handled in the .connect handler of each + * specific component driver. + * + * For example, this is a multi-component layer stage layout: + * FRAME_IN -> _____ LAYER_MASTER ______ + * / | | \ -> BLEND -> NEXT + * HW_STG1 HW_STG2 HW_STG3 HW_STGx HW HWIP + * + * And following, another one that gets handled (to simplify the + * code) anyway like the first: + * FRAME_IN -> LAYER_MASTER -> HW_STG1 -> HW_STG(x) -> NEXT HWIP + * + * For the moment, this also supposes that a component cannot be + * both primary and secondary (so if it has layer_nr, stage_nr + * will not be evaluated for such component). + */ + if (mtk_ddp_comp_layer_nr(comp, comp_idx)) { + master_layer_component =3D comp_idx; + continue; + } + + /* If this component doesn't provide any stages, keep searching */ + if (!mtk_ddp_comp_stage_nr(comp)) + continue; + + /* + * If the index of the master layer component changed, find it + * in the stack of registered layer components + */ + if (master_layer_component !=3D prev_master_layer_component) { + hwlayer =3D mtk_crtc_find_hwlayer_with_comp(mtk_crtc, master_layer_comp= onent); + if (!hwlayer) { + drm_err(mtk_crtc->base.dev, + "Could not find layer master for %d!\n", + master_layer_component); + continue; + } + prev_master_layer_component =3D master_layer_component; + } + + /* Add the newly found layer stage to the correct layer master */ + hwlayer->layer_stages[hwlayer->layer_stages_nr] =3D comp_idx; + hwlayer->layer_stages_nr++; } return 0; } @@ -1039,6 +1112,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, struct mtk_ddp_comp *dma_comp; struct mtk_crtc *mtk_crtc; unsigned int num_comp_planes =3D 0; + unsigned int max_comp_stages =3D 0; int ret; int i, j; bool has_ctm =3D false; @@ -1121,20 +1195,54 @@ int mtk_crtc_create(struct drm_device *drm_dev, &mtk_crtc->base); } =20 - for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) - num_comp_planes +=3D mtk_crtc_num_comp_planes(mtk_crtc, i); + for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[i]; + + num_comp_planes +=3D mtk_ddp_comp_layer_nr(comp, 0); + max_comp_stages =3D MAX(mtk_ddp_comp_stage_nr(comp), max_comp_stages); + } =20 - mtk_crtc->planes =3D devm_kcalloc(dev, num_comp_planes, - sizeof(struct drm_plane), GFP_KERNEL); - if (!mtk_crtc->planes) + /* + * On the older and/or simpler display controllers, each layer is single + * stage, while newer ones are more complex and may have multiple stages + * to form one full layer. + * + * In both cases, anyway, in order to form a complete layer for plane, + * there will always be at least one layer stage, so the maximum number + * of stages is always (1 + max_comp_stages): for this reason, just add 1. + */ + max_comp_stages++; + + mtk_crtc->hwlayers =3D devm_kcalloc(dev, num_comp_planes, + sizeof(*mtk_crtc->hwlayers), + GFP_KERNEL); + if (!mtk_crtc->hwlayers) return -ENOMEM; =20 + for (i =3D 0; i < num_comp_planes; i++) { + struct mtk_crtc_hw_layer *comp_plane =3D &mtk_crtc->hwlayers[i]; + comp_plane->layer_stages =3D devm_kcalloc(dev, max_comp_stages, + sizeof(*comp_plane->layer_stages), + GFP_KERNEL); + if (!comp_plane->layer_stages) + return -ENOMEM; + } + for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { ret =3D mtk_crtc_init_comp_planes(drm_dev, mtk_crtc, i, crtc_i); if (ret) return ret; } =20 + /* Initialize multi-stage only if present */ + if (max_comp_stages > 1) { + ret =3D mtk_crtc_init_layer_stages(mtk_crtc); + if (ret) + return ret; + } + dev_dbg(dev, "Found %u layers composed by maximum of %u stage(s) each.\n", + mtk_crtc->hwlayer_nr, max_comp_stages); + /* * Default to use the first component as the dma dev. * In the case of ovl_adaptor sub driver, it needs to use the diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index 5206445b7157..a7ed46a95037 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -50,7 +50,8 @@ struct mtk_ddp_comp_funcs { void (*enable_vblank)(struct device *dev); void (*disable_vblank)(struct device *dev); unsigned int (*supported_rotations)(struct device *dev); - unsigned int (*layer_nr)(struct device *dev); + unsigned int (*layer_nr)(struct device *dev, int pipeline_index); + unsigned int (*layerstage_nr)(struct device *dev); int (*layer_check)(struct device *dev, unsigned int idx, struct mtk_plane_state *state); @@ -196,10 +197,18 @@ unsigned int mtk_ddp_comp_supported_rotations(struct = mtk_ddp_comp *comp) return DRM_MODE_ROTATE_0; } =20 -static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp) +static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp= , int pipeline_idx) { if (comp->funcs && comp->funcs->layer_nr) - return comp->funcs->layer_nr(comp->dev); + return comp->funcs->layer_nr(comp->dev, pipeline_idx); + + return 0; +} + +static inline unsigned int mtk_ddp_comp_stage_nr(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->layerstage_nr) + return comp->funcs->layerstage_nr(comp->dev); =20 return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index e0c30c6c7cc8..7706d95b3be8 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2020 MediaTek Inc. + * Copyright (c) 2020-2025 MediaTek Inc. + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #ifndef _MTK_DISP_DRV_H_ @@ -98,7 +100,7 @@ int mtk_ovl_layer_check(struct device *dev, unsigned int= idx, void mtk_ovl_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); -unsigned int mtk_ovl_layer_nr(struct device *dev); +unsigned int mtk_ovl_layer_nr(struct device *dev, int pipeline_index); void mtk_ovl_layer_on(struct device *dev, unsigned int idx, struct cmdq_pkt *cmdq_pkt); void mtk_ovl_layer_off(struct device *dev, unsigned int idx, @@ -141,7 +143,7 @@ void mtk_ovl_adaptor_enable_vblank(struct device *dev); void mtk_ovl_adaptor_disable_vblank(struct device *dev); void mtk_ovl_adaptor_start(struct device *dev); void mtk_ovl_adaptor_stop(struct device *dev); -unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev); +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev, int pipeline_ind= ex); struct device *mtk_ovl_adaptor_dma_dev_get(struct device *dev); u32 mtk_ovl_adaptor_get_blend_modes(struct device *dev); const u32 *mtk_ovl_adaptor_get_formats(struct device *dev); @@ -155,7 +157,7 @@ void mtk_rdma_clk_disable(struct device *dev); void mtk_rdma_config(struct device *dev, unsigned int width, unsigned int height, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); -unsigned int mtk_rdma_layer_nr(struct device *dev); +unsigned int mtk_rdma_layer_nr(struct device *dev, int pipeline_index); void mtk_rdma_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); @@ -186,7 +188,7 @@ void mtk_wdma_clk_disable(struct device *dev); void mtk_wdma_config(struct device *dev, unsigned int width, unsigned int height, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); -unsigned int mtk_wdma_layer_nr(struct device *dev); +unsigned int mtk_wdma_layer_nr(struct device *dev, int pipeline_index); void mtk_wdma_layer_config(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/medi= atek/mtk_disp_ovl.c index 8ef174987cb8..2bddabd11eab 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c @@ -347,10 +347,20 @@ void mtk_ovl_config(struct device *dev, unsigned int = w, mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_RST); } =20 -unsigned int mtk_ovl_layer_nr(struct device *dev) +unsigned int mtk_ovl_layer_nr(struct device *dev, int pipeline_index) { struct mtk_disp_ovl *ovl =3D dev_get_drvdata(dev); =20 + /* + * Only the first OVL in a display pipeline can form layers, and it + * must be either: + * - The first HW component in the pipeline; or + * - The second HW component in the pipeline, taking its input from + * a ReadDMA (RDMA) output. + */ + if (pipeline_index > 1) + return 0; + return ovl->data->layer_nr; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index bbf1d8ccda05..78bc3bee0794 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -360,7 +360,7 @@ enum drm_mode_status mtk_ovl_adaptor_mode_valid(struct = device *dev, return MODE_OK; } =20 -unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev) +unsigned int mtk_ovl_adaptor_layer_nr(struct device *dev, int pipeline_ind= ex) { return MTK_OVL_ADAPTOR_LAYER_NUM; } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/med= iatek/mtk_disp_rdma.c index c9d41d75e7f2..ead1c5a1e861 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -250,8 +250,15 @@ static unsigned int rdma_fmt_convert(struct mtk_disp_r= dma *rdma, } } =20 -unsigned int mtk_rdma_layer_nr(struct device *dev) +unsigned int mtk_rdma_layer_nr(struct device *dev, int pipeline_index) { + /* + * ReadDMA may participate in forming a layer only if it is the first + * component in a pipeline, usually passing data to a DispHW Overlay (OVL) + */ + if (pipeline_index > 0) + return 0; + return 1; } =20 diff --git a/drivers/gpu/drm/mediatek/mtk_disp_wdma.c b/drivers/gpu/drm/med= iatek/mtk_disp_wdma.c index 7c3df4c1445d..cf676f0e2d19 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_wdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_wdma.c @@ -264,7 +264,7 @@ static u32 wdma_fmt_convert(unsigned int fmt) } } =20 -unsigned int mtk_wdma_layer_nr(struct device *dev) +unsigned int mtk_wdma_layer_nr(struct device *dev, int pipeline_index) { return 1; } --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0462539B947; Tue, 14 Jul 2026 11:44:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029496; cv=none; b=LjONvXD7d3V8Q4KsgC1642Jlmo1MvRlgwTkZXrFNxl7T32w8t7SoZgQ0Z237ugHid9omBMmSdn72FIM3OZ4Z4FonkRAXNLoHarq13XPnietZXTNTdgvZ7ZA7fML5UAUuz9mZuOXhN7NC2QEiyPy3x4FegWV+eYxxfHgW7vC6iZw= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029492; bh=OmKruBuMwOuM/jqTHcrOt10988D6GNY5qNqd/zM9TCI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XQ5w0jngNb6D1U5uNMeKYsXPWUjUWjb4vJjC740GFMQ17Mw1vGctmrs4+ctsBvwXE A4RECSeal47P84Z6MSxKjenDeTaRm8uYTis1kznDHkUn2wIFGv9+iy95sogiTtzFKT t+xHVJ+0ca1MbafoKFkCUXfP6RWFjAp9X+Plz8lCBtfyZe8rXW0y0c2sTOzvGctI6G uWBGtVzOvibucycFutQIUJ2dh9nGiuMklFTnKombycKUWR66VD0Vch1FWCOzCLCy21 aCDhcxFCJnHBq9HrD5yQotJUQwLskJmFyIRGR5EJ1dBudOdoZ5khNd63NnQ2S7jja+ HdnRUgtT/m1SQ== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7C21B17E010F; Tue, 14 Jul 2026 13:44:51 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 18/46] drm/mediatek: mtk_crtc: Complete documentation for struct mtk_crtc Date: Tue, 14 Jul 2026 13:43:46 +0200 Message-ID: <20260714114414.184512-19-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mtk_crtc structure was missing many member descriptions, for which reason, a while ago it was demoted from kerneldoc to code comment. Add documentation for all of the missing structure members and promote it back to kerneldoc. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 33 +++++++++++++++++++---------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 28c0269c3424..e74f6244606f 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -41,18 +41,31 @@ struct mtk_crtc_hw_layer { u8 layer_stages_nr; }; =20 -/* +/** * struct mtk_crtc - MediaTek specific crtc structure. - * @base: crtc object. - * @enabled: records whether crtc_enable succeeded + * @base: CRTC object + * @enabled: Records whether crtc_enable succeeded + * @pending_needs_vblank: Records whether pending config operation needs a= VBlank to finish + * @event: VBlank event to signal upon completion of state update * @hwlayers: Array of mtk_crtc_hw_layer structures, one for each o= verlay plane * @hwlayer_nr: Number of hwlayers - * @mmsys_dev: pointer to the mmsys device for configuration registers - * @mutex: handle to one of the ten disp_mutex streams - * @ddp_comp_nr: number of components in ddp_comp - * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this c= rtc - * - * TODO: Needs update: this header is missing a bunch of member descriptio= ns. + * @pending_planes: Planes pending atomic configuration operation + * @pending_async_planes: Planes pending asynchronous configuration operat= ion + * @cmdq_client: CMDQ Mailbox Client structure + * @cmdq_handle: Handle to CMDQ Packet structure, used to send a packet + * @cmdq_event: Bitmask of GCE Events that CMDQ listens to (to send p= ackets on event) + * @cmdq_vblank_cnt: Number of VBlanks after which CMDQ packet sending ope= ration times out + * @cb_blocking_queue: Wait queue for sending blocking command packet thro= ugh CMDQ Mailbox + * @mmsys_dev: Pointer to the MMSYS device for configuration registe= rs + * @dma_dev: Pointer to the DMA device (usually linked to an IOMMU) + * @mutex: Pointer to the MediaTek MuteX device for HW triggers = mute/unmuting + * @ddp_comp_nr: Number of HW components in ddp_comp structure + * @num_conn_routes: Number of alternative connection routes for a pipeline + * @conn_routes: Array of HW components usable as alternative connecti= on route + * @hw_lock: Display HW access mutex lock + * @config_updating: Tracks whether an asynchronous config update operatio= n is in progress + * @config_lock: Spinlock to protect config_updating variable + * @ddp_comp: Array of HW components used in one Display Controller= pipeline */ struct mtk_crtc { struct drm_crtc base; @@ -81,10 +94,8 @@ struct mtk_crtc { unsigned int num_conn_routes; const struct mtk_drm_route *conn_routes; =20 - /* lock for display hardware access */ struct mutex hw_lock; bool config_updating; - /* lock for config_updating to cmd buffer */ spinlock_t config_lock; =20 struct mtk_ddp_comp *ddp_comp[]; --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6D233A1E92; Tue, 14 Jul 2026 11:44:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029498; cv=none; b=R45DU7kvwKp+YcgdL3EnvHaGJCMNmn3sDKBUlDBHtapVcecDnDK414sh2ObpNzkaR314DtvTVjgm2y2PqnFy6Cq/iwbs2+P3p8oIpMNom8nUyXZLVjzfgiregYYNDLvA9wWrU3yB2jQrFyvUfv5jtTOAWm5+NqEvzP+beT8PurE= ARC-Message-Signature: i=1; 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charset="utf-8" In ddp_cmdq_cb (the CMDQ mailbox callback), the config_lock spin lock is being locked to read the config_updating variable in the mtk_crtc structure, as, if configuration is updating, the callback function shall not run (or shall run at a later time). It is therefore unnecessary to keep the spinlock until the end of the function, in case pending config, planes, or async planes bools need to be updated. Though the cmdq callback is not a performance path in this case, this may be running for each frame that is pushed to the display, so from 30 (or less) up to 144 times (or more) per second. Add a temporary "cfg_updating" variable to aid with readability, and unlock the spinlock as soon as the config_updating variable read operation is done as a micro-optimization. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index e74f6244606f..2cdf28a0e2ff 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -288,6 +288,7 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *m= ssg) struct mtk_crtc_state *state; unsigned int i; unsigned long flags; + bool cfg_updating; =20 /* release GCE HW usage and start autosuspend */ pm_runtime_mark_last_busy(cmdq_cl->chan->mbox->dev); @@ -299,7 +300,10 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *= mssg) state =3D to_mtk_crtc_state(mtk_crtc->base.state); =20 spin_lock_irqsave(&mtk_crtc->config_lock, flags); - if (mtk_crtc->config_updating) + cfg_updating =3D mtk_crtc->config_updating; + spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); + + if (cfg_updating) goto ddp_cmdq_cb_out; =20 state->pending_config =3D false; @@ -329,14 +333,11 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void = *mssg) } =20 ddp_cmdq_cb_out: - if (mtk_crtc->pending_needs_vblank) { mtk_crtc_finish_page_flip(mtk_crtc); mtk_crtc->pending_needs_vblank =3D false; } =20 - spin_unlock_irqrestore(&mtk_crtc->config_lock, flags); - mtk_crtc->cmdq_vblank_cnt =3D 0; wake_up(&mtk_crtc->cb_blocking_queue); } --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E5F3AB5B7; Tue, 14 Jul 2026 11:44:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029498; cv=none; b=l9vNSB/bJWBXnL5sNLzJ2wH5rKfdF4G7f3wuNZMqrl1xLwouffaIAUSg3OqsZVTbOlTWJF2NpWMn7pv6rQEezo2355B0w39Y2Q7sifJV0f4WXF53d3gJuyJxb7bCvvrR1sFWif5DnzrnDC2H+hGq3hifRL6fQwH74u4G2BTvrJs= ARC-Message-Signature: i=1; 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charset="utf-8" As of now mtk_crtc assumes that, on all MediaTek SoCs, both the vblank and configuration components are the same one, and also that this would always be the first one in a display pipeline. This is not true! Or at least, it's true for the display pipelines supported by the legacy SoCs like MT8173, and also for the ones that are currently used in the upstream boards on more recent SoCs like MT8188/95, but for the latter ones it just happens to be like this because of how the boards are configured. This is done both in preparation for adding support for complex Display Controller pipelines like needed in MT8196 and MT8894, but also for supporting display pipelines in MT8188/89/95 (and others from the same generation) that are not starting with a component that handles both vblank and layer configuration at the same time. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 56 ++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 2cdf28a0e2ff..72d5caedc4af 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -59,6 +59,8 @@ struct mtk_crtc_hw_layer { * @mmsys_dev: Pointer to the MMSYS device for configuration registe= rs * @dma_dev: Pointer to the DMA device (usually linked to an IOMMU) * @mutex: Pointer to the MediaTek MuteX device for HW triggers = mute/unmuting + * @vblank_comp_idx: Index of HW component where to enable sending VBlanks + * @config_comp_idx: Index of main HW component to use for plane configura= tion * @ddp_comp_nr: Number of HW components in ddp_comp structure * @num_conn_routes: Number of alternative connection routes for a pipeline * @conn_routes: Array of HW components usable as alternative connecti= on route @@ -90,6 +92,8 @@ struct mtk_crtc { struct device *mmsys_dev; struct device *dma_dev; struct mtk_mutex *mutex; + s8 vblank_comp_idx; + s8 config_comp_idx; unsigned int ddp_comp_nr; unsigned int num_conn_routes; const struct mtk_drm_route *conn_routes; @@ -523,7 +527,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc, { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); struct mtk_crtc_state *state =3D to_mtk_crtc_state(mtk_crtc->base.state); - struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[mtk_crtc->config_comp_id= x]; unsigned int i; =20 /* @@ -693,7 +697,7 @@ static void mtk_crtc_ddp_irq(void *data) static int mtk_crtc_enable_vblank(struct drm_crtc *crtc) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[mtk_crtc->vblank_comp_id= x]; =20 mtk_ddp_comp_enable_vblank(comp); =20 @@ -703,7 +707,7 @@ static int mtk_crtc_enable_vblank(struct drm_crtc *crtc) static void mtk_crtc_disable_vblank(struct drm_crtc *crtc) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[mtk_crtc->vblank_comp_id= x]; =20 mtk_ddp_comp_disable_vblank(comp); } @@ -816,7 +820,7 @@ static void mtk_crtc_atomic_enable(struct drm_crtc *crt= c, struct drm_atomic_commit *state) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[mtk_crtc->config_comp_id= x]; struct drm_device *dev =3D mtk_crtc->base.dev; int ret; =20 @@ -844,7 +848,7 @@ static void mtk_crtc_atomic_disable(struct drm_crtc *cr= tc, struct drm_atomic_commit *state) { struct mtk_crtc *mtk_crtc =3D to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[0]; + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[mtk_crtc->config_comp_id= x]; struct drm_device *dev =3D mtk_crtc->base.dev; int i; =20 @@ -1179,6 +1183,10 @@ int mtk_crtc_create(struct drm_device *drm_dev, return ret; } =20 + /* Component 0 would be valid so initialize vblank and config idx to -EIN= VAL */ + mtk_crtc->vblank_comp_idx =3D -EINVAL; + mtk_crtc->config_comp_idx =3D -EINVAL; + for (i =3D 0, j =3D 0; i < mtk_crtc->ddp_comp_nr; i++, j++) { unsigned int comp_id =3D output_path->comp[i].type; struct mtk_ddp_comp *comp; @@ -1201,12 +1209,50 @@ int mtk_crtc_create(struct drm_device *drm_dev, =20 if (comp->funcs->ctm_set) has_ctm =3D true; + + /* + * Assumes that there can only be one vblank enabler per CRTC, + * and that should there be more than one, the one that should + * handle vblanks has to be the bottom-most HW component. + */ + if (mtk_crtc->vblank_comp_idx < 0 && comp->funcs->enable_vblank) + mtk_crtc->vblank_comp_idx =3D j; + + /* + * Assumes that there can only be one main configuration + * component per CRTC, and that if more than one has to + * be configured for at each frame, the main one would + * take care of the config chain. + * + * As a note, such component has specific characteristics: + * - It is configurable, and supports per-layer properties; + * - It is a main layer component and not a layer stage; + * - It is always the first one (the bottom-most) in the + * pipeline that has the characteristics explaned above. + * + * Such hardware is usually an OVL, RDMA or exDMA. + * + * This may change in the future with more complex pipelines. + */ + if (mtk_crtc->config_comp_idx < 0 && comp->funcs->config && + comp->funcs->layer_config && comp->funcs->layer_nr) + mtk_crtc->config_comp_idx =3D j; } =20 mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, &mtk_crtc->base); } =20 + if (mtk_crtc->config_comp_idx < 0) { + dev_err(dev, "No HW component for layer configuration. Bailing out.\n"); + return -EINVAL; + } + + if (mtk_crtc->vblank_comp_idx < 0) { + dev_info(dev, "No vblank enabler component found! Expect timeouts.\n"); + mtk_crtc->vblank_comp_idx =3D 0; + } + for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[i]; =20 --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C43153AFB12; Tue, 14 Jul 2026 11:44:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029499; cv=none; b=WGlLwGgKdBmMgawWkCMEDI8VwYnGi6ugIyacnLvXBIqyIw+wQSq0P/8DHo2KbPdcrII+oITH/1tuGslgYrBS0jf/ouoy9f7FvBQHKq1t5E8iuGGG1pFSSstPGfj2E54R8yD8E0DnQNacN5FFXyNSrNPsmIUdUqPXAhHRAyljz5g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784029499; c=relaxed/simple; bh=s6Vj1WZujnvXkBCJEH/Iq1V9qS+ywOCxMkXWi8KrhAo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SfwK/1InjQMZ1r5t6BYAC4fsYty4iJ3Lti9T7mPdkZwWioSzPET9zNxhFKB7WcTS8Hsg9BK4Z5/PGzqDYvI5AQk+Dn07I9tkymJDqsN6BLd9OVr4EpvlgZgy/I/h3sY2jYfEefCEljHsJt4FTGgsBe6CM8rcbTN+HOT+JfSYuqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=iQqAKbDD; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="iQqAKbDD" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1784029495; bh=s6Vj1WZujnvXkBCJEH/Iq1V9qS+ywOCxMkXWi8KrhAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iQqAKbDD3YnVKW5TOlrwucYuuRYXYBd0OIlnK6/CIMTIM2wvMPRGPyTepKFhJUC3K IHbiHBjaQ8yPm7tAvsKR9i9izex+TtuuOyKEfaANYFYTrE7cmyDCGrRWeKbHl3ZZgu 1SBmabcNYsdKVmRDs77ZwFUbyyDU9ZIZjR6pRa59n2tSfe1QsSCqi7Q4Ue7zYHKqId 4NhVDoq3u7iYjVDo2cvZXBVbhnsPW/L+5F5LtLklRO0IllQHVp+6GpMDMatPX7qH/q NAuozkkRzu1NsxzhhFQiSYEUnsHiLZUMiqjTOko/Dit7Qr4XTN9TtgX8tWWDakp415 huIJHKXNktnoA== Received: from IcarusMOD.eternityproject.eu (unknown [100.64.1.21]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 389A617E0FD0; Tue, 14 Jul 2026 13:44:54 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 21/46] soc: mediatek: mtk-mutex: Add new functions to add/remove triggers Date: Tue, 14 Jul 2026 13:43:49 +0200 Message-ID: <20260714114414.184512-22-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add new mtk_mutex_add_trigger() and mtk_mutex_remove_trigger() to replace, in the near future, their older style equivalents such as mtk_mutex_add_comp() and mtk_mutex_remove_comp() for the Display Controller related MuteX triggers. The same functions will be used to also replace the Media Data Path 3 (MDP3) specific mtk_mutex_write_mod(), unifying the MuteX handling across all of the currently supported multimedia-related drivers for MediaTek SoCs. While at it, this also takes into account the upcoming refactoring of mtk_mmsys and mediatek-drm, which are about to migrate to a new Component "Type -> Hardware ID" mapping, by adding a new function parameter "hw_inst_id" to support that. Acked-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 60 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mutex.h | 6 +++ 2 files changed, 66 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mu= tex.c index eb5d381ff5af..ef8e77f7e2f6 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -887,6 +887,65 @@ void mtk_mutex_unprepare(struct mtk_mutex *mutex) } EXPORT_SYMBOL_GPL(mtk_mutex_unprepare); =20 +static enum mtk_mutex_sof_id mtk_mutex_get_sof_trig(enum mtk_ddp_comp_type= type, + unsigned int hw_inst_id) +{ + switch (type) { + case MTK_DISP_DSI: + return MUTEX_SOF_DSI0 + hw_inst_id; + case MTK_DISP_DPI: + return MUTEX_SOF_DPI0 + hw_inst_id; + case MTK_DISP_DP_INTF: + return MUTEX_SOF_DP_INTF0 + hw_inst_id; + default: + break; + } + + return DDP_MUTEX_SOF_MAX; +} + +void mtk_mutex_add_trigger(struct mtk_mutex *mutex, enum mtk_ddp_comp_type= type, + unsigned int hw_inst_id, unsigned int mtx_trig_id) +{ + struct mtk_mutex_ctx *ctx =3D container_of(mutex, struct mtk_mutex_ctx, m= utex[mutex->id]); + enum mtk_mutex_sof_id sof_id =3D mtk_mutex_get_sof_trig(type, hw_inst_id); + const u32 offset =3D DISP_REG_MUTEX_MOD(ctx, mtx_trig_id, mutex->id); + u32 val; + + if (sof_id < DDP_MUTEX_SOF_MAX) { + const u32 sof_offset =3D DISP_REG_MUTEX_SOF(ctx->data->mutex_sof_reg, mu= tex->id); + + writel(ctx->data->mutex_sof[sof_id], ctx->regs + sof_offset); + return; + } + + val =3D readl(ctx->regs + offset); + writel(val | BIT(mtx_trig_id % 32), ctx->regs + offset); +} +EXPORT_SYMBOL_NS_GPL(mtk_mutex_add_trigger, "MTK_MUTEX"); + +void mtk_mutex_remove_trigger(struct mtk_mutex *mutex, enum mtk_ddp_comp_t= ype type, + unsigned int hw_inst_id, unsigned int mtx_trig_id) +{ + struct mtk_mutex_ctx *ctx =3D container_of(mutex, struct mtk_mutex_ctx, m= utex[mutex->id]); + enum mtk_mutex_sof_id sof_id =3D mtk_mutex_get_sof_trig(type, hw_inst_id); + const u32 offset =3D DISP_REG_MUTEX_MOD(ctx, mtx_trig_id, mutex->id); + u32 val; + + if (sof_id < DDP_MUTEX_SOF_MAX) { + const u32 sof_offset =3D DISP_REG_MUTEX_SOF(ctx->data->mutex_sof_reg, mu= tex->id); + + val =3D readl(ctx->regs + sof_offset); + writel(val & ~ctx->data->mutex_sof[sof_id], ctx->regs + sof_offset); + return; + } + + val =3D readl(ctx->regs + offset); + writel(val & ~BIT(mtx_trig_id % 32), ctx->regs + offset); +} +EXPORT_SYMBOL_NS_GPL(mtk_mutex_remove_trigger, "MTK_MUTEX"); + +/* TODO: Legacy - Scheduled for removal */ void mtk_mutex_add_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id) { @@ -938,6 +997,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex, } EXPORT_SYMBOL_GPL(mtk_mutex_add_comp); =20 +/* TODO: Legacy - Scheduled for removal */ void mtk_mutex_remove_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id) { diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/med= iatek/mtk-mutex.h index 635218e3ac68..5368206dd62c 100644 --- a/include/linux/soc/mediatek/mtk-mutex.h +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -67,16 +67,22 @@ enum mtk_mutex_sof_index { MUTEX_SOF_IDX_MAX /* ALWAYS keep at the end */ }; =20 +enum mtk_ddp_comp_type; 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Tue, 14 Jul 2026 13:44:55 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 22/46] soc: mediatek: mtk-mmsys: Migrate to new Multimedia DDP HW indexing Date: Tue, 14 Jul 2026 13:43:50 +0200 Message-ID: <20260714114414.184512-23-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The mediatek-drm driver is ready to switch to the new Multimedia Subsystem Display Controller HW indexing. Perform the switch by: - Adding new "from_comp_inst" and "to_comp_inst" members in the Multimedia Subsystem HW Routes structure (mtk_mmsys_routes); - Changing the MMSYS_ROUTE() macro to use those, which performs the migration of all SoCs in one go (as all of them use this macro to declare their route entries); - Adding new mtk_mmsys_hw_connect() and mtk_mmsys_hw_disconnect() functions, making use of the new HW Component Type-Instance indexing. Unfortunately, this change needs to go along with the related one in the mediatek-drm driver, otherwise functionality of the Display Controller will regress. The only way to make this possible in two steps is to duplicate all of the routes structure arrays for all of the SoCs, which would result in a total of around ~1200 lines changed twice, and that ignores the big increase in size for this driver during the migration process so, in order to avoid useless bloat, I opted for an inter-dependency between the two changes: mediatek-drm and mtk-mmsys. Acked-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mmsys.c | 99 ++++++++++++++++++++------ drivers/soc/mediatek/mtk-mmsys.h | 15 ++-- include/linux/soc/mediatek/mtk-mmsys.h | 16 ++--- 3 files changed, 90 insertions(+), 40 deletions(-) diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mm= sys.c index 2f3e0778bb17..f501a29a7697 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -1,7 +1,10 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 MediaTek Inc. - * Author: James Liao + * James Liao + * + * Copyrignt (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -182,38 +185,90 @@ static void mtk_mmsys_update_bits(struct mtk_mmsys *m= msys, u32 offset, u32 mask, writel_relaxed(tmp, mmsys->regs + offset); } =20 -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) +/** + * mtk_mmsys_hw_connect - Connect MultiMedia Subsystem (MMSYS) Hardware IPs + * @dev: Device pointer + * @src_type: Type of the Source IP + * @src_hw_inst_id: Hardware instance of the Source IP + * @dst_type: Type of the Destination IP + * @dst_hw_inst_id: Hardware instance of the Destination IP + * + * This function connects one MultiMedia Subsystem (MMSYS) related hardware + * to another (in the same subsystem), depending on supported connections. + * In short, this connects "Source" to "Destination", as in, enables sendi= ng + * data from a Source IP to a Destination IP. + * + * As a final note - depending on the SoC and on the specific IPs, it may + * also be possible to connect multiple Sources to a single Destination. + * + * Examples below follow this format to explain hardware components: + * [Source Type][Instance ID] -> [Destination Type] [Instance ID] + * + * Example 1 - Single Source to Destination + * GAMMA 0 -> DITHER 0 + * + * Example 2 - Multiple Sources to Single Destination + * MDP_RDMA 0 -----\ + * | + * v + * MDP_RDMA 1 ---> MERGE 1 \ + * MDP_RDMA 2 ---> MERGE 2 -\ + * >> ETHDR_MIXER 0 + * (other 1) ---> MERGE 3 -/ + * (other 2) ---> MERGE 4 / + * + * Note that in Example 2, some components are not chained together, but + * connected in parallel to a destination. + */ +void mtk_mmsys_hw_connect(struct device *dev, + enum mtk_ddp_comp_type src_type, u8 src_hw_inst_id, + enum mtk_ddp_comp_type dst_type, u8 dst_hw_inst_id) { struct mtk_mmsys *mmsys =3D dev_get_drvdata(dev); const struct mtk_mmsys_routes *routes =3D mmsys->data->routes; - int i; =20 - for (i =3D 0; i < mmsys->data->num_routes; i++) - if (cur =3D=3D routes[i].from_comp && next =3D=3D routes[i].to_comp) - mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, - routes[i].val, NULL); + for (int i =3D 0; i < mmsys->data->num_routes; i++) { + if (src_type !=3D routes[i].from_comp_type || + src_hw_inst_id !=3D routes[i].from_comp_inst || + dst_type !=3D routes[i].to_comp_type || + dst_hw_inst_id !=3D routes[i].to_comp_inst) + continue; =20 - if (mmsys->data->vsync_len) - mtk_mmsys_update_bits(mmsys, MT8188_VDO1_MIXER_VSYNC_LEN, GENMASK(31, 0), - mmsys->data->vsync_len, NULL); + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, routes[i].v= al, NULL); + dev_dbg(dev, "Connected %u-%u to %u-%u\n", + src_type, src_hw_inst_id, dst_type, dst_hw_inst_id); + } } -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next) +EXPORT_SYMBOL_NS_GPL(mtk_mmsys_hw_connect, "MTK_MMSYS"); + +/** + * mtk_mmsys_hw_disconnect - Disconnect MultiMedia Subsystem (MMSYS) Hardw= are IPs + * @dev: Device pointer + * @src_type: Type of the Source IP + * @src_hw_inst_id: Hardware instance of the Source IP + * @dst_type: Type of the Destination IP + * @dst_hw_inst_id: Hardware instance of the Destination IP + */ +void mtk_mmsys_hw_disconnect(struct device *dev, + enum mtk_ddp_comp_type src_type, u8 src_hw_inst_id, + enum mtk_ddp_comp_type dst_type, u8 dst_hw_inst_id) { struct mtk_mmsys *mmsys =3D dev_get_drvdata(dev); const struct mtk_mmsys_routes *routes =3D mmsys->data->routes; - int i; =20 - for (i =3D 0; i < mmsys->data->num_routes; i++) - if (cur =3D=3D routes[i].from_comp && next =3D=3D routes[i].to_comp) - mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL); + for (int i =3D 0; i < mmsys->data->num_routes; i++) { + if (src_type !=3D routes[i].from_comp_type || + src_hw_inst_id !=3D routes[i].from_comp_inst || + dst_type !=3D routes[i].to_comp_type || + dst_hw_inst_id !=3D routes[i].to_comp_inst) + continue; + + mtk_mmsys_update_bits(mmsys, routes[i].addr, routes[i].mask, 0, NULL); + dev_dbg(dev, "Disconnected %u-%u from %u-%u\n", + src_type, src_hw_inst_id, dst_type, dst_hw_inst_id); + } } -EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect); +EXPORT_SYMBOL_NS_GPL(mtk_mmsys_hw_disconnect, "MTK_MMSYS"); =20 void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, = int height, struct cmdq_pkt *cmdq_pkt) diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mm= sys.h index c51a5e334e29..5c9319f3a2bb 100644 --- a/drivers/soc/mediatek/mtk-mmsys.h +++ b/drivers/soc/mediatek/mtk-mmsys.h @@ -80,20 +80,13 @@ =20 #define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit)) =20 -/* Temporary compatibility definitions */ -#define DDP_COMPONENT_BLS0 DDP_COMPONENT_BLS -#define DDP_COMPONENT_CCORR0 DDP_COMPONENT_CCORR -#define DDP_COMPONENT_UFOE0 DDP_COMPONENT_UFOE -#define DDP_COMPONENT_GAMMA0 DDP_COMPONENT_GAMMA -#define DDP_COMPONENT_ETHDR_MIXER0 DDP_COMPONENT_ETHDR_MIXER - /* * This macro adds a compile time check to make sure that the in/out * selection bit(s) fit in the register mask, similar to bitfield * macros, but this does not transform the value. */ #define MMSYS_ROUTE(from, fsid, to, tsid, reg_addr, reg_mask, selection) \ - { DDP_COMPONENT_##from##fsid, DDP_COMPONENT_##to##tsid, reg_addr, reg_mas= k, \ + { MTK_DISP_##from, fsid, MTK_DISP_##to, tsid, reg_addr, reg_mask, \ (__BUILD_BUG_ON_ZERO_MSG((reg_mask) =3D=3D 0, "Invalid mask") + \ __BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection), \ #selection " does not fit in " \ @@ -102,8 +95,10 @@ } =20 struct mtk_mmsys_routes { - u32 from_comp; - u32 to_comp; + u8 from_comp_type; + u8 from_comp_inst; + u8 to_comp_type; + u8 to_comp_inst; u32 addr; u32 mask; u32 val; diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/med= iatek/mtk-mmsys.h index bbdd0b01927d..f67f21d04163 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -118,14 +118,6 @@ enum mtk_ddp_comp_type { MTK_DDP_COMP_TYPE_MAX }; =20 -void mtk_mmsys_ddp_connect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next); - -void mtk_mmsys_ddp_disconnect(struct device *dev, - enum mtk_ddp_comp_id cur, - enum mtk_ddp_comp_id next); - void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val); =20 void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, @@ -134,6 +126,14 @@ void mtk_mmsys_merge_async_config(struct device *dev, = int idx, int width, void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height, struct cmdq_pkt *cmdq_pkt); =20 +void mtk_mmsys_hw_connect(struct device *dev, + enum mtk_ddp_comp_type src_type, u8 src_hw_inst_id, + enum mtk_ddp_comp_type dst_type, u8 dst_hw_inst_id); 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charset="utf-8" Perform a full migration to HW Type -> HW Instance ID indexing for all of the currently supported Display Controller hardware sub-components. This allows to remove the big fixed-size catch-all components array (that contains as many element as much as the number of supported hardware and number of instances of that), which is currently growing bigger and bigger at every sub-ip support addition in mediatek-drm. Note that this cleanup became necessary seen the need to add support for new components found in MT8196, MT8994 and other variants of it, and of course those SoCs won't be the last ones to be upstreamed... so the size of that array would get out of control pretty fast (and again, it's already very big). As a side effect, while saving memory compared to before this change, this also allows to have up to 24 (as an extensible fixed size declared in this driver) instances of the same HW Type with no further increase in memory footprint. Similarly, adding support for new hardware will not produce an increase of memory footprint on all SoCs (if not only temporarily while the probe process is in place) as there's no more catch-all array, but only a dynamically allocated list of per display output components. Unfortunately, this change needs to go along with the related one in the mtk-mmsys driver, otherwise functionality of the Display Controller will regress. The only way to make this possible in two steps is to duplicate all of the routes structure arrays for all of the SoCs, which would result in a total of around ~1200 lines changed twice, and that ignores the big increase in size for this driver during the migration process so, in order to avoid useless bloat, I opted for an inter-dependency between the two changes: mediatek-drm and mtk-mmsys. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_crtc.c | 126 ++-- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 131 ++-- drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 28 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 +- .../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 108 ++-- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 74 +-- drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +- drivers/gpu/drm/mediatek/mtk_drm_legacy.c | 602 +++++++++--------- drivers/gpu/drm/mediatek/mtk_drm_legacy.h | 3 +- 9 files changed, 538 insertions(+), 552 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek= /mtk_crtc.c index 72d5caedc4af..3cb2d1a28987 100644 --- a/drivers/gpu/drm/mediatek/mtk_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c @@ -416,28 +416,32 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_= crtc) } =20 for (i =3D 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { - if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, - mtk_crtc->ddp_comp[i + 1]->id)) - mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev, - mtk_crtc->ddp_comp[i]->id, - mtk_crtc->ddp_comp[i + 1]->id); - if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) - mtk_mutex_add_comp(mtk_crtc->mutex, - mtk_crtc->ddp_comp[i]->id); - - /* For now, only single DSI is supported */ - if (mtk_crtc->ddp_comp[i]->id >=3D DDP_COMPONENT_DSI0 && - mtk_crtc->ddp_comp[i]->id <=3D DDP_COMPONENT_DSI3) - if (!comp_dsi) - comp_dsi =3D mtk_crtc->ddp_comp[i]; - - if (mtk_crtc->ddp_comp[i]->id =3D=3D DDP_COMPONENT_DSC0 || - mtk_crtc->ddp_comp[i]->id =3D=3D DDP_COMPONENT_DSC1) - if (!comp_dsc) - comp_dsc =3D mtk_crtc->ddp_comp[i]; + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[i]; + struct mtk_ddp_comp *next =3D mtk_crtc->ddp_comp[i + 1]; + + if (!mtk_ddp_comp_connect(comp, mtk_crtc->mmsys_dev, next)) + mtk_mmsys_hw_connect(mtk_crtc->mmsys_dev, + comp->type, comp->inst_id, + next->type, next->inst_id); + + if (!mtk_ddp_comp_add(comp, mtk_crtc->mutex)) + mtk_mutex_add_trigger(mtk_crtc->mutex, + comp->type, comp->inst_id, + comp->mtx_trig_id); + + /* For DSC only single DSI is supported at the moment */ + if (comp->type =3D=3D MTK_DISP_DSI && !comp_dsi) + comp_dsi =3D mtk_crtc->ddp_comp[i]; + + if (comp->type =3D=3D MTK_DISP_DSC && !comp_dsc) + comp_dsc =3D mtk_crtc->ddp_comp[i]; } if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) - mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); + mtk_mutex_add_trigger(mtk_crtc->mutex, + mtk_crtc->ddp_comp[i]->type, + mtk_crtc->ddp_comp[i]->inst_id, + mtk_crtc->ddp_comp[i]->mtx_trig_id); + mtk_mutex_enable(mtk_crtc->mutex); =20 for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) { @@ -494,21 +498,31 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk= _crtc) =20 for (i =3D 0; i < mtk_crtc->ddp_comp_nr; i++) if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) - mtk_mutex_remove_comp(mtk_crtc->mutex, - mtk_crtc->ddp_comp[i]->id); + mtk_mutex_remove_trigger(mtk_crtc->mutex, + mtk_crtc->ddp_comp[i]->type, + mtk_crtc->ddp_comp[i]->inst_id, + mtk_crtc->ddp_comp[i]->mtx_trig_id); mtk_mutex_disable(mtk_crtc->mutex); for (i =3D 0; i < mtk_crtc->ddp_comp_nr - 1; i++) { - if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev, - mtk_crtc->ddp_comp[i + 1]->id)) - mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev, - mtk_crtc->ddp_comp[i]->id, - mtk_crtc->ddp_comp[i + 1]->id); + struct mtk_ddp_comp *comp =3D mtk_crtc->ddp_comp[i]; + struct mtk_ddp_comp *next =3D mtk_crtc->ddp_comp[i + 1]; + + if (!mtk_ddp_comp_disconnect(comp, mtk_crtc->mmsys_dev, next)) + mtk_mmsys_hw_disconnect(mtk_crtc->mmsys_dev, + comp->type, comp->inst_id, + next->type, next->inst_id); + if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) - mtk_mutex_remove_comp(mtk_crtc->mutex, - mtk_crtc->ddp_comp[i]->id); + mtk_mutex_remove_trigger(mtk_crtc->mutex, + mtk_crtc->ddp_comp[i]->type, + mtk_crtc->ddp_comp[i]->inst_id, + mtk_crtc->ddp_comp[i]->mtx_trig_id); } if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex)) - mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id); + mtk_mutex_remove_trigger(mtk_crtc->mutex, + mtk_crtc->ddp_comp[i]->type, + mtk_crtc->ddp_comp[i]->inst_id, + mtk_crtc->ddp_comp[i]->mtx_trig_id); mtk_crtc_ddp_clk_disable(mtk_crtc); mtk_mutex_unprepare(mtk_crtc->mutex); =20 @@ -739,15 +753,16 @@ static void mtk_crtc_update_output(struct drm_crtc *c= rtc, const struct mtk_drm_route *conn_route =3D &mtk_crtc->conn_routes[i]; struct mtk_ddp_comp *comp; =20 - comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, conn_route->route_ddp); + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, conn_route->route_ddp_typ= e, + conn_route->route_ddp_inst_id); if (!comp) continue; =20 if (comp->encoder_index >=3D 0 && (encoder_mask & BIT(comp->encoder_index))) { mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] =3D comp; - dev_dbg(dev, "Add comp_id: %d at path index %d\n", - comp->id, mtk_crtc->ddp_comp_nr - 1); + dev_dbg(dev, "Add comp %u-%u at path index %d\n", + comp->type, comp->inst_id, mtk_crtc->ddp_comp_nr - 1); break; } } @@ -1143,25 +1158,15 @@ int mtk_crtc_create(struct drm_device *drm_dev, crtc_i++; =20 for (i =3D 0; i < output_path[i].len; i++) { - enum mtk_ddp_comp_id comp_id =3D output_path->comp[i].type; - struct device_node *node; + enum mtk_ddp_comp_type comp_type =3D output_path->comp[i].type; + u8 comp_inst =3D output_path->comp[i].inst_id; struct mtk_ddp_comp *comp; =20 - node =3D priv->comp_node[comp_id]; - comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_id); - - /* Not all drm components have a DTS device node, such as ovl_adaptor, - * which is the drm bring up sub driver - */ - if (!node && comp_id !=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { - dev_info(dev, - "Not creating crtc %d because component %d is disabled or missing\n", - crtc_i, comp_id); - return 0; - } - + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_type, comp_inst); if (!comp || !comp->dev) { - dev_err(dev, "Component %pOF not initialized\n", node); + dev_err(dev, + "CRTC%d: Component type=3D%u inst=3D%u not initialized\n", + crtc_i, comp_type, comp_inst); return -ENODEV; } } @@ -1188,13 +1193,14 @@ int mtk_crtc_create(struct drm_device *drm_dev, mtk_crtc->config_comp_idx =3D -EINVAL; =20 for (i =3D 0, j =3D 0; i < mtk_crtc->ddp_comp_nr; i++, j++) { - unsigned int comp_id =3D output_path->comp[i].type; + enum mtk_ddp_comp_type comp_type =3D output_path->comp[i].type; + u8 comp_inst =3D output_path->comp[i].inst_id; struct mtk_ddp_comp *comp; =20 - comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_id); + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_type, comp_inst); if (!comp) { j--; - dev_dbg(dev, "Cannot find component %d.\n", comp_id); + dev_dbg(dev, "Cannot find component %u-%u.\n", comp_type, comp_inst); continue; } mtk_crtc->ddp_comp[j] =3D comp; @@ -1306,7 +1312,9 @@ int mtk_crtc_create(struct drm_device *drm_dev, * In the case of ovl_adaptor sub driver, it needs to use the * dma_dev_get function to get representative dma dev. */ - dma_comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, output_path->comp[0].t= ype); + dma_comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, + output_path->comp[0].type, + output_path->comp[0].inst_id); if (dma_comp =3D=3D NULL) { dev_err(dev, "Could not find appropriate DMA device!\n"); return -EINVAL; @@ -1368,13 +1376,15 @@ int mtk_crtc_create(struct drm_device *drm_dev, =20 if (conn_routes) { for (i =3D 0; i < num_conn_routes; i++) { - unsigned int comp_id =3D conn_routes[i].route_ddp; - struct device_node *node =3D priv->comp_node[comp_id]; - struct mtk_ddp_comp *comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, com= p_id); + enum mtk_ddp_comp_type comp_type =3D conn_routes[i].route_ddp_type; + u8 comp_inst =3D conn_routes[i].route_ddp_inst_id; + struct mtk_ddp_comp *comp; =20 + comp =3D mtk_ddp_comp_find_by_id(&priv->hlist, comp_type, comp_inst); if (!comp || !comp->dev) { - dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n", - comp_id, node); + dev_dbg(dev, "Cannot find conn_route component %u-%u.\n", + comp_type, comp_inst); + /* mark encoder_index to -1, if route comp device is not enabled */ if (comp) comp->encoder_index =3D -1; diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index ee8d12dd9968..3ad364abc95b 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -4,6 +4,10 @@ * Authors: * YT Shen * CK Hu + * + * Major refactoring + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include @@ -428,65 +432,36 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_C= OMP_TYPE_MAX] =3D { [MTK_DISP_DSI] =3D "dsi", }; =20 -struct mtk_ddp_comp_match { - enum mtk_ddp_comp_type type; - int alias_id; - const struct mtk_ddp_comp_funcs *funcs; -}; - -static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_I= D_MAX] =3D { - [DDP_COMPONENT_AAL0] =3D { MTK_DISP_AAL, 0, &ddp_aal }, - [DDP_COMPONENT_AAL1] =3D { MTK_DISP_AAL, 1, &ddp_aal }, - [DDP_COMPONENT_BLS] =3D { MTK_DISP_BLS, 0, NULL }, - [DDP_COMPONENT_CCORR] =3D { MTK_DISP_CCORR, 0, &ddp_ccorr }, - [DDP_COMPONENT_COLOR0] =3D { MTK_DISP_COLOR, 0, &ddp_color }, - [DDP_COMPONENT_COLOR1] =3D { MTK_DISP_COLOR, 1, &ddp_color }, - [DDP_COMPONENT_DITHER0] =3D { MTK_DISP_DITHER, 0, &ddp_dither }, - [DDP_COMPONENT_DP_INTF0] =3D { MTK_DISP_DP_INTF, 0, &ddp_dpi }, - [DDP_COMPONENT_DP_INTF1] =3D { MTK_DISP_DP_INTF, 1, &ddp_dpi }, - [DDP_COMPONENT_DPI0] =3D { MTK_DISP_DPI, 0, &ddp_dpi }, - [DDP_COMPONENT_DPI1] =3D { MTK_DISP_DPI, 1, &ddp_dpi }, - [DDP_COMPONENT_DRM_OVL_ADAPTOR] =3D { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_a= daptor }, - [DDP_COMPONENT_DSC0] =3D { MTK_DISP_DSC, 0, &ddp_dsc }, - [DDP_COMPONENT_DSC1] =3D { MTK_DISP_DSC, 1, &ddp_dsc }, - [DDP_COMPONENT_DSI0] =3D { MTK_DISP_DSI, 0, &ddp_dsi }, - [DDP_COMPONENT_DSI1] =3D { MTK_DISP_DSI, 1, &ddp_dsi }, - [DDP_COMPONENT_DSI2] =3D { MTK_DISP_DSI, 2, &ddp_dsi }, - [DDP_COMPONENT_DSI3] =3D { MTK_DISP_DSI, 3, &ddp_dsi }, - [DDP_COMPONENT_GAMMA] =3D { MTK_DISP_GAMMA, 0, &ddp_gamma }, - [DDP_COMPONENT_MERGE0] =3D { MTK_DISP_MERGE, 0, &ddp_merge }, - [DDP_COMPONENT_MERGE1] =3D { MTK_DISP_MERGE, 1, &ddp_merge }, - [DDP_COMPONENT_MERGE2] =3D { MTK_DISP_MERGE, 2, &ddp_merge }, - [DDP_COMPONENT_MERGE3] =3D { MTK_DISP_MERGE, 3, &ddp_merge }, - [DDP_COMPONENT_MERGE4] =3D { MTK_DISP_MERGE, 4, &ddp_merge }, - [DDP_COMPONENT_MERGE5] =3D { MTK_DISP_MERGE, 5, &ddp_merge }, - [DDP_COMPONENT_OD0] =3D { MTK_DISP_OD, 0, &ddp_od }, - [DDP_COMPONENT_OD1] =3D { MTK_DISP_OD, 1, &ddp_od }, - [DDP_COMPONENT_OVL0] =3D { MTK_DISP_OVL, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL1] =3D { MTK_DISP_OVL, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L0] =3D { MTK_DISP_OVL_2L, 0, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L1] =3D { MTK_DISP_OVL_2L, 1, &ddp_ovl }, - [DDP_COMPONENT_OVL_2L2] =3D { MTK_DISP_OVL_2L, 2, &ddp_ovl }, - [DDP_COMPONENT_POSTMASK0] =3D { MTK_DISP_POSTMASK, 0, &ddp_postmask }, - [DDP_COMPONENT_PWM0] =3D { MTK_DISP_PWM, 0, NULL }, - [DDP_COMPONENT_PWM1] =3D { MTK_DISP_PWM, 1, NULL }, - [DDP_COMPONENT_PWM2] =3D { MTK_DISP_PWM, 2, NULL }, - [DDP_COMPONENT_RDMA0] =3D { MTK_DISP_RDMA, 0, &ddp_rdma }, - [DDP_COMPONENT_RDMA1] =3D { MTK_DISP_RDMA, 1, &ddp_rdma }, - [DDP_COMPONENT_RDMA2] =3D { MTK_DISP_RDMA, 2, &ddp_rdma }, - [DDP_COMPONENT_RDMA4] =3D { MTK_DISP_RDMA, 4, &ddp_rdma }, - [DDP_COMPONENT_UFOE] =3D { MTK_DISP_UFOE, 0, &ddp_ufoe }, - [DDP_COMPONENT_WDMA0] =3D { MTK_DISP_WDMA, 0, &ddp_wdma }, - [DDP_COMPONENT_WDMA1] =3D { MTK_DISP_WDMA, 1, &ddp_wdma }, +static const struct mtk_ddp_comp_funcs *mtk_ddp_funcs[MTK_DDP_COMP_TYPE_MA= X] =3D { + [MTK_DISP_AAL] =3D &ddp_aal, + [MTK_DISP_BLS] =3D NULL, + [MTK_DISP_CCORR] =3D &ddp_ccorr, + [MTK_DISP_COLOR] =3D &ddp_color, + [MTK_DISP_DITHER] =3D &ddp_dither, + [MTK_DISP_DSC] =3D &ddp_dsc, + [MTK_DISP_GAMMA] =3D &ddp_gamma, + [MTK_DISP_MERGE] =3D &ddp_merge, + [MTK_DISP_OD] =3D &ddp_od, + [MTK_DISP_OVL] =3D &ddp_ovl, + [MTK_DISP_OVL_2L] =3D &ddp_ovl, + [MTK_DISP_OVL_ADAPTOR] =3D &ddp_ovl_adaptor, + [MTK_DISP_POSTMASK] =3D &ddp_postmask, + [MTK_DISP_PWM] =3D NULL, + [MTK_DISP_RDMA] =3D &ddp_rdma, + [MTK_DISP_UFOE] =3D &ddp_ufoe, + [MTK_DISP_WDMA] =3D &ddp_wdma, + [MTK_DISP_DPI] =3D &ddp_dpi, + [MTK_DISP_DP_INTF] =3D &ddp_dpi, + [MTK_DISP_DSI] =3D &ddp_dsi, }; =20 static bool mtk_ddp_find_comp_dev_in_table(const struct mtk_drm_comp_list = *hlist, - const unsigned int comp_id, + const unsigned int comp_type, struct device *dev) { struct mtk_ddp_comp *ddp_comp; =20 - hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_id) { + hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_type) { if (ddp_comp->dev =3D=3D dev) return true; } @@ -518,42 +493,23 @@ static int mtk_ddp_comp_find_in_route(struct device *= dev, return -EINVAL; =20 for (i =3D 0; i < num_routes; i++) - if (mtk_ddp_find_comp_dev_in_table(hlist, routes[i].route_ddp, dev)) + if (mtk_ddp_find_comp_dev_in_table(hlist, routes[i].route_ddp_type, dev)) return BIT(routes[i].crtc_id); =20 return -ENODEV; } =20 -static bool mtk_ddp_path_available(const struct mtk_drm_path_definition *o= utput_path, - struct device_node **comp_node) -{ - unsigned int i; - - for (i =3D 0U; i < output_path->len; i++) { - /* OVL_ADAPTOR doesn't have a device node */ - if (output_path->comp[i].type =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) - continue; - - if (!comp_node[output_path->comp[i].type]) - return false; - } - - return true; -} - int mtk_ddp_comp_get_id(struct device_node *node, enum mtk_ddp_comp_type comp_type) { - int id =3D of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); - int i; - - for (i =3D 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) { - if (comp_type =3D=3D mtk_ddp_matches[i].type && - (id < 0 || id =3D=3D mtk_ddp_matches[i].alias_id)) - return i; + /* If there's an alias, return the ID from that */ + if (mtk_ddp_comp_stem[comp_type]) { + int alias_id =3D of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]); + if (alias_id >=3D 0) + return alias_id; } =20 - return -EINVAL; + return 0; } =20 int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev) @@ -561,7 +517,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, str= uct device *dev) struct mtk_drm_private *private =3D drm->dev_private; const struct mtk_mmsys_driver_data *data; struct mtk_drm_private *priv_n; - int i =3D 0, j; + int i, j; int ret; =20 for (j =3D 0; j < private->data->mmsys_dev_num; j++) { @@ -673,24 +629,22 @@ static int mtk_ddp_comp_init_internal_comp(struct dev= ice *dev, struct device *co =20 int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_drm_comp_list *hlist, - unsigned int comp_id) + enum mtk_ddp_comp_type comp_type, int comp_inst_id) { struct platform_device *comp_pdev; struct mtk_ddp_comp *comp; - enum mtk_ddp_comp_type type; int ret; =20 - if (comp_id >=3D DDP_COMPONENT_DRM_ID_MAX) + if (comp_type >=3D MTK_DDP_COMP_TYPE_MAX) return -EINVAL; =20 comp =3D devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); if (!comp) return -ENOMEM; =20 - type =3D mtk_ddp_matches[comp_id].type; - - comp->id =3D comp_id; - comp->funcs =3D mtk_ddp_matches[comp_id].funcs; + comp->type =3D comp_type; + comp->inst_id =3D comp_inst_id; + comp->funcs =3D mtk_ddp_funcs[comp_type]; /* Not all drm components have a DTS device node, such as ovl_adaptor, * which is the drm bring up sub driver */ @@ -715,13 +669,14 @@ int mtk_ddp_comp_init(struct device *dev, struct devi= ce_node *node, comp->mtx_trig_id =3D ret; =20 /* If there's no external driver for this component, allocate and init no= w */ - if (mtk_ddp_comp_is_internal_comp(type) || mtk_ddp_comp_is_backlight_comp= (type)) { + if (mtk_ddp_comp_is_internal_comp(comp->type) || + mtk_ddp_comp_is_backlight_comp(comp->type)) { ret =3D mtk_ddp_comp_init_internal_comp(dev, comp->dev); if (ret) return ret; } end: - hash_add(hlist->ddp_list, &comp->lnode, comp->id); + hash_add(hlist->ddp_list, &comp->lnode, comp->type); =20 return 0; } diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index a7ed46a95037..ab9d5e4dfb98 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -16,6 +16,7 @@ #include =20 #define MTK_DISP_CONTROLLER_MAX_COMP_PER_PATH 24 +#define MTK_DISP_CONTROLLER_MAX_HW_COMP_INSTANCE 32 =20 struct device; struct device_node; @@ -70,8 +71,10 @@ struct mtk_ddp_comp_funcs { const u32 *(*get_formats)(struct device *dev); size_t (*get_num_formats)(struct device *dev); bool (*is_afbc_supported)(struct device *dev); - void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned in= t next); - void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned= int next); + void (*connect)(struct mtk_ddp_comp *comp, struct device *mmsys_dev, + struct mtk_ddp_comp *next); + void (*disconnect)(struct mtk_ddp_comp *comp, struct device *mmsys_dev, + struct mtk_ddp_comp *next); void (*add)(struct device *dev, struct mtk_mutex *mutex); void (*remove)(struct device *dev, struct mtk_mutex *mutex); unsigned int (*encoder_index)(struct device *dev); @@ -81,7 +84,8 @@ struct mtk_ddp_comp_funcs { struct mtk_ddp_comp { struct device *dev; int irq; - unsigned int id; + enum mtk_ddp_comp_type type; + u8 inst_id; u8 mtx_trig_id; int encoder_index; const struct mtk_ddp_comp_funcs *funcs; @@ -326,20 +330,20 @@ static inline bool mtk_ddp_comp_remove(struct mtk_ddp= _comp *comp, struct mtk_mut } =20 static inline bool mtk_ddp_comp_connect(struct mtk_ddp_comp *comp, struct = device *mmsys_dev, - unsigned int next) + struct mtk_ddp_comp *next) { if (comp->funcs && comp->funcs->connect) { - comp->funcs->connect(comp->dev, mmsys_dev, next); + comp->funcs->connect(comp, mmsys_dev, next); return true; } return false; } =20 static inline bool mtk_ddp_comp_disconnect(struct mtk_ddp_comp *comp, stru= ct device *mmsys_dev, - unsigned int next) + struct mtk_ddp_comp *next) { if (comp->funcs && comp->funcs->disconnect) { - comp->funcs->disconnect(comp->dev, mmsys_dev, next); + comp->funcs->disconnect(comp, mmsys_dev, next); return true; } return false; @@ -353,12 +357,14 @@ static inline void mtk_ddp_comp_encoder_index_set(str= uct mtk_ddp_comp *comp) =20 static inline struct mtk_ddp_comp *mtk_ddp_comp_find_by_id(struct mtk_drm_comp_list *hlist, - const unsigned int id) + const unsigned int comp_type, + const unsigned int comp_inst_id) { struct mtk_ddp_comp *ddp_comp; =20 - hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, id) - return ddp_comp; + hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_type) + if (ddp_comp->inst_id =3D=3D comp_inst_id) + return ddp_comp; =20 return NULL; } @@ -369,7 +375,7 @@ int mtk_ddp_comp_get_id(struct device_node *node, int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev); int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_drm_comp_list *hlist, - unsigned int comp_id); + enum mtk_ddp_comp_type comp_type, int comp_inst_id); int mtk_ddp_comp_get_mutex_trigger(struct device_node *node, unsigned int = index); enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id); void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value, diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/medi= atek/mtk_disp_drv.h index 7706d95b3be8..c4b44b761633 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -11,6 +11,7 @@ #include #include #include +#include "mtk_ddp_comp.h" #include "mtk_mdp_rdma.h" #include "mtk_plane.h" =20 @@ -122,10 +123,10 @@ bool mtk_ovl_is_afbc_supported(struct device *dev); void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex); void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mut= ex); bool mtk_ovl_adaptor_is_comp_present(struct device_node *node); -void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, - unsigned int next); -void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_d= ev, - unsigned int next); +void mtk_ovl_adaptor_connect(struct mtk_ddp_comp *comp, struct device *mms= ys_dev, + struct mtk_ddp_comp *next); +void mtk_ovl_adaptor_disconnect(struct mtk_ddp_comp *comp, struct device *= mmsys_dev, + struct mtk_ddp_comp *next); int mtk_ovl_adaptor_power_on(struct device *dev); void mtk_ovl_adaptor_power_off(struct device *dev); int mtk_ovl_adaptor_clk_enable(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/= drm/mediatek/mtk_disp_ovl_adaptor.c index 78bc3bee0794..225ab87bca71 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c @@ -61,7 +61,7 @@ enum mtk_ovl_adaptor_comp_id { =20 struct ovl_adaptor_comp_match { enum mtk_ovl_adaptor_comp_type type; - enum mtk_ddp_comp_id comp_id; + enum mtk_ddp_comp_type comp_type; int alias_id; const struct mtk_ddp_comp_funcs *funcs; }; @@ -108,27 +108,27 @@ static const struct mtk_ddp_comp_funcs rdma =3D { }; =20 static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX= ] =3D { - [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MI= XER, 0, ðdr }, - [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA0, 0, &rdma }, - [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA1, 1, &rdma }, - [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA2, 2, &rdma }, - [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA3, 3, &rdma }, - [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA4, 4, &rdma }, - [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA5, 5, &rdma }, - [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA6, 6, &rdma }, - [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MD= P_RDMA7, 7, &rdma }, - [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, = 1, &merge }, - [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, = 2, &merge }, - [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, = 3, &merge }, - [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, = 4, &merge }, - [OVL_ADAPTOR_PADDING0] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING0, 0, &padding }, - [OVL_ADAPTOR_PADDING1] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING1, 1, &padding }, - [OVL_ADAPTOR_PADDING2] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING2, 2, &padding }, - [OVL_ADAPTOR_PADDING3] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING3, 3, &padding }, - [OVL_ADAPTOR_PADDING4] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING4, 4, &padding }, - [OVL_ADAPTOR_PADDING5] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING5, 5, &padding }, - [OVL_ADAPTOR_PADDING6] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING6, 6, &padding }, - [OVL_ADAPTOR_PADDING7] =3D { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADD= ING7, 7, &padding }, + [OVL_ADAPTOR_ETHDR0] =3D { OVL_ADAPTOR_TYPE_ETHDR, MTK_DISP_ETHDR_MIXER, = 0, ðdr }, + [OVL_ADAPTOR_MDP_RDMA0] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 0, &rdma }, + [OVL_ADAPTOR_MDP_RDMA1] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 1, &rdma }, + [OVL_ADAPTOR_MDP_RDMA2] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 2, &rdma }, + [OVL_ADAPTOR_MDP_RDMA3] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 3, &rdma }, + [OVL_ADAPTOR_MDP_RDMA4] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 4, &rdma }, + [OVL_ADAPTOR_MDP_RDMA5] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 5, &rdma }, + [OVL_ADAPTOR_MDP_RDMA6] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 6, &rdma }, + [OVL_ADAPTOR_MDP_RDMA7] =3D { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDM= A, 7, &rdma }, + [OVL_ADAPTOR_MERGE0] =3D { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 1, &me= rge }, + [OVL_ADAPTOR_MERGE1] =3D { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 2, &me= rge }, + [OVL_ADAPTOR_MERGE2] =3D { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 3, &me= rge }, + [OVL_ADAPTOR_MERGE3] =3D { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 4, &me= rge }, + [OVL_ADAPTOR_PADDING0] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 0, &padding }, + [OVL_ADAPTOR_PADDING1] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 1, &padding }, + [OVL_ADAPTOR_PADDING2] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 2, &padding }, + [OVL_ADAPTOR_PADDING3] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 3, &padding }, + [OVL_ADAPTOR_PADDING4] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 4, &padding }, + [OVL_ADAPTOR_PADDING5] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 5, &padding }, + [OVL_ADAPTOR_PADDING6] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 6, &padding }, + [OVL_ADAPTOR_PADDING7] =3D { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, = 7, &padding }, }; =20 void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx, @@ -431,7 +431,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, stru= ct mtk_mutex *mutex) for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { if (!ovl_adaptor->ovl_adaptor_comp[i]) continue; - mtk_mutex_add_comp(mutex, comp_matches[i].comp_id); + + mtk_mutex_add_trigger(mutex, + comp_matches[i].comp_type, + comp_matches[i].alias_id, + ovl_adaptor->mtx_trig_ids[i]); } } =20 @@ -443,32 +447,38 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, = struct mtk_mutex *mutex) for (i =3D 0; i < OVL_ADAPTOR_ID_MAX; i++) { if (!ovl_adaptor->ovl_adaptor_comp[i]) continue; - mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id); + + mtk_mutex_remove_trigger(mutex, + comp_matches[i].comp_type, + comp_matches[i].alias_id, + ovl_adaptor->mtx_trig_ids[i]); } } =20 -void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,= unsigned int next) +void mtk_ovl_adaptor_connect(struct mtk_ddp_comp *comp, struct device *mms= ys_dev, + struct mtk_ddp_comp *next) { - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_M= ERGE1); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_M= ERGE1); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_M= ERGE2); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHD= R_MIXER); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHD= R_MIXER); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHD= R_MIXER); - mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHD= R_MIXER); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_ETHDR_MIXER, 0, next->type, next= ->inst_id); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MDP_RDMA, 0, MTK_DISP_MERGE, 1); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MDP_RDMA, 1, MTK_DISP_MERGE, 1); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MDP_RDMA, 2, MTK_DISP_MERGE, 2); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 1, MTK_DISP_ETHDR_MIXER, = 0); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 2, MTK_DISP_ETHDR_MIXER, = 0); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 3, MTK_DISP_ETHDR_MIXER, = 0); + mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 4, MTK_DISP_ETHDR_MIXER, = 0); } =20 -void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_d= ev, unsigned int next) +void mtk_ovl_adaptor_disconnect(struct mtk_ddp_comp *comp, struct device *= mmsys_dev, + struct mtk_ddp_comp *next) { - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONEN= T_MERGE1); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONEN= T_MERGE1); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONEN= T_MERGE2); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE1, DDP_COMPONENT_E= THDR_MIXER); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_E= THDR_MIXER); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_E= THDR_MIXER); - mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_E= THDR_MIXER); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_ETHDR_MIXER, 0, next->type, n= ext->inst_id); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MDP_RDMA, 0, MTK_DISP_MERGE, = 1); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MDP_RDMA, 1, MTK_DISP_MERGE, = 1); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MDP_RDMA, 2, MTK_DISP_MERGE, = 2); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 1, MTK_DISP_ETHDR_MIXE= R, 0); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 2, MTK_DISP_ETHDR_MIXE= R, 0); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 3, MTK_DISP_ETHDR_MIXE= R, 0); + mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 4, MTK_DISP_ETHDR_MIXE= R, 0); } =20 static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node = *node, @@ -557,12 +567,12 @@ static int ovl_adaptor_comp_init(struct device *dev, = struct device_node *mutex_n parent =3D dev->parent->parent->of_node->parent; =20 for_each_child_of_node_scoped(parent, node) { - enum mtk_ovl_adaptor_comp_type type; - enum mtk_ddp_comp_id ddp_type; + enum mtk_ovl_adaptor_comp_type ovla_type; + enum mtk_ddp_comp_type ddp_type; + u8 ddp_inst_id, mtx_id; int id, ret; - u8 mtx_id; =20 - ret =3D ovl_adaptor_of_get_ddp_comp_type(node, &type); + ret =3D ovl_adaptor_of_get_ddp_comp_type(node, &ovla_type); if (ret) continue; =20 @@ -572,15 +582,17 @@ static int ovl_adaptor_comp_init(struct device *dev, = struct device_node *mutex_n continue; } =20 - id =3D ovl_adaptor_comp_get_id(dev, node, type); + id =3D ovl_adaptor_comp_get_id(dev, node, ovla_type); if (id < 0) { dev_warn(dev, "Skipping unknown component %pOF\n", node); continue; } =20 - ddp_type =3D comp_matches[id].comp_id; + ddp_type =3D comp_matches[id].comp_type; + ddp_inst_id =3D comp_matches[id].alias_id; mtx_id =3D mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(ddp_type, + ddp_inst_id, mutex_node); =20 comp_pdev =3D of_find_device_by_node(node); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index cdff5edd09da..f7cbf9b47672 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -102,8 +102,8 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_= driver_data =3D { }; =20 static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] =3D { - { 0, DDP_COMPONENT_DP_INTF0 }, - { 0, DDP_COMPONENT_DSI0 }, + { 0, MTK_DISP_DP_INTF, 0 }, + { 0, MTK_DISP_DSI, 0 }, }; =20 static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data =3D { @@ -245,7 +245,8 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev) return false; } =20 -static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int c= omp_id) +static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, + enum mtk_ddp_comp_type type, u8 inst_id) { const struct mtk_mmsys_driver_data *data =3D private->data; int i, j; @@ -254,7 +255,8 @@ static bool mtk_drm_find_mmsys_comp(struct mtk_drm_priv= ate *private, int comp_id const struct mtk_drm_path_definition *output_path =3D &data->output_path= s[i]; =20 for (j =3D 0; j < output_path->len; j++) { - if (output_path->comp[j].type !=3D comp_id) + if (output_path->comp[j].type !=3D type || + output_path->comp[j].inst_id !=3D inst_id) continue; =20 return true; @@ -263,7 +265,8 @@ static bool mtk_drm_find_mmsys_comp(struct mtk_drm_priv= ate *private, int comp_id =20 if (data->num_conn_routes) for (i =3D 0; i < data->num_conn_routes; i++) - if (data->conn_routes[i].route_ddp =3D=3D comp_id) + if (data->conn_routes[i].route_ddp_type =3D=3D type && + data->conn_routes[i].route_ddp_inst_id =3D=3D inst_id) return true; =20 return false; @@ -635,7 +638,7 @@ static int mtk_drm_of_get_ddp_comp_type(struct device_n= ode *node, enum mtk_ddp_c return 0; } =20 -static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node, +static int mtk_drm_of_get_ddp_ep_cid(struct device *dev, struct device_nod= e *node, int output_port, enum mtk_crtc_path crtc_path, struct device_node **next, struct mtk_drm_comp_definition *comp_def) @@ -666,7 +669,9 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_node= *node, ret =3D mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type); if (ret) { if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) { - comp_def->type =3D DDP_COMPONENT_DRM_OVL_ADAPTOR; + comp_def->type =3D MTK_DISP_OVL_ADAPTOR; + comp_def->inst_id =3D 0; + return 0; } return ret; @@ -677,7 +682,11 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_nod= e *node, return ret; =20 /* All ok! Pass the Component ID to the caller. */ - comp_def->type =3D ret; + comp_def->type =3D comp_type; + comp_def->inst_id =3D ret; + + dev_vdbg(dev, "Found component %pOF with Type:%u, HW Instance:%u\n", + ep_dev_node, comp_def->type, comp_def->inst_id); =20 return 0; } @@ -710,9 +719,9 @@ static int mtk_drm_of_ddp_path_build_one(struct device = *dev, enum mtk_crtc_path int ret; =20 /* Get the first entry for the temp_path array */ - ret =3D mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]); + ret =3D mtk_drm_of_get_ddp_ep_cid(dev, vdo, 0, cpath, &next, &temp_path[i= dx]); if (ret) { - if (next && temp_path[idx].type =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { + if (next && temp_path[idx].type =3D=3D MTK_DISP_OVL_ADAPTOR) { dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next); ovl_adaptor_comp_added =3D true; } else { @@ -732,9 +741,10 @@ static int mtk_drm_of_ddp_path_build_one(struct device= *dev, enum mtk_crtc_path */ do { prev =3D next; - ret =3D mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]= ); + ret =3D mtk_drm_of_get_ddp_ep_cid(dev, next, 1, cpath, &next, &temp_path= [idx]); of_node_put(prev); if (ret) { + dev_vdbg(dev, "Invalid comp reached with result %d\n", ret); of_node_put(next); break; } @@ -746,13 +756,13 @@ static int mtk_drm_of_ddp_path_build_one(struct devic= e *dev, enum mtk_crtc_path * to probe that component master driver of which only one instance * is needed and possible. */ - if (temp_path[idx].type =3D=3D DDP_COMPONENT_DRM_OVL_ADAPTOR) { + if (temp_path[idx].type =3D=3D MTK_DISP_OVL_ADAPTOR) { if (!ovl_adaptor_comp_added) ovl_adaptor_comp_added =3D true; else idx--; } - } while (++idx < DDP_COMPONENT_DRM_ID_MAX); + } while (++idx < MTK_DISP_CONTROLLER_MAX_COMP_PER_PATH); =20 /* * The device component might not be enabled: in that case, don't @@ -763,18 +773,13 @@ static int mtk_drm_of_ddp_path_build_one(struct devic= e *dev, enum mtk_crtc_path =20 /* If the last entry is not a final display output, the configuration is = wrong */ switch (temp_path[idx - 1].type) { - case DDP_COMPONENT_DP_INTF0: - case DDP_COMPONENT_DP_INTF1: - case DDP_COMPONENT_DPI0: - case DDP_COMPONENT_DPI1: - case DDP_COMPONENT_DSI0: - case DDP_COMPONENT_DSI1: - case DDP_COMPONENT_DSI2: - case DDP_COMPONENT_DSI3: + case MTK_DISP_DP_INTF: + case MTK_DISP_DPI: + case MTK_DISP_DSI: break; default: - dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=3D%d)= \n", - temp_path[idx - 1].type, ret); + dev_err(dev, "Invalid display hw pipeline. Last component: %u-%u (ret=3D= %d)\n", + temp_path[idx - 1].type, temp_path[idx - 1].inst_id, ret); return -EINVAL; } =20 @@ -852,7 +857,6 @@ static int mtk_drm_probe(struct platform_device *pdev) struct device_node *node; struct component_match *match =3D NULL; int ret; - int i; =20 private =3D devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); if (!private) @@ -901,7 +905,7 @@ static int mtk_drm_probe(struct platform_device *pdev) /* Iterate over sibling DISP function blocks */ for_each_child_of_node(phandle->parent, node) { enum mtk_ddp_comp_type comp_type; - int comp_id; + u8 comp_inst_id; =20 ret =3D mtk_drm_of_get_ddp_comp_type(node, &comp_type); if (ret) @@ -924,18 +928,16 @@ static int mtk_drm_probe(struct platform_device *pdev) continue; } =20 - comp_id =3D mtk_ddp_comp_get_id(node, comp_type); - if (comp_id < 0) { + comp_inst_id =3D mtk_ddp_comp_get_id(node, comp_type); + if (comp_inst_id < 0) { dev_warn(dev, "Skipping unknown component %pOF\n", node); continue; } =20 - if (!mtk_drm_find_mmsys_comp(private, comp_id)) + if (!mtk_drm_find_mmsys_comp(private, comp_type, comp_inst_id)) continue; =20 - private->comp_node[comp_id] =3D of_node_get(node); - /* * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, a= nd DPI * blocks have separate component platform drivers and initialize their = own @@ -949,7 +951,8 @@ static int mtk_drm_probe(struct platform_device *pdev) node); } =20 - ret =3D mtk_ddp_comp_init(dev, node, &private->hlist, comp_id); + ret =3D mtk_ddp_comp_init(dev, node, &private->hlist, + comp_type, comp_inst_id); if (ret) { of_node_put(node); goto err_node; @@ -970,7 +973,7 @@ static int mtk_drm_probe(struct platform_device *pdev) } =20 /* Bringup ovl_adaptor */ - if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR)) + if (mtk_drm_find_mmsys_comp(private, MTK_DISP_OVL_ADAPTOR, 0)) mtk_drm_legacy_ovl_adaptor_probe(dev, private, &match); =20 pm_runtime_enable(dev); @@ -987,21 +990,16 @@ static int mtk_drm_probe(struct platform_device *pdev) pm_runtime_disable(dev); err_node: of_node_put(private->mutex_node); - for (i =3D 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) - of_node_put(private->comp_node[i]); return ret; } =20 static void mtk_drm_remove(struct platform_device *pdev) { struct mtk_drm_private *private =3D platform_get_drvdata(pdev); - int i; =20 component_master_del(&pdev->dev, &mtk_drm_ops); pm_runtime_disable(&pdev->dev); of_node_put(private->mutex_node); - for (i =3D 0; i < DDP_COMPONENT_DRM_ID_MAX; i++) - of_node_put(private->comp_node[i]); } =20 static void mtk_drm_shutdown(struct platform_device *pdev) @@ -1085,4 +1083,6 @@ module_exit(mtk_drm_exit); =20 MODULE_AUTHOR("YT SHEN "); MODULE_DESCRIPTION("Mediatek SoC DRM driver"); +MODULE_IMPORT_NS("MTK_MMSYS"); +MODULE_IMPORT_NS("MTK_MUTEX"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/media= tek/mtk_drm_drv.h index 7dc208669c2e..d86175180e11 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h @@ -10,8 +10,6 @@ #include "mtk_ddp_comp.h" =20 #define MAX_CONNECTOR 2 -#define DDP_COMPONENT_DRM_OVL_ADAPTOR (DDP_COMPONENT_ID_MAX + 1) -#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVL_ADAPTOR + 1) =20 enum mtk_crtc_path { CRTC_MAIN, @@ -30,11 +28,13 @@ struct regmap; =20 struct mtk_drm_route { const unsigned int crtc_id; - const unsigned int route_ddp; + const enum mtk_ddp_comp_type route_ddp_type; + const u8 route_ddp_inst_id; }; =20 struct mtk_drm_comp_definition { - enum mtk_ddp_comp_id type; + enum mtk_ddp_comp_type type; + u8 inst_id; }; =20 struct mtk_drm_path_definition { @@ -66,7 +66,6 @@ struct mtk_drm_private { struct device *mutex_dev; struct device *mmsys_dev; struct mtk_drm_comp_list hlist; - struct device_node *comp_node[DDP_COMPONENT_DRM_ID_MAX]; struct mtk_mmsys_driver_data *data; struct drm_atomic_commit *suspend_state; unsigned int mbox_index; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c b/drivers/gpu/drm/me= diatek/mtk_drm_legacy.c index d6e3ab7e08ba..801e0ab43ff5 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c @@ -248,16 +248,16 @@ struct mtk_drm_legacy_mtx_data { }; =20 static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_BLS }, - { DDP_COMPONENT_DSI0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_BLS, 0 }, + { MTK_DISP_DSI, 0 }, }; =20 static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, + { MTK_DISP_RDMA, 1 }, + { MTK_DISP_DPI, 0 }, }; =20 struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] =3D { @@ -272,29 +272,29 @@ struct mtk_drm_path_definition mt2701_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_OD0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_DPI0 }, - { DDP_COMPONENT_PWM0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_OD, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_DPI, 0 }, + { MTK_DISP_PWM, 0 }, }; =20 static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL1 }, - { DDP_COMPONENT_COLOR1 }, - { DDP_COMPONENT_AAL1 }, - { DDP_COMPONENT_OD1 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI1 }, - { DDP_COMPONENT_PWM1 }, + { MTK_DISP_OVL, 1 }, + { MTK_DISP_COLOR, 1 }, + { MTK_DISP_AAL, 1 }, + { MTK_DISP_OD, 1 }, + { MTK_DISP_RDMA, 1 }, + { MTK_DISP_DPI, 1 }, + { MTK_DISP_PWM, 1 }, }; =20 static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] =3D { - { DDP_COMPONENT_RDMA2 }, - { DDP_COMPONENT_DSI3 }, - { DDP_COMPONENT_PWM2 }, + { MTK_DISP_RDMA, 2 }, + { MTK_DISP_DSI, 3 }, + { MTK_DISP_PWM, 2 }, }; =20 struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] =3D { @@ -313,16 +313,16 @@ struct mtk_drm_path_definition mt2712_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_BLS }, - { DDP_COMPONENT_DPI0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_BLS, 0 }, + { MTK_DISP_DPI, 0 }, }; =20 static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DSI0 }, + { MTK_DISP_RDMA, 1 }, + { MTK_DISP_DSI, 0 }, }; =20 struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] =3D { @@ -337,14 +337,14 @@ struct mtk_drm_path_definition mt7623_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_DSI0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_CCORR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_DITHER, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_DSI, 0 }, }; =20 struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] =3D { @@ -355,22 +355,22 @@ struct mtk_drm_path_definition mt8167_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_OD0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_UFOE }, - { DDP_COMPONENT_DSI0 }, - { DDP_COMPONENT_PWM0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_OD, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_UFOE, 0 }, + { MTK_DISP_DSI, 0 }, + { MTK_DISP_PWM, 0 }, }; =20 static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL1 }, - { DDP_COMPONENT_COLOR1 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, + { MTK_DISP_OVL, 1 }, + { MTK_DISP_COLOR, 1 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_RDMA, 1 }, + { MTK_DISP_DPI, 0 }, }; =20 struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] =3D { @@ -385,21 +385,21 @@ struct mtk_drm_path_definition mt8173_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_OVL_2L, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_CCORR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_DITHER, 0 }, + { MTK_DISP_DSI, 0 }, }; =20 static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL_2L1 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, + { MTK_DISP_OVL_2L, 1 }, + { MTK_DISP_RDMA, 1 }, + { MTK_DISP_DPI, 0 }, }; =20 struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] =3D { @@ -414,21 +414,21 @@ struct mtk_drm_path_definition mt8183_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_CCORR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_POSTMASK, 0 }, + { MTK_DISP_DITHER, 0 }, + { MTK_DISP_DSI, 0 }, }; =20 static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA1 }, - { DDP_COMPONENT_DPI0 }, + { MTK_DISP_OVL_2L, 0 }, + { MTK_DISP_RDMA, 1 }, + { MTK_DISP_DPI, 0 }, }; =20 struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] =3D { @@ -443,14 +443,14 @@ struct mtk_drm_path_definition mt8186_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_CCORR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_POSTMASK, 0 }, + { MTK_DISP_DITHER, 0 }, }; =20 struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] =3D { @@ -461,22 +461,22 @@ struct mtk_drm_path_definition mt8188_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_OVL_2L0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_POSTMASK0 }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSI0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_OVL_2L, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_CCORR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_POSTMASK, 0 }, + { MTK_DISP_DITHER, 0 }, + { MTK_DISP_DSI, 0 }, }; =20 static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_OVL_2L2 }, - { DDP_COMPONENT_RDMA4 }, - { DDP_COMPONENT_DPI0 }, + { MTK_DISP_OVL_2L, 2 }, + { MTK_DISP_RDMA, 4 }, + { MTK_DISP_DPI, 0 }, }; =20 struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] =3D { @@ -491,22 +491,22 @@ struct mtk_drm_path_definition mt8192_legacy_paths[MA= X_CRTC] =3D { }; =20 static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] =3D { - { DDP_COMPONENT_OVL0 }, - { DDP_COMPONENT_RDMA0 }, - { DDP_COMPONENT_COLOR0 }, - { DDP_COMPONENT_CCORR }, - { DDP_COMPONENT_AAL0 }, - { DDP_COMPONENT_GAMMA }, - { DDP_COMPONENT_DITHER0 }, - { DDP_COMPONENT_DSC0 }, - { DDP_COMPONENT_MERGE0 }, - { DDP_COMPONENT_DP_INTF0 }, + { MTK_DISP_OVL, 0 }, + { MTK_DISP_RDMA, 0 }, + { MTK_DISP_COLOR, 0 }, + { MTK_DISP_CCORR, 0 }, + { MTK_DISP_AAL, 0 }, + { MTK_DISP_GAMMA, 0 }, + { MTK_DISP_DITHER, 0 }, + { MTK_DISP_DSC, 0 }, + { MTK_DISP_MERGE, 0 }, + { MTK_DISP_DP_INTF, 0 }, }; =20 static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] =3D { - { DDP_COMPONENT_DRM_OVL_ADAPTOR }, - { DDP_COMPONENT_MERGE5 }, - { DDP_COMPONENT_DP_INTF1 }, + { MTK_DISP_OVL_ADAPTOR, 0 }, + { MTK_DISP_MERGE, 5 }, + { MTK_DISP_DP_INTF, 1 }, }; =20 struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] =3D { @@ -524,12 +524,12 @@ struct mtk_drm_path_definition mt8195_vdo1_legacy_pat= hs[MAX_CRTC] =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt2701_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_BLS }, MT2701_MUTEX_MOD_DISP_BLS }, - { { DDP_COMPONENT_COLOR0 }, MT2701_MUTEX_MOD_DISP_COLOR }, - { { DDP_COMPONENT_OVL0 }, MT2701_MUTEX_MOD_DISP_OVL }, - { { DDP_COMPONENT_RDMA0 }, MT2701_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT2701_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_WDMA0 }, MT2701_MUTEX_MOD_DISP_WDMA }, + { { MTK_DISP_BLS, 0 }, MT2701_MUTEX_MOD_DISP_BLS }, + { { MTK_DISP_COLOR, 0 }, MT2701_MUTEX_MOD_DISP_COLOR }, + { { MTK_DISP_OVL, 0 }, MT2701_MUTEX_MOD_DISP_OVL }, + { { MTK_DISP_RDMA, 0 }, MT2701_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT2701_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_WDMA, 0 }, MT2701_MUTEX_MOD_DISP_WDMA }, }; =20 const struct mtk_drm_legacy_mtx_data mt2701_legacy_mtx_data =3D { @@ -538,23 +538,23 @@ const struct mtk_drm_legacy_mtx_data mt2701_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt2712_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT2712_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_AAL1 }, MT2712_MUTEX_MOD2_DISP_AAL1 }, - { { DDP_COMPONENT_COLOR0 }, MT2712_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_COLOR1 }, MT2712_MUTEX_MOD_DISP_COLOR1 }, - { { DDP_COMPONENT_OD0 }, MT2712_MUTEX_MOD_DISP_OD0 }, - { { DDP_COMPONENT_OD1 }, MT2712_MUTEX_MOD2_DISP_OD1 }, - { { DDP_COMPONENT_OVL0 }, MT2712_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL1 }, MT2712_MUTEX_MOD_DISP_OVL1 }, - { { DDP_COMPONENT_PWM0 }, MT2712_MUTEX_MOD_DISP_PWM0 }, - { { DDP_COMPONENT_PWM1 }, MT2712_MUTEX_MOD_DISP_PWM1 }, - { { DDP_COMPONENT_PWM2 }, MT2712_MUTEX_MOD_DISP_PWM2 }, - { { DDP_COMPONENT_RDMA0 }, MT2712_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT2712_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_RDMA2 }, MT2712_MUTEX_MOD_DISP_RDMA2 }, - { { DDP_COMPONENT_UFOE }, MT2712_MUTEX_MOD_DISP_UFOE }, - { { DDP_COMPONENT_WDMA0 }, MT2712_MUTEX_MOD_DISP_WDMA0 }, - { { DDP_COMPONENT_WDMA1 }, MT2712_MUTEX_MOD_DISP_WDMA1 }, + { { MTK_DISP_AAL, 0 }, MT2712_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_AAL, 1 }, MT2712_MUTEX_MOD2_DISP_AAL1 }, + { { MTK_DISP_COLOR, 0 }, MT2712_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_COLOR, 1 }, MT2712_MUTEX_MOD_DISP_COLOR1 }, + { { MTK_DISP_OD, 0 }, MT2712_MUTEX_MOD_DISP_OD0 }, + { { MTK_DISP_OD, 1 }, MT2712_MUTEX_MOD2_DISP_OD1 }, + { { MTK_DISP_OVL, 0 }, MT2712_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL, 1 }, MT2712_MUTEX_MOD_DISP_OVL1 }, + { { MTK_DISP_PWM, 0 }, MT2712_MUTEX_MOD_DISP_PWM0 }, + { { MTK_DISP_PWM, 1 }, MT2712_MUTEX_MOD_DISP_PWM1 }, + { { MTK_DISP_PWM, 2 }, MT2712_MUTEX_MOD_DISP_PWM2 }, + { { MTK_DISP_RDMA, 0 }, MT2712_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT2712_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_RDMA, 2 }, MT2712_MUTEX_MOD_DISP_RDMA2 }, + { { MTK_DISP_UFOE, 0 }, MT2712_MUTEX_MOD_DISP_UFOE }, + { { MTK_DISP_WDMA, 0 }, MT2712_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_WDMA, 1 }, MT2712_MUTEX_MOD_DISP_WDMA1 }, }; =20 const struct mtk_drm_legacy_mtx_data mt2712_legacy_mtx_data =3D { @@ -563,31 +563,31 @@ const struct mtk_drm_legacy_mtx_data mt2712_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt6893_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT6893_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_AAL1 }, MT6893_MUTEX_MOD_DISP_AAL1 }, - { { DDP_COMPONENT_CCORR }, MT6893_MUTEX_MOD_DISP_CCORR0 }, - { { DDP_COMPONENT_COLOR0 }, MT6893_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_COLOR1 }, MT6893_MUTEX_MOD_DISP_COLOR1 }, - { { DDP_COMPONENT_DITHER0 }, MT6893_MUTEX_MOD_DISP_DITHER0 }, - { { DDP_COMPONENT_DITHER1 }, MT6893_MUTEX_MOD_DISP_DITHER1 }, - { { DDP_COMPONENT_DP_INTF0 }, MT6893_MUTEX_MOD_DISP_DP }, - { { DDP_COMPONENT_DSC0 }, MT6893_MUTEX_MOD_DISP_DSC0 }, - { { DDP_COMPONENT_DSI0 }, MT6893_MUTEX_MOD_DISP_DSI0 }, - { { DDP_COMPONENT_DSI1 }, MT6893_MUTEX_MOD_DISP_DSI1 }, - { { DDP_COMPONENT_GAMMA }, MT6893_MUTEX_MOD_DISP_GAMMA0 }, - { { DDP_COMPONENT_MERGE1 }, MT6893_MUTEX_MOD_DISP_MERGE1 }, - { { DDP_COMPONENT_OVL0 }, MT6893_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL1 }, MT6893_MUTEX_MOD_DISP_OVL1 }, - { { DDP_COMPONENT_OVL_2L0 }, MT6893_MUTEX_MOD_DISP_OVL0_2L }, - { { DDP_COMPONENT_OVL_2L1 }, MT6893_MUTEX_MOD_DISP_OVL1_2L }, - { { DDP_COMPONENT_OVL_2L2 }, MT6893_MUTEX_MOD_DISP_OVL2 }, - { { DDP_COMPONENT_POSTMASK0 }, MT6893_MUTEX_MOD_DISP_POSTMASK0 }, - { { DDP_COMPONENT_PWM0 }, MT6893_MUTEX_MOD_DISP_PWM0 }, - { { DDP_COMPONENT_RDMA0 }, MT6893_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT6893_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_RDMA4 }, MT6893_MUTEX_MOD_DISP_RDMA4 }, - { { DDP_COMPONENT_WDMA0 }, MT6893_MUTEX_MOD_DISP_WDMA0 }, - { { DDP_COMPONENT_WDMA1 }, MT6893_MUTEX_MOD_DISP_WDMA1 }, + { { MTK_DISP_AAL, 0 }, MT6893_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_AAL, 1 }, MT6893_MUTEX_MOD_DISP_AAL1 }, + { { MTK_DISP_CCORR, 0 }, MT6893_MUTEX_MOD_DISP_CCORR0 }, + { { MTK_DISP_COLOR, 0 }, MT6893_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_COLOR, 1 }, MT6893_MUTEX_MOD_DISP_COLOR1 }, + { { MTK_DISP_DITHER, 0 }, MT6893_MUTEX_MOD_DISP_DITHER0 }, + { { MTK_DISP_DITHER, 1 }, MT6893_MUTEX_MOD_DISP_DITHER1 }, + { { MTK_DISP_DP_INTF, 0 }, MT6893_MUTEX_MOD_DISP_DP }, + { { MTK_DISP_DSC, 0 }, MT6893_MUTEX_MOD_DISP_DSC0 }, + { { MTK_DISP_DSI, 0 }, MT6893_MUTEX_MOD_DISP_DSI0 }, + { { MTK_DISP_DSI, 1 }, MT6893_MUTEX_MOD_DISP_DSI1 }, + { { MTK_DISP_GAMMA, 0 }, MT6893_MUTEX_MOD_DISP_GAMMA0 }, + { { MTK_DISP_MERGE, 1 }, MT6893_MUTEX_MOD_DISP_MERGE1 }, + { { MTK_DISP_OVL, 0 }, MT6893_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL, 1 }, MT6893_MUTEX_MOD_DISP_OVL1 }, + { { MTK_DISP_OVL_2L, 0 }, MT6893_MUTEX_MOD_DISP_OVL0_2L }, + { { MTK_DISP_OVL_2L, 1 }, MT6893_MUTEX_MOD_DISP_OVL1_2L }, + { { MTK_DISP_OVL_2L, 2 }, MT6893_MUTEX_MOD_DISP_OVL2 }, + { { MTK_DISP_POSTMASK, 0 }, MT6893_MUTEX_MOD_DISP_POSTMASK0 }, + { { MTK_DISP_PWM, 0 }, MT6893_MUTEX_MOD_DISP_PWM0 }, + { { MTK_DISP_RDMA, 0 }, MT6893_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT6893_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_RDMA, 4 }, MT6893_MUTEX_MOD_DISP_RDMA4 }, + { { MTK_DISP_WDMA, 0 }, MT6893_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_WDMA, 1 }, MT6893_MUTEX_MOD_DISP_WDMA1 }, }; =20 const struct mtk_drm_legacy_mtx_data mt6893_legacy_mtx_data =3D { @@ -596,18 +596,18 @@ const struct mtk_drm_legacy_mtx_data mt6893_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8167_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT8167_MUTEX_MOD_DISP_AAL }, - { { DDP_COMPONENT_CCORR }, MT8167_MUTEX_MOD_DISP_CCORR }, - { { DDP_COMPONENT_COLOR0 }, MT8167_MUTEX_MOD_DISP_COLOR }, - { { DDP_COMPONENT_DITHER0 }, MT8167_MUTEX_MOD_DISP_DITHER }, - { { DDP_COMPONENT_GAMMA }, MT8167_MUTEX_MOD_DISP_GAMMA }, - { { DDP_COMPONENT_OVL0 }, MT8167_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL1 }, MT8167_MUTEX_MOD_DISP_OVL1 }, - { { DDP_COMPONENT_PWM0 }, MT8167_MUTEX_MOD_DISP_PWM }, - { { DDP_COMPONENT_RDMA0 }, MT8167_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT8167_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_UFOE }, MT8167_MUTEX_MOD_DISP_UFOE }, - { { DDP_COMPONENT_WDMA0 }, MT8167_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_AAL, 0 }, MT8167_MUTEX_MOD_DISP_AAL }, + { { MTK_DISP_CCORR, 0 }, MT8167_MUTEX_MOD_DISP_CCORR }, + { { MTK_DISP_COLOR, 0 }, MT8167_MUTEX_MOD_DISP_COLOR }, + { { MTK_DISP_DITHER, 0 }, MT8167_MUTEX_MOD_DISP_DITHER }, + { { MTK_DISP_GAMMA, 0 }, MT8167_MUTEX_MOD_DISP_GAMMA }, + { { MTK_DISP_OVL, 0 }, MT8167_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL, 1 }, MT8167_MUTEX_MOD_DISP_OVL1 }, + { { MTK_DISP_PWM, 0 }, MT8167_MUTEX_MOD_DISP_PWM }, + { { MTK_DISP_RDMA, 0 }, MT8167_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT8167_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_UFOE, 0 }, MT8167_MUTEX_MOD_DISP_UFOE }, + { { MTK_DISP_WDMA, 0 }, MT8167_MUTEX_MOD_DISP_WDMA0 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8167_legacy_mtx_data =3D { @@ -616,21 +616,21 @@ const struct mtk_drm_legacy_mtx_data mt8167_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8173_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT8173_MUTEX_MOD_DISP_AAL }, - { { DDP_COMPONENT_COLOR0 }, MT8173_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_COLOR1 }, MT8173_MUTEX_MOD_DISP_COLOR1 }, - { { DDP_COMPONENT_GAMMA }, MT8173_MUTEX_MOD_DISP_GAMMA }, - { { DDP_COMPONENT_OD0 }, MT8173_MUTEX_MOD_DISP_OD }, - { { DDP_COMPONENT_OVL0 }, MT8173_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL1 }, MT8173_MUTEX_MOD_DISP_OVL1 }, - { { DDP_COMPONENT_PWM0 }, MT8173_MUTEX_MOD_DISP_PWM0 }, - { { DDP_COMPONENT_PWM1 }, MT8173_MUTEX_MOD_DISP_PWM1 }, - { { DDP_COMPONENT_RDMA0 }, MT8173_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT8173_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_RDMA2 }, MT8173_MUTEX_MOD_DISP_RDMA2 }, - { { DDP_COMPONENT_UFOE }, MT8173_MUTEX_MOD_DISP_UFOE }, - { { DDP_COMPONENT_WDMA0 }, MT8173_MUTEX_MOD_DISP_WDMA0 }, - { { DDP_COMPONENT_WDMA1 }, MT8173_MUTEX_MOD_DISP_WDMA1 }, + { { MTK_DISP_AAL, 0 }, MT8173_MUTEX_MOD_DISP_AAL }, + { { MTK_DISP_COLOR, 0 }, MT8173_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_COLOR, 1 }, MT8173_MUTEX_MOD_DISP_COLOR1 }, + { { MTK_DISP_GAMMA, 0 }, MT8173_MUTEX_MOD_DISP_GAMMA }, + { { MTK_DISP_OD, 0 }, MT8173_MUTEX_MOD_DISP_OD }, + { { MTK_DISP_OVL, 0 }, MT8173_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL, 1 }, MT8173_MUTEX_MOD_DISP_OVL1 }, + { { MTK_DISP_PWM, 0 }, MT8173_MUTEX_MOD_DISP_PWM0 }, + { { MTK_DISP_PWM, 1 }, MT8173_MUTEX_MOD_DISP_PWM1 }, + { { MTK_DISP_RDMA, 0 }, MT8173_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT8173_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_RDMA, 2 }, MT8173_MUTEX_MOD_DISP_RDMA2 }, + { { MTK_DISP_UFOE, 0 }, MT8173_MUTEX_MOD_DISP_UFOE }, + { { MTK_DISP_WDMA, 0 }, MT8173_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_WDMA, 1 }, MT8173_MUTEX_MOD_DISP_WDMA1 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8173_legacy_mtx_data =3D { @@ -639,17 +639,17 @@ const struct mtk_drm_legacy_mtx_data mt8173_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8183_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT8183_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_CCORR }, MT8183_MUTEX_MOD_DISP_CCORR0 }, - { { DDP_COMPONENT_COLOR0 }, MT8183_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_DITHER0 }, MT8183_MUTEX_MOD_DISP_DITHER0 }, - { { DDP_COMPONENT_GAMMA }, MT8183_MUTEX_MOD_DISP_GAMMA0 }, - { { DDP_COMPONENT_OVL0 }, MT8183_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL_2L0 }, MT8183_MUTEX_MOD_DISP_OVL0_2L }, - { { DDP_COMPONENT_OVL_2L1 }, MT8183_MUTEX_MOD_DISP_OVL1_2L }, - { { DDP_COMPONENT_RDMA0 }, MT8183_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT8183_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_WDMA0 }, MT8183_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_AAL, 0 }, MT8183_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_CCORR, 0 }, MT8183_MUTEX_MOD_DISP_CCORR0 }, + { { MTK_DISP_COLOR, 0 }, MT8183_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_DITHER, 0 }, MT8183_MUTEX_MOD_DISP_DITHER0 }, + { { MTK_DISP_GAMMA, 0 }, MT8183_MUTEX_MOD_DISP_GAMMA0 }, + { { MTK_DISP_OVL, 0 }, MT8183_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL_2L, 0 }, MT8183_MUTEX_MOD_DISP_OVL0_2L }, + { { MTK_DISP_OVL_2L, 1 }, MT8183_MUTEX_MOD_DISP_OVL1_2L }, + { { MTK_DISP_RDMA, 0 }, MT8183_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT8183_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_WDMA, 0 }, MT8183_MUTEX_MOD_DISP_WDMA0 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8183_legacy_mtx_data =3D { @@ -658,16 +658,16 @@ const struct mtk_drm_legacy_mtx_data mt8183_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8186_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT8186_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_CCORR }, MT8186_MUTEX_MOD_DISP_CCORR0 }, - { { DDP_COMPONENT_COLOR0 }, MT8186_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_DITHER0 }, MT8186_MUTEX_MOD_DISP_DITHER0 }, - { { DDP_COMPONENT_GAMMA }, MT8186_MUTEX_MOD_DISP_GAMMA0 }, - { { DDP_COMPONENT_OVL0 }, MT8186_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL_2L0 }, MT8186_MUTEX_MOD_DISP_OVL0_2L }, - { { DDP_COMPONENT_POSTMASK0 }, MT8186_MUTEX_MOD_DISP_POSTMASK0 }, - { { DDP_COMPONENT_RDMA0 }, MT8186_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT8186_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_AAL, 0 }, MT8186_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_CCORR, 0 }, MT8186_MUTEX_MOD_DISP_CCORR0 }, + { { MTK_DISP_COLOR, 0 }, MT8186_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_DITHER, 0 }, MT8186_MUTEX_MOD_DISP_DITHER0 }, + { { MTK_DISP_GAMMA, 0 }, MT8186_MUTEX_MOD_DISP_GAMMA0 }, + { { MTK_DISP_OVL, 0 }, MT8186_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL_2L, 0 }, MT8186_MUTEX_MOD_DISP_OVL0_2L }, + { { MTK_DISP_POSTMASK, 0 }, MT8186_MUTEX_MOD_DISP_POSTMASK0 }, + { { MTK_DISP_RDMA, 0 }, MT8186_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT8186_MUTEX_MOD_DISP_RDMA1 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8186_legacy_mtx_data =3D { @@ -676,44 +676,44 @@ const struct mtk_drm_legacy_mtx_data mt8186_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8188_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_OVL0 }, MT8188_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_WDMA0 }, MT8188_MUTEX_MOD_DISP_WDMA0 }, - { { DDP_COMPONENT_RDMA0 }, MT8188_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_COLOR0 }, MT8188_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_CCORR }, MT8188_MUTEX_MOD_DISP_CCORR0 }, - { { DDP_COMPONENT_AAL0 }, MT8188_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_GAMMA }, MT8188_MUTEX_MOD_DISP_GAMMA0 }, - { { DDP_COMPONENT_POSTMASK0 }, MT8188_MUTEX_MOD_DISP_POSTMASK0 }, - { { DDP_COMPONENT_DITHER0 }, MT8188_MUTEX_MOD_DISP_DITHER0 }, - { { DDP_COMPONENT_MERGE0 }, MT8188_MUTEX_MOD_DISP_VPP_MERGE }, - { { DDP_COMPONENT_DSC0 }, MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 }, - { { DDP_COMPONENT_DSI0 }, MT8188_MUTEX_MOD_DISP_DSI0 }, - { { DDP_COMPONENT_PWM0 }, MT8188_MUTEX_MOD2_DISP_PWM0 }, - { { DDP_COMPONENT_DP_INTF0 }, MT8188_MUTEX_MOD_DISP_DP_INTF0 }, - { { DDP_COMPONENT_DP_INTF1 }, MT8188_MUTEX_MOD_DISP1_DP_INTF1 }, - { { DDP_COMPONENT_DPI1 }, MT8188_MUTEX_MOD_DISP1_DPI1 }, - { { DDP_COMPONENT_ETHDR_MIXER }, MT8188_MUTEX_MOD_DISP1_DISP_MIXER }, - { { DDP_COMPONENT_MDP_RDMA0 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 }, - { { DDP_COMPONENT_MDP_RDMA1 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 }, - { { DDP_COMPONENT_MDP_RDMA2 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 }, - { { DDP_COMPONENT_MDP_RDMA3 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 }, - { { DDP_COMPONENT_MDP_RDMA4 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 }, - { { DDP_COMPONENT_MDP_RDMA5 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 }, - { { DDP_COMPONENT_MDP_RDMA6 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 }, - { { DDP_COMPONENT_MDP_RDMA7 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 }, - { { DDP_COMPONENT_PADDING0 }, MT8188_MUTEX_MOD_DISP1_PADDING0 }, - { { DDP_COMPONENT_PADDING1 }, MT8188_MUTEX_MOD_DISP1_PADDING1 }, - { { DDP_COMPONENT_PADDING2 }, MT8188_MUTEX_MOD_DISP1_PADDING2 }, - { { DDP_COMPONENT_PADDING3 }, MT8188_MUTEX_MOD_DISP1_PADDING3 }, - { { DDP_COMPONENT_PADDING4 }, MT8188_MUTEX_MOD_DISP1_PADDING4 }, - { { DDP_COMPONENT_PADDING5 }, MT8188_MUTEX_MOD_DISP1_PADDING5 }, - { { DDP_COMPONENT_PADDING6 }, MT8188_MUTEX_MOD_DISP1_PADDING6 }, - { { DDP_COMPONENT_PADDING7 }, MT8188_MUTEX_MOD_DISP1_PADDING7 }, - { { DDP_COMPONENT_MERGE1 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 }, - { { DDP_COMPONENT_MERGE2 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 }, - { { DDP_COMPONENT_MERGE3 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 }, - { { DDP_COMPONENT_MERGE4 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 }, - { { DDP_COMPONENT_MERGE5 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 }, + { { MTK_DISP_OVL, 0 }, MT8188_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_WDMA, 0 }, MT8188_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_RDMA, 0 }, MT8188_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_COLOR, 0 }, MT8188_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_CCORR, 0 }, MT8188_MUTEX_MOD_DISP_CCORR0 }, + { { MTK_DISP_AAL, 0 }, MT8188_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_GAMMA, 0 }, MT8188_MUTEX_MOD_DISP_GAMMA0 }, + { { MTK_DISP_POSTMASK, 0 }, MT8188_MUTEX_MOD_DISP_POSTMASK0 }, + { { MTK_DISP_DITHER, 0 }, MT8188_MUTEX_MOD_DISP_DITHER0 }, + { { MTK_DISP_MERGE, 0 }, MT8188_MUTEX_MOD_DISP_VPP_MERGE }, + { { MTK_DISP_DSC, 0 }, MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 }, + { { MTK_DISP_DSI, 0 }, MT8188_MUTEX_MOD_DISP_DSI0 }, + { { MTK_DISP_PWM, 0 }, MT8188_MUTEX_MOD2_DISP_PWM0 }, + { { MTK_DISP_DP_INTF, 0 }, MT8188_MUTEX_MOD_DISP_DP_INTF0 }, + { { MTK_DISP_DP_INTF, 1 }, MT8188_MUTEX_MOD_DISP1_DP_INTF1 }, + { { MTK_DISP_DPI, 1 }, MT8188_MUTEX_MOD_DISP1_DPI1 }, + { { MTK_DISP_ETHDR_MIXER, 0 }, MT8188_MUTEX_MOD_DISP1_DISP_MIXER }, + { { MTK_DISP_MDP_RDMA, 0 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 }, + { { MTK_DISP_MDP_RDMA, 1 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 }, + { { MTK_DISP_MDP_RDMA, 2 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 }, + { { MTK_DISP_MDP_RDMA, 3 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 }, + { { MTK_DISP_MDP_RDMA, 4 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 }, + { { MTK_DISP_MDP_RDMA, 5 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 }, + { { MTK_DISP_MDP_RDMA, 6 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 }, + { { MTK_DISP_MDP_RDMA, 7 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 }, + { { MTK_DISP_PADDING, 0 }, MT8188_MUTEX_MOD_DISP1_PADDING0 }, + { { MTK_DISP_PADDING, 1 }, MT8188_MUTEX_MOD_DISP1_PADDING1 }, + { { MTK_DISP_PADDING, 2 }, MT8188_MUTEX_MOD_DISP1_PADDING2 }, + { { MTK_DISP_PADDING, 3 }, MT8188_MUTEX_MOD_DISP1_PADDING3 }, + { { MTK_DISP_PADDING, 4 }, MT8188_MUTEX_MOD_DISP1_PADDING4 }, + { { MTK_DISP_PADDING, 5 }, MT8188_MUTEX_MOD_DISP1_PADDING5 }, + { { MTK_DISP_PADDING, 6 }, MT8188_MUTEX_MOD_DISP1_PADDING6 }, + { { MTK_DISP_PADDING, 7 }, MT8188_MUTEX_MOD_DISP1_PADDING7 }, + { { MTK_DISP_MERGE, 1 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 }, + { { MTK_DISP_MERGE, 2 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 }, + { { MTK_DISP_MERGE, 3 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 }, + { { MTK_DISP_MERGE, 4 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 }, + { { MTK_DISP_MERGE, 5 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8188_legacy_mtx_data =3D { @@ -722,17 +722,17 @@ const struct mtk_drm_legacy_mtx_data mt8188_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8192_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT8192_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_CCORR }, MT8192_MUTEX_MOD_DISP_CCORR0 }, - { { DDP_COMPONENT_COLOR0 }, MT8192_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_DITHER0 }, MT8192_MUTEX_MOD_DISP_DITHER0 }, - { { DDP_COMPONENT_GAMMA }, MT8192_MUTEX_MOD_DISP_GAMMA0 }, - { { DDP_COMPONENT_POSTMASK0 }, MT8192_MUTEX_MOD_DISP_POSTMASK0 }, - { { DDP_COMPONENT_OVL0 }, MT8192_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL_2L0 }, MT8192_MUTEX_MOD_DISP_OVL0_2L }, - { { DDP_COMPONENT_OVL_2L2 }, MT8192_MUTEX_MOD_DISP_OVL2_2L }, - { { DDP_COMPONENT_RDMA0 }, MT8192_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA4 }, MT8192_MUTEX_MOD_DISP_RDMA4 }, + { { MTK_DISP_AAL, 0 }, MT8192_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_CCORR, 0 }, MT8192_MUTEX_MOD_DISP_CCORR0 }, + { { MTK_DISP_COLOR, 0 }, MT8192_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_DITHER, 0 }, MT8192_MUTEX_MOD_DISP_DITHER0 }, + { { MTK_DISP_GAMMA, 0 }, MT8192_MUTEX_MOD_DISP_GAMMA0 }, + { { MTK_DISP_POSTMASK, 0 }, MT8192_MUTEX_MOD_DISP_POSTMASK0 }, + { { MTK_DISP_OVL, 0 }, MT8192_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL_2L, 0 }, MT8192_MUTEX_MOD_DISP_OVL0_2L }, + { { MTK_DISP_OVL_2L, 2 }, MT8192_MUTEX_MOD_DISP_OVL2_2L }, + { { MTK_DISP_RDMA, 0 }, MT8192_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 4 }, MT8192_MUTEX_MOD_DISP_RDMA4 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8192_legacy_mtx_data =3D { @@ -741,34 +741,34 @@ const struct mtk_drm_legacy_mtx_data mt8192_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8195_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_OVL0 }, MT8195_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_WDMA0 }, MT8195_MUTEX_MOD_DISP_WDMA0 }, - { { DDP_COMPONENT_RDMA0 }, MT8195_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_COLOR0 }, MT8195_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_CCORR }, MT8195_MUTEX_MOD_DISP_CCORR0 }, - { { DDP_COMPONENT_AAL0 }, MT8195_MUTEX_MOD_DISP_AAL0 }, - { { DDP_COMPONENT_GAMMA }, MT8195_MUTEX_MOD_DISP_GAMMA0 }, - { { DDP_COMPONENT_DITHER0 }, MT8195_MUTEX_MOD_DISP_DITHER0 }, - { { DDP_COMPONENT_MERGE0 }, MT8195_MUTEX_MOD_DISP_VPP_MERGE }, - { { DDP_COMPONENT_DSC0 }, MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 }, - { { DDP_COMPONENT_DSI0 }, MT8195_MUTEX_MOD_DISP_DSI0 }, - { { DDP_COMPONENT_PWM0 }, MT8195_MUTEX_MOD_DISP_PWM0 }, - { { DDP_COMPONENT_DP_INTF0 }, MT8195_MUTEX_MOD_DISP_DP_INTF0 }, - { { DDP_COMPONENT_MDP_RDMA0 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 }, - { { DDP_COMPONENT_MDP_RDMA1 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 }, - { { DDP_COMPONENT_MDP_RDMA2 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 }, - { { DDP_COMPONENT_MDP_RDMA3 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 }, - { { DDP_COMPONENT_MDP_RDMA4 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 }, - { { DDP_COMPONENT_MDP_RDMA5 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 }, - { { DDP_COMPONENT_MDP_RDMA6 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 }, - { { DDP_COMPONENT_MDP_RDMA7 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 }, - { { DDP_COMPONENT_MERGE1 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 }, - { { DDP_COMPONENT_MERGE2 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 }, - { { DDP_COMPONENT_MERGE3 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 }, - { { DDP_COMPONENT_MERGE4 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 }, - { { DDP_COMPONENT_ETHDR_MIXER }, MT8195_MUTEX_MOD_DISP1_DISP_MIXER }, - { { DDP_COMPONENT_MERGE5 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 }, - { { DDP_COMPONENT_DP_INTF1 }, MT8195_MUTEX_MOD_DISP1_DP_INTF0 }, + { { MTK_DISP_OVL, 0 }, MT8195_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_WDMA, 0 }, MT8195_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_RDMA, 0 }, MT8195_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_COLOR, 0 }, MT8195_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_CCORR, 0 }, MT8195_MUTEX_MOD_DISP_CCORR0 }, + { { MTK_DISP_AAL, 0 }, MT8195_MUTEX_MOD_DISP_AAL0 }, + { { MTK_DISP_GAMMA, 0 }, MT8195_MUTEX_MOD_DISP_GAMMA0 }, + { { MTK_DISP_DITHER, 0 }, MT8195_MUTEX_MOD_DISP_DITHER0 }, + { { MTK_DISP_MERGE, 0 }, MT8195_MUTEX_MOD_DISP_VPP_MERGE }, + { { MTK_DISP_DSC, 0 }, MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 }, + { { MTK_DISP_DSI, 0 }, MT8195_MUTEX_MOD_DISP_DSI0 }, + { { MTK_DISP_PWM, 0 }, MT8195_MUTEX_MOD_DISP_PWM0 }, + { { MTK_DISP_DP_INTF, 0 }, MT8195_MUTEX_MOD_DISP_DP_INTF0 }, + { { MTK_DISP_MDP_RDMA, 0 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 }, + { { MTK_DISP_MDP_RDMA, 1 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 }, + { { MTK_DISP_MDP_RDMA, 2 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 }, + { { MTK_DISP_MDP_RDMA, 3 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 }, + { { MTK_DISP_MDP_RDMA, 4 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 }, + { { MTK_DISP_MDP_RDMA, 5 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 }, + { { MTK_DISP_MDP_RDMA, 6 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 }, + { { MTK_DISP_MDP_RDMA, 7 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 }, + { { MTK_DISP_MERGE, 1 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 }, + { { MTK_DISP_MERGE, 2 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 }, + { { MTK_DISP_MERGE, 3 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 }, + { { MTK_DISP_MERGE, 4 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 }, + { { MTK_DISP_ETHDR_MIXER, 0 }, MT8195_MUTEX_MOD_DISP1_DISP_MIXER }, + { { MTK_DISP_MERGE, 5 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 }, + { { MTK_DISP_DP_INTF, 1 }, MT8195_MUTEX_MOD_DISP1_DP_INTF0 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8195_legacy_mtx_data =3D { @@ -777,19 +777,19 @@ const struct mtk_drm_legacy_mtx_data mt8195_legacy_mt= x_data =3D { }; =20 static const struct mtk_drm_legacy_mtx_pairs mt8365_legacy_mtx_trig_ids[] = =3D { - { { DDP_COMPONENT_AAL0 }, MT8365_MUTEX_MOD_DISP_AAL }, - { { DDP_COMPONENT_CCORR }, MT8365_MUTEX_MOD_DISP_CCORR }, - { { DDP_COMPONENT_COLOR0 }, MT8365_MUTEX_MOD_DISP_COLOR0 }, - { { DDP_COMPONENT_DITHER0 }, MT8365_MUTEX_MOD_DISP_DITHER }, - { { DDP_COMPONENT_DPI0 }, MT8365_MUTEX_MOD_DISP_DPI0 }, - { { DDP_COMPONENT_DSI0 }, MT8365_MUTEX_MOD_DISP_DSI0 }, - { { DDP_COMPONENT_GAMMA }, MT8365_MUTEX_MOD_DISP_GAMMA }, - { { DDP_COMPONENT_OVL0 }, MT8365_MUTEX_MOD_DISP_OVL0 }, - { { DDP_COMPONENT_OVL_2L0 }, MT8365_MUTEX_MOD_DISP_OVL0_2L }, - { { DDP_COMPONENT_PWM0 }, MT8365_MUTEX_MOD_DISP_PWM0 }, - { { DDP_COMPONENT_RDMA0 }, MT8365_MUTEX_MOD_DISP_RDMA0 }, - { { DDP_COMPONENT_RDMA1 }, MT8365_MUTEX_MOD_DISP_RDMA1 }, - { { DDP_COMPONENT_WDMA0 }, MT8365_MUTEX_MOD_DISP_WDMA0 }, + { { MTK_DISP_AAL, 0 }, MT8365_MUTEX_MOD_DISP_AAL }, + { { MTK_DISP_CCORR, 0 }, MT8365_MUTEX_MOD_DISP_CCORR }, + { { MTK_DISP_COLOR, 0 }, MT8365_MUTEX_MOD_DISP_COLOR0 }, + { { MTK_DISP_DITHER, 0 }, MT8365_MUTEX_MOD_DISP_DITHER }, + { { MTK_DISP_DPI, 0 }, MT8365_MUTEX_MOD_DISP_DPI0 }, + { { MTK_DISP_DSI, 0 }, MT8365_MUTEX_MOD_DISP_DSI0 }, + { { MTK_DISP_GAMMA, 0 }, MT8365_MUTEX_MOD_DISP_GAMMA }, + { { MTK_DISP_OVL, 0 }, MT8365_MUTEX_MOD_DISP_OVL0 }, + { { MTK_DISP_OVL_2L, 0 }, MT8365_MUTEX_MOD_DISP_OVL0_2L }, + { { MTK_DISP_PWM, 0 }, MT8365_MUTEX_MOD_DISP_PWM0 }, + { { MTK_DISP_RDMA, 0 }, MT8365_MUTEX_MOD_DISP_RDMA0 }, + { { MTK_DISP_RDMA, 1 }, MT8365_MUTEX_MOD_DISP_RDMA1 }, + { { MTK_DISP_WDMA, 0 }, MT8365_MUTEX_MOD_DISP_WDMA0 }, }; =20 const struct mtk_drm_legacy_mtx_data mt8365_legacy_mtx_data =3D { @@ -831,13 +831,15 @@ int mtk_drm_legacy_inject_mutex_trig_ids(struct mtk_d= rm_comp_list *hlist, const struct mtk_drm_comp_definition *comp =3D &data->pairs[i].comp; =20 hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp->type) - ddp_comp->mtx_trig_id =3D data->pairs[i].mtx_trig_id; + if (ddp_comp->inst_id =3D=3D comp->inst_id) + ddp_comp->mtx_trig_id =3D data->pairs[i].mtx_trig_id; } =20 return 0; } =20 -u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_id ddp_t= ype, +u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_type ddp= _type, + u8 ddp_inst_id, struct device_node *mutex_node) { struct mtk_drm_legacy_mtx_data *data; @@ -853,7 +855,7 @@ u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mt= k_ddp_comp_id ddp_type, for (i =3D 0; i < data->num_pairs; i++) { const struct mtk_drm_comp_definition *comp =3D &data->pairs[i].comp; =20 - if (ddp_type !=3D comp->type) + if (ddp_type !=3D comp->type || ddp_inst_id !=3D comp->inst_id) continue; =20 return data->pairs[i].mtx_trig_id; @@ -871,6 +873,6 @@ void mtk_drm_legacy_ovl_adaptor_probe(struct device *de= v, struct mtk_drm_private PLATFORM_DEVID_AUTO, (void *)priv, sizeof(*priv)); =20 - mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &priv->hlist, DDP_COMPONENT_DR= M_OVL_ADAPTOR); + mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &priv->hlist, MTK_DISP_OVL_ADA= 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linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 24/46] drm/mediatek: mtk_dpi: Pass parameters with new mtk_dpi_sync structure Date: Tue, 14 Jul 2026 13:43:52 +0200 Message-ID: <20260714114414.184512-25-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for moving common code between DPI and DVO into a new mtk_dpi_common library, add a new mtk_dpi_sync structure which contains all of the sync parameters, such as HSYNC and Left/Right Odd and Even VSYNC. This is now passed as parameter of mtk_dpi_set_display_mode() and stack initialized in mtk_dpi_bridge_enable(): future preparation changes will add abstraction for hardware specific configuration which purpose will be to interpret the generic parameters to write those to the hardware specific registers. This brings no functional change. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 76 +++++++++++++++--------------- 1 file changed, 39 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 959c994eef24..f1200d5f926a 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -112,6 +112,14 @@ struct mtk_dpi_sync_param { bool shift_half_line; }; =20 +struct mtk_dpi_sync { + struct mtk_dpi_sync_param hsync; + struct mtk_dpi_sync_param vsync_l_odd; + struct mtk_dpi_sync_param vsync_l_even; + struct mtk_dpi_sync_param vsync_r_odd; + struct mtk_dpi_sync_param vsync_r_even; +}; + struct mtk_dpi_yc_limit { u16 y_top; u16 y_bottom; @@ -600,14 +608,10 @@ static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi= , struct videomode *vm, int } =20 static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, + struct mtk_dpi_sync *sync, struct drm_display_mode *mode) { struct mtk_dpi_polarities dpi_pol; - struct mtk_dpi_sync_param hsync; - struct mtk_dpi_sync_param vsync_lodd =3D { 0 }; - struct mtk_dpi_sync_param vsync_leven =3D { 0 }; - struct mtk_dpi_sync_param vsync_rodd =3D { 0 }; - struct mtk_dpi_sync_param vsync_reven =3D { 0 }; struct videomode vm =3D { 0 }; =20 drm_display_mode_to_videomode(mode, &vm); @@ -624,42 +628,39 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, =20 /* * Depending on the IP version, we may output a different amount of - * pixels for each iteration: divide the clock by this number and - * adjust the display porches accordingly. + * pixels for each iteration: adjust the display porches accordingly. */ - hsync.sync_width =3D vm.hsync_len / dpi->conf->pixels_per_iter; - hsync.back_porch =3D vm.hback_porch / dpi->conf->pixels_per_iter; - hsync.front_porch =3D vm.hfront_porch / dpi->conf->pixels_per_iter; - - hsync.shift_half_line =3D false; - vsync_lodd.sync_width =3D vm.vsync_len; - vsync_lodd.back_porch =3D vm.vback_porch; - vsync_lodd.front_porch =3D vm.vfront_porch; - vsync_lodd.shift_half_line =3D false; - - if (vm.flags & DISPLAY_FLAGS_INTERLACED && - mode->flags & DRM_MODE_FLAG_3D_MASK) { - vsync_leven =3D vsync_lodd; - vsync_rodd =3D vsync_lodd; - vsync_reven =3D vsync_lodd; - vsync_leven.shift_half_line =3D true; - vsync_reven.shift_half_line =3D true; - } else if (vm.flags & DISPLAY_FLAGS_INTERLACED && - !(mode->flags & DRM_MODE_FLAG_3D_MASK)) { - vsync_leven =3D vsync_lodd; - vsync_leven.shift_half_line =3D true; - } else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) && - mode->flags & DRM_MODE_FLAG_3D_MASK) { - vsync_rodd =3D vsync_lodd; + sync->hsync.sync_width =3D vm.hsync_len / dpi->conf->pixels_per_iter; + sync->hsync.back_porch =3D vm.hback_porch / dpi->conf->pixels_per_iter; + sync->hsync.front_porch =3D vm.hfront_porch / dpi->conf->pixels_per_iter; + sync->hsync.shift_half_line =3D false; + + sync->vsync_l_odd.sync_width =3D vm.vsync_len; + sync->vsync_l_odd.back_porch =3D vm.vback_porch; + sync->vsync_l_odd.front_porch =3D vm.vfront_porch; + sync->vsync_l_odd.shift_half_line =3D false; + + if (vm.flags & DISPLAY_FLAGS_INTERLACED) { + sync->vsync_l_even =3D sync->vsync_l_odd; + sync->vsync_l_even.shift_half_line =3D true; + + if (mode->flags & DRM_MODE_FLAG_3D_MASK) { + sync->vsync_r_odd =3D sync->vsync_l_odd; + sync->vsync_r_even =3D sync->vsync_l_odd; + sync->vsync_r_even.shift_half_line =3D true; + } + } else if (mode->flags & DRM_MODE_FLAG_3D_MASK) { + sync->vsync_r_odd =3D sync->vsync_l_odd; } + mtk_dpi_sw_reset(dpi, true); mtk_dpi_config_pol(dpi, &dpi_pol); =20 - mtk_dpi_config_hsync(dpi, &hsync); - mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd); - mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd); - mtk_dpi_config_vsync_leven(dpi, &vsync_leven); - mtk_dpi_config_vsync_reven(dpi, &vsync_reven); + mtk_dpi_config_hsync(dpi, &sync->hsync); + mtk_dpi_config_vsync_lodd(dpi, &sync->vsync_l_odd); + mtk_dpi_config_vsync_rodd(dpi, &sync->vsync_r_odd); + mtk_dpi_config_vsync_leven(dpi, &sync->vsync_l_even); + mtk_dpi_config_vsync_reven(dpi, &sync->vsync_r_even); =20 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); mtk_dpi_config_interface(dpi, !!(vm.flags & @@ -863,12 +864,13 @@ static void mtk_dpi_bridge_disable(struct drm_bridge = *bridge) static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); + struct mtk_dpi_sync sync =3D { 0 }; =20 if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); =20 mtk_dpi_power_on(dpi); - mtk_dpi_set_display_mode(dpi, &dpi->mode); + mtk_dpi_set_display_mode(dpi, &sync, &dpi->mode); mtk_dpi_enable(dpi); } =20 --=20 2.54.0 From nobody Sat Jul 25 19:29:21 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1B7A380FE7; Tue, 14 Jul 2026 11:45:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Tue, 14 Jul 2026 13:45:00 +0200 (CEST) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, justin.yeh@mediatek.com, jason-jh.lin@mediatek.com, kernel@collabora.com Subject: [PATCH v2 25/46] drm/mediatek: mtk_dpi: Fully separate HW setup from common code Date: Tue, 14 Jul 2026 13:43:53 +0200 Message-ID: <20260714114414.184512-26-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> References: <20260714114414.184512-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" As a preparation step for adding support for DVO and creating a mtk_dpi_common library, fully separate all of the register writing mechanisms from commonizable hardware setup functions. While at it, also perform some spare code style cleanups and also remove the mtk_dpi_config_vsync_{l,r}{odd,even}() functions and open-code the single line found in each of those, as now all of the parameters are clearly labeled and won't have any meaningful impact on human readability. This change brings no functional differences. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_dpi.c | 172 ++++++++++++++--------------- 1 file changed, 86 insertions(+), 86 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index f1200d5f926a..c39e0b064b6f 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -246,33 +246,6 @@ static void mtk_dpi_config_vsync(struct mtk_dpi *dpi, dpi->conf->dimension_mask << VSYNC_FRONT_PORCH_SHIFT); } =20 -static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi, - struct mtk_dpi_sync_param *sync) -{ - mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); -} - -static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi, - struct mtk_dpi_sync_param *sync) -{ - mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN, - DPI_TGEN_VPORCH_LEVEN); -} - -static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi, - struct mtk_dpi_sync_param *sync) -{ - mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD, - DPI_TGEN_VPORCH_RODD); -} - -static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi, - struct mtk_dpi_sync_param *sync) -{ - mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN, - DPI_TGEN_VPORCH_REVEN); -} - static void mtk_dpi_config_pol(struct mtk_dpi *dpi, struct mtk_dpi_polarities *dpi_pol) { @@ -311,30 +284,15 @@ static void mtk_dpi_config_fb_size(struct mtk_dpi *dp= i, u32 width, u32 height) dpi->conf->hvsize_mask << VSIZE); } =20 -static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi) +static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi, struct mtk_d= pi_yc_limit *limit) { - struct mtk_dpi_yc_limit limit; - - if (drm_default_rgb_quant_range(&dpi->mode) =3D=3D - HDMI_QUANTIZATION_RANGE_LIMITED) { - limit.y_bottom =3D 0x10; - limit.y_top =3D 0xfe0; - limit.c_bottom =3D 0x10; - limit.c_top =3D 0xfe0; - } else { - limit.y_bottom =3D 0; - limit.y_top =3D 0xfff; - limit.c_bottom =3D 0; - limit.c_top =3D 0xfff; - } - - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_bottom << Y_LIMINT_BOT, + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit.y_top << Y_LIMINT_TOP, + mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP, Y_LIMINT_TOP_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_bottom << C_LIMIT_BOT, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT, C_LIMIT_BOT_MASK); - mtk_dpi_mask(dpi, DPI_C_LIMIT, limit.c_top << C_LIMIT_TOP, + mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK); } =20 @@ -516,7 +474,6 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) if (--dpi->refcount !=3D 0) return; =20 - mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); clk_disable_unprepare(dpi->tvd_clk); clk_disable_unprepare(dpi->engine_clk); @@ -607,40 +564,40 @@ static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi= , struct videomode *vm, int pll_rate, vm->pixelclock); } =20 -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, +static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct videomode = *vm, struct mtk_dpi_sync *sync, - struct drm_display_mode *mode) + struct mtk_dpi_polarities *dpi_pol, + struct mtk_dpi_yc_limit *limit) { - struct mtk_dpi_polarities dpi_pol; - struct videomode vm =3D { 0 }; + struct drm_display_mode *mode =3D &dpi->mode; =20 - drm_display_mode_to_videomode(mode, &vm); + drm_display_mode_to_videomode(mode, vm); =20 if (!dpi->conf->clocked_by_hdmi) - mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock); + mtk_dpi_set_pixel_clk(dpi, vm, mode->clock); =20 - dpi_pol.ck_pol =3D MTK_DPI_POLARITY_FALLING; - dpi_pol.de_pol =3D MTK_DPI_POLARITY_RISING; - dpi_pol.hsync_pol =3D vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ? + dpi_pol->ck_pol =3D MTK_DPI_POLARITY_FALLING; + dpi_pol->de_pol =3D MTK_DPI_POLARITY_RISING; + dpi_pol->hsync_pol =3D vm->flags & DISPLAY_FLAGS_HSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - dpi_pol.vsync_pol =3D vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ? + dpi_pol->vsync_pol =3D vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ? MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; =20 /* * Depending on the IP version, we may output a different amount of * pixels for each iteration: adjust the display porches accordingly. */ - sync->hsync.sync_width =3D vm.hsync_len / dpi->conf->pixels_per_iter; - sync->hsync.back_porch =3D vm.hback_porch / dpi->conf->pixels_per_iter; - sync->hsync.front_porch =3D vm.hfront_porch / dpi->conf->pixels_per_iter; + sync->hsync.sync_width =3D vm->hsync_len / dpi->conf->pixels_per_iter; + sync->hsync.back_porch =3D vm->hback_porch / dpi->conf->pixels_per_iter; + sync->hsync.front_porch =3D vm->hfront_porch / dpi->conf->pixels_per_iter; sync->hsync.shift_half_line =3D false; =20 - sync->vsync_l_odd.sync_width =3D vm.vsync_len; - sync->vsync_l_odd.back_porch =3D vm.vback_porch; - sync->vsync_l_odd.front_porch =3D vm.vfront_porch; + sync->vsync_l_odd.sync_width =3D vm->vsync_len; + sync->vsync_l_odd.back_porch =3D vm->vback_porch; + sync->vsync_l_odd.front_porch =3D vm->vfront_porch; sync->vsync_l_odd.shift_half_line =3D false; =20 - if (vm.flags & DISPLAY_FLAGS_INTERLACED) { + if (vm->flags & DISPLAY_FLAGS_INTERLACED) { sync->vsync_l_even =3D sync->vsync_l_odd; sync->vsync_l_even.shift_half_line =3D true; =20 @@ -653,27 +610,55 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, sync->vsync_r_odd =3D sync->vsync_l_odd; } =20 + if (drm_default_rgb_quant_range(&dpi->mode) =3D=3D HDMI_QUANTIZATION_RANG= E_LIMITED) { + limit->y_bottom =3D 0x10; + limit->y_top =3D 0xfe0; + limit->c_bottom =3D 0x10; + limit->c_top =3D 0xfe0; + } else { + limit->y_bottom =3D 0; + limit->y_top =3D 0xfff; + limit->c_bottom =3D 0; + limit->c_top =3D 0xfff; + } + + return 0; +} + +static void mtk_dpi_config_hw(struct mtk_dpi *dpi, + struct videomode *vm, struct mtk_dpi_sync *sync, + struct mtk_dpi_polarities *dpi_pol, + struct mtk_dpi_yc_limit *limit) +{ + struct drm_display_mode *mode =3D &dpi->mode; + u32 vactive =3D vm->vactive; + mtk_dpi_sw_reset(dpi, true); - mtk_dpi_config_pol(dpi, &dpi_pol); + mtk_dpi_config_pol(dpi, dpi_pol); =20 mtk_dpi_config_hsync(dpi, &sync->hsync); - mtk_dpi_config_vsync_lodd(dpi, &sync->vsync_l_odd); - mtk_dpi_config_vsync_rodd(dpi, &sync->vsync_r_odd); - mtk_dpi_config_vsync_leven(dpi, &sync->vsync_l_even); - mtk_dpi_config_vsync_reven(dpi, &sync->vsync_r_even); + + mtk_dpi_config_vsync(dpi, &sync->vsync_l_odd, + DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH); + mtk_dpi_config_vsync(dpi, &sync->vsync_r_odd, + DPI_TGEN_VWIDTH_RODD, DPI_TGEN_VPORCH_RODD); + mtk_dpi_config_vsync(dpi, &sync->vsync_l_even, + DPI_TGEN_VWIDTH_LEVEN, DPI_TGEN_VPORCH_LEVEN); + mtk_dpi_config_vsync(dpi, &sync->vsync_r_even, + DPI_TGEN_VWIDTH_REVEN, DPI_TGEN_VPORCH_REVEN); =20 mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK)); - mtk_dpi_config_interface(dpi, !!(vm.flags & - DISPLAY_FLAGS_INTERLACED)); - if (vm.flags & DISPLAY_FLAGS_INTERLACED) - mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1); - else - mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive); + mtk_dpi_config_interface(dpi, !!(vm->flags & DISPLAY_FLAGS_INTERLACED)); + + if (vm->flags & DISPLAY_FLAGS_INTERLACED) + vactive >>=3D 1; =20 - mtk_dpi_config_channel_limit(dpi); + mtk_dpi_config_fb_size(dpi, vm->hactive, vactive); + mtk_dpi_config_channel_limit(dpi, limit); mtk_dpi_config_bit_num(dpi, dpi->bit_num); mtk_dpi_config_channel_swap(dpi, dpi->channel_swap); mtk_dpi_config_color_format(dpi, dpi->color_format); + if (dpi->conf->support_direct_pin) { mtk_dpi_config_yc_map(dpi, dpi->yc_map); mtk_dpi_config_2n_h_fre(dpi); @@ -686,13 +671,13 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *d= pi, =20 mtk_dpi_config_disable_edge(dpi); } - if (dpi->conf->input_2p_en_bit) { + + if (dpi->conf->input_2p_en_bit) mtk_dpi_mask(dpi, DPI_CON, dpi->conf->input_2p_en_bit, dpi->conf->input_2p_en_bit); - } - mtk_dpi_sw_reset(dpi, false); =20 - return 0; + mtk_dpi_sw_reset(dpi, false); + return; } =20 static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *b= ridge, @@ -855,6 +840,7 @@ static void mtk_dpi_bridge_disable(struct drm_bridge *b= ridge) { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); =20 + mtk_dpi_disable(dpi); mtk_dpi_power_off(dpi); =20 if (dpi->pinctrl && dpi->pins_gpio) @@ -864,13 +850,22 @@ static void mtk_dpi_bridge_disable(struct drm_bridge = *bridge) static void mtk_dpi_bridge_enable(struct drm_bridge *bridge) { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); + struct mtk_dpi_polarities dpi_pol; struct mtk_dpi_sync sync =3D { 0 }; + struct mtk_dpi_yc_limit limit; + struct videomode vm; =20 if (dpi->pinctrl && dpi->pins_dpi) pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi); =20 mtk_dpi_power_on(dpi); - mtk_dpi_set_display_mode(dpi, &sync, &dpi->mode); + + /* Set pixel clock and initialize parameters to send to the HW */ + mtk_dpi_set_display_mode(dpi, &vm, &sync, &dpi_pol, &limit); + + /* Format and send the parameters to the HW */ + mtk_dpi_config_hw(dpi, &vm, &sync, &dpi_pol, &limit); + mtk_dpi_enable(dpi); } =20 @@ -1003,16 +998,21 @@ void mtk_dpi_start(struct device *dev) { struct mtk_dpi *dpi =3D dev_get_drvdata(dev); =20 - if (!dpi->conf->clocked_by_hdmi) - mtk_dpi_power_on(dpi); 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charset="utf-8" As a final preparation step for adding support for the MediaTek Digital Video Out (DVO) hardware found in newer SoCs, create a new mtk_dpi_common library and move common code between the DPI and the upcoming DVO in there. This change brings no functional differences, as the new file is built-in on the mediatek-drm object anyway. Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/Makefile | 1 + drivers/gpu/drm/mediatek/mtk_dpi.c | 656 +--------------------- drivers/gpu/drm/mediatek/mtk_dpi_common.c | 472 ++++++++++++++++ drivers/gpu/drm/mediatek/mtk_dpi_common.h | 276 +++++++++ 4 files changed, 766 insertions(+), 639 deletions(-) create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_common.c create mode 100644 drivers/gpu/drm/mediatek/mtk_dpi_common.h diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/M= akefile index f40ad5565716..34a1d4721b70 100644 --- a/drivers/gpu/drm/mediatek/Makefile +++ b/drivers/gpu/drm/mediatek/Makefile @@ -15,6 +15,7 @@ mediatek-drm-y :=3D mtk_crtc.o \ mtk_drm_drv.o \ mtk_drm_legacy.o \ mtk_dsi.o \ + mtk_dpi_common.o \ mtk_dpi.o \ mtk_ethdr.o \ mtk_mdp_rdma.o \ diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index c39e0b064b6f..6988b31175bf 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -2,17 +2,16 @@ /* * Copyright (c) 2014 MediaTek Inc. * Author: Jie Qiu + * + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno */ =20 #include -#include #include #include -#include #include #include -#include -#include #include #include #include @@ -23,173 +22,15 @@ #include #include #include -#include -#include #include #include =20 #include "mtk_ddp_comp.h" #include "mtk_disp_drv.h" +#include "mtk_dpi_common.h" #include "mtk_dpi_regs.h" #include "mtk_drm_drv.h" =20 -enum mtk_dpi_out_bit_num { - MTK_DPI_OUT_BIT_NUM_8BITS, - MTK_DPI_OUT_BIT_NUM_10BITS, - MTK_DPI_OUT_BIT_NUM_12BITS, - MTK_DPI_OUT_BIT_NUM_16BITS -}; - -enum mtk_dpi_out_yc_map { - MTK_DPI_OUT_YC_MAP_RGB, - MTK_DPI_OUT_YC_MAP_CYCY, - MTK_DPI_OUT_YC_MAP_YCYC, - MTK_DPI_OUT_YC_MAP_CY, - MTK_DPI_OUT_YC_MAP_YC -}; - -enum mtk_dpi_out_channel_swap { - MTK_DPI_OUT_CHANNEL_SWAP_RGB, - MTK_DPI_OUT_CHANNEL_SWAP_GBR, - MTK_DPI_OUT_CHANNEL_SWAP_BRG, - MTK_DPI_OUT_CHANNEL_SWAP_RBG, - MTK_DPI_OUT_CHANNEL_SWAP_GRB, - MTK_DPI_OUT_CHANNEL_SWAP_BGR -}; - -enum mtk_dpi_out_color_format { - MTK_DPI_COLOR_FORMAT_RGB, - MTK_DPI_COLOR_FORMAT_YCBCR_422, - MTK_DPI_COLOR_FORMAT_YCBCR_444 -}; - -struct mtk_dpi { - struct drm_encoder encoder; - struct drm_bridge bridge; - struct drm_bridge *next_bridge; - struct drm_connector *connector; - void __iomem *regs; - struct device *dev; - struct device *mmsys_dev; - struct clk *engine_clk; - struct clk *pixel_clk; - struct clk *tvd_clk; - int irq; - struct drm_display_mode mode; - const struct mtk_dpi_conf *conf; - enum mtk_dpi_out_color_format color_format; - enum mtk_dpi_out_yc_map yc_map; - enum mtk_dpi_out_bit_num bit_num; - enum mtk_dpi_out_channel_swap channel_swap; - struct pinctrl *pinctrl; - struct pinctrl_state *pins_gpio; - struct pinctrl_state *pins_dpi; - u32 output_fmt; - int refcount; -}; - -static inline struct mtk_dpi *bridge_to_dpi(struct drm_bridge *b) -{ - return container_of(b, struct mtk_dpi, bridge); -} - -enum mtk_dpi_polarity { - MTK_DPI_POLARITY_RISING, - MTK_DPI_POLARITY_FALLING, -}; - -struct mtk_dpi_polarities { - enum mtk_dpi_polarity de_pol; - enum mtk_dpi_polarity ck_pol; - enum mtk_dpi_polarity hsync_pol; - enum mtk_dpi_polarity vsync_pol; -}; - -struct mtk_dpi_sync_param { - u32 sync_width; - u32 front_porch; - u32 back_porch; - bool shift_half_line; -}; - -struct mtk_dpi_sync { - struct mtk_dpi_sync_param hsync; - struct mtk_dpi_sync_param vsync_l_odd; - struct mtk_dpi_sync_param vsync_l_even; - struct mtk_dpi_sync_param vsync_r_odd; - struct mtk_dpi_sync_param vsync_r_even; -}; - -struct mtk_dpi_yc_limit { - u16 y_top; - u16 y_bottom; - u16 c_top; - u16 c_bottom; -}; - -struct mtk_dpi_factor { - u32 clock; - u8 factor; -}; - -/** - * struct mtk_dpi_conf - Configuration of mediatek dpi. - * @dpi_factor: SoC-specific pixel clock PLL factor values. - * @num_dpi_factor: Number of pixel clock PLL factor values. - * @reg_h_fre_con: Register address of frequency control. - * @max_clock_khz: Max clock frequency supported for this SoCs in khz unit= s. - * @edge_sel_en: Enable of edge selection. - * @output_fmts: Array of supported output formats. - * @num_output_fmts: Quantity of supported output formats. - * @is_ck_de_pol: Support CK/DE polarity. - * @swap_input_support: Support input swap function. - * @support_direct_pin: IP supports direct connection to dpi panels. - * @dimension_mask: Mask used for HWIDTH, HPORCH, VSYNC_WIDTH and VSYNC_PO= RCH - * (no shift). - * @hvsize_mask: Mask of HSIZE and VSIZE mask (no shift). - * @channel_swap_shift: Shift value of channel swap. - * @yuv422_en_bit: Enable bit of yuv422. - * @csc_enable_bit: Enable bit of CSC. - * @input_2p_en_bit: Enable bit for input two pixel per round feature. - * If present, implies that the feature must be enabled. - * @pixels_per_iter: Quantity of transferred pixels per iteration. - * @edge_cfg_in_mmsys: If the edge configuration for DPI's output needs to= be set in MMSYS. - * @clocked_by_hdmi: HDMI IP outputs clock to dpi_pixel_clk input clock, n= eeded - * for DPI registers access. - * @output_1pixel: Enable outputting one pixel per round; if the input is = two pixel per - * round, the DPI hardware will internally transform it to= 1T1P. - */ -struct mtk_dpi_conf { - const struct mtk_dpi_factor *dpi_factor; - const u8 num_dpi_factor; - u32 reg_h_fre_con; - u32 max_clock_khz; - bool edge_sel_en; - const u32 *output_fmts; - u32 num_output_fmts; - bool is_ck_de_pol; - bool swap_input_support; - bool support_direct_pin; - u32 dimension_mask; - u32 hvsize_mask; - u32 channel_swap_shift; - u32 yuv422_en_bit; - u32 csc_enable_bit; - u32 input_2p_en_bit; - u32 pixels_per_iter; - bool edge_cfg_in_mmsys; - bool clocked_by_hdmi; - bool output_1pixel; -}; - -static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mas= k) -{ - u32 tmp =3D readl(dpi->regs + offset) & ~mask; - - tmp |=3D (val & mask); - writel(tmp, dpi->regs + offset); -} - static void mtk_dpi_test_pattern_en(struct mtk_dpi *dpi, u8 type, bool ena= ble) { u32 val; @@ -466,165 +307,6 @@ static void mtk_dpi_dual_edge(struct mtk_dpi *dpi) } } =20 -static void mtk_dpi_power_off(struct mtk_dpi *dpi) -{ - if (WARN_ON(dpi->refcount =3D=3D 0)) - return; - - if (--dpi->refcount !=3D 0) - return; - - clk_disable_unprepare(dpi->pixel_clk); - clk_disable_unprepare(dpi->tvd_clk); - clk_disable_unprepare(dpi->engine_clk); -} - -static int mtk_dpi_power_on(struct mtk_dpi *dpi) -{ - int ret; - - if (++dpi->refcount !=3D 1) - return 0; - - ret =3D clk_prepare_enable(dpi->engine_clk); - if (ret) { - dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); - goto err_refcount; - } - - ret =3D clk_prepare_enable(dpi->tvd_clk); - if (ret) { - dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); - goto err_engine; - } - - ret =3D clk_prepare_enable(dpi->pixel_clk); - if (ret) { - dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); - goto err_pixel; - } - - return 0; - -err_pixel: - clk_disable_unprepare(dpi->tvd_clk); -err_engine: - clk_disable_unprepare(dpi->engine_clk); -err_refcount: - dpi->refcount--; - return ret; -} - -static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode= _clk) -{ - const struct mtk_dpi_factor *dpi_factor =3D dpi->conf->dpi_factor; - int i; - - for (i =3D 0; i < dpi->conf->num_dpi_factor; i++) { - if (mode_clk <=3D dpi_factor[i].clock) - return dpi_factor[i].factor; - } - - /* If no match try the lowest possible factor */ - return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; -} - -static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *v= m, int mode_clk) -{ - unsigned long pll_rate; - unsigned int factor; - - /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ - factor =3D mtk_dpi_calculate_factor(dpi, mode_clk); - pll_rate =3D vm->pixelclock * factor; - - dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm->pixelclock); - - clk_set_rate(dpi->tvd_clk, pll_rate); - pll_rate =3D clk_get_rate(dpi->tvd_clk); - - /* - * Depending on the IP version, we may output a different amount of - * pixels for each iteration: divide the clock by this number and - * adjust the display porches accordingly. - */ - vm->pixelclock =3D pll_rate / factor; - vm->pixelclock /=3D dpi->conf->pixels_per_iter; - - if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || - (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) - clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); - else - clk_set_rate(dpi->pixel_clk, vm->pixelclock); - - vm->pixelclock =3D clk_get_rate(dpi->pixel_clk); - - dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", - pll_rate, vm->pixelclock); -} - -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct videomode = *vm, - struct mtk_dpi_sync *sync, - struct mtk_dpi_polarities *dpi_pol, - struct mtk_dpi_yc_limit *limit) -{ - struct drm_display_mode *mode =3D &dpi->mode; - - drm_display_mode_to_videomode(mode, vm); - - if (!dpi->conf->clocked_by_hdmi) - mtk_dpi_set_pixel_clk(dpi, vm, mode->clock); - - dpi_pol->ck_pol =3D MTK_DPI_POLARITY_FALLING; - dpi_pol->de_pol =3D MTK_DPI_POLARITY_RISING; - dpi_pol->hsync_pol =3D vm->flags & DISPLAY_FLAGS_HSYNC_HIGH ? - MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - dpi_pol->vsync_pol =3D vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ? - MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; - - /* - * Depending on the IP version, we may output a different amount of - * pixels for each iteration: adjust the display porches accordingly. - */ - sync->hsync.sync_width =3D vm->hsync_len / dpi->conf->pixels_per_iter; - sync->hsync.back_porch =3D vm->hback_porch / dpi->conf->pixels_per_iter; - sync->hsync.front_porch =3D vm->hfront_porch / dpi->conf->pixels_per_iter; - sync->hsync.shift_half_line =3D false; - - sync->vsync_l_odd.sync_width =3D vm->vsync_len; - sync->vsync_l_odd.back_porch =3D vm->vback_porch; - sync->vsync_l_odd.front_porch =3D vm->vfront_porch; - sync->vsync_l_odd.shift_half_line =3D false; - - if (vm->flags & DISPLAY_FLAGS_INTERLACED) { - sync->vsync_l_even =3D sync->vsync_l_odd; - sync->vsync_l_even.shift_half_line =3D true; - - if (mode->flags & DRM_MODE_FLAG_3D_MASK) { - sync->vsync_r_odd =3D sync->vsync_l_odd; - sync->vsync_r_even =3D sync->vsync_l_odd; - sync->vsync_r_even.shift_half_line =3D true; - } - } else if (mode->flags & DRM_MODE_FLAG_3D_MASK) { - sync->vsync_r_odd =3D sync->vsync_l_odd; - } - - if (drm_default_rgb_quant_range(&dpi->mode) =3D=3D HDMI_QUANTIZATION_RANG= E_LIMITED) { - limit->y_bottom =3D 0x10; - limit->y_top =3D 0xfe0; - limit->c_bottom =3D 0x10; - limit->c_top =3D 0xfe0; - } else { - limit->y_bottom =3D 0; - limit->y_top =3D 0xfff; - limit->c_bottom =3D 0; - limit->c_top =3D 0xfff; - } - - return 0; -} - static void mtk_dpi_config_hw(struct mtk_dpi *dpi, struct videomode *vm, struct mtk_dpi_sync *sync, struct mtk_dpi_polarities *dpi_pol, @@ -680,143 +362,6 @@ static void mtk_dpi_config_hw(struct mtk_dpi *dpi, return; } =20 -static u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *b= ridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - unsigned int *num_output_fmts) -{ - struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); - u32 *output_fmts; - - *num_output_fmts =3D 0; - - if (!dpi->conf->output_fmts) { - dev_err(dpi->dev, "output_fmts should not be null\n"); - return NULL; - } - - output_fmts =3D kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts), - GFP_KERNEL); - if (!output_fmts) - return NULL; - - *num_output_fmts =3D dpi->conf->num_output_fmts; - - memcpy(output_fmts, dpi->conf->output_fmts, - sizeof(*output_fmts) * dpi->conf->num_output_fmts); - - return output_fmts; -} - -static u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *br= idge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state, - u32 output_fmt, - unsigned int *num_input_fmts) -{ - u32 *input_fmts; - - *num_input_fmts =3D 0; - - input_fmts =3D kcalloc(1, sizeof(*input_fmts), - GFP_KERNEL); - if (!input_fmts) - return NULL; - - *num_input_fmts =3D 1; - input_fmts[0] =3D MEDIA_BUS_FMT_RGB888_1X24; - - return input_fmts; -} - -static unsigned int mtk_dpi_bus_fmt_bit_num(unsigned int out_bus_format) -{ - switch (out_bus_format) { - default: - case MEDIA_BUS_FMT_RGB888_1X24: - case MEDIA_BUS_FMT_BGR888_1X24: - case MEDIA_BUS_FMT_RGB888_2X12_LE: - case MEDIA_BUS_FMT_RGB888_2X12_BE: - case MEDIA_BUS_FMT_YUYV8_1X16: - case MEDIA_BUS_FMT_YUV8_1X24: - return MTK_DPI_OUT_BIT_NUM_8BITS; - case MEDIA_BUS_FMT_RGB101010_1X30: - case MEDIA_BUS_FMT_YUYV10_1X20: - case MEDIA_BUS_FMT_YUV10_1X30: - return MTK_DPI_OUT_BIT_NUM_10BITS; - case MEDIA_BUS_FMT_YUYV12_1X24: - return MTK_DPI_OUT_BIT_NUM_12BITS; - } -} - -static unsigned int mtk_dpi_bus_fmt_channel_swap(unsigned int out_bus_form= at) -{ - switch (out_bus_format) { - default: - case MEDIA_BUS_FMT_RGB888_1X24: - case MEDIA_BUS_FMT_RGB888_2X12_LE: - case MEDIA_BUS_FMT_RGB888_2X12_BE: - case MEDIA_BUS_FMT_RGB101010_1X30: - case MEDIA_BUS_FMT_YUYV8_1X16: - case MEDIA_BUS_FMT_YUYV10_1X20: - case MEDIA_BUS_FMT_YUYV12_1X24: - return MTK_DPI_OUT_CHANNEL_SWAP_RGB; - case MEDIA_BUS_FMT_BGR888_1X24: - case MEDIA_BUS_FMT_YUV8_1X24: - case MEDIA_BUS_FMT_YUV10_1X30: - return MTK_DPI_OUT_CHANNEL_SWAP_BGR; - } -} - -static unsigned int mtk_dpi_bus_fmt_color_format(unsigned int out_bus_form= at) -{ - switch (out_bus_format) { - default: - case MEDIA_BUS_FMT_RGB888_1X24: - case MEDIA_BUS_FMT_BGR888_1X24: - case MEDIA_BUS_FMT_RGB888_2X12_LE: - case MEDIA_BUS_FMT_RGB888_2X12_BE: - case MEDIA_BUS_FMT_RGB101010_1X30: - return MTK_DPI_COLOR_FORMAT_RGB; - case MEDIA_BUS_FMT_YUYV8_1X16: - case MEDIA_BUS_FMT_YUYV10_1X20: - case MEDIA_BUS_FMT_YUYV12_1X24: - return MTK_DPI_COLOR_FORMAT_YCBCR_422; - case MEDIA_BUS_FMT_YUV8_1X24: - case MEDIA_BUS_FMT_YUV10_1X30: - return MTK_DPI_COLOR_FORMAT_YCBCR_444; - } -} - -static int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, - struct drm_bridge_state *bridge_state, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); - unsigned int out_bus_format; - - out_bus_format =3D bridge_state->output_bus_cfg.format; - - if (out_bus_format =3D=3D MEDIA_BUS_FMT_FIXED) - if (dpi->conf->num_output_fmts) - out_bus_format =3D dpi->conf->output_fmts[0]; - - dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", - bridge_state->input_bus_cfg.format, - bridge_state->output_bus_cfg.format); - - dpi->output_fmt =3D out_bus_format; - dpi->bit_num =3D mtk_dpi_bus_fmt_bit_num(out_bus_format); - dpi->channel_swap =3D mtk_dpi_bus_fmt_channel_swap(out_bus_format); - dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; - dpi->color_format =3D mtk_dpi_bus_fmt_color_format(out_bus_format); - - return 0; -} - static int mtk_dpi_bridge_attach(struct drm_bridge *bridge, struct drm_encoder *encoder, enum drm_bridge_attach_flags flags) @@ -827,15 +372,6 @@ static int mtk_dpi_bridge_attach(struct drm_bridge *br= idge, &dpi->bridge, flags); } =20 -static void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) -{ - struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); - - drm_mode_copy(&dpi->mode, adjusted_mode); -} - static void mtk_dpi_bridge_disable(struct drm_bridge *bridge) { struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); @@ -895,39 +431,7 @@ static int mtk_dpi_debug_tp_show(struct seq_file *m, v= oid *arg) en =3D val & DPI_PAT_EN; val =3D FIELD_GET(DPI_PAT_SEL, val); =20 - seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled"); - - if (en) { - seq_printf(m, "Internal pattern %d: ", val); - switch (val) { - case 0: - seq_puts(m, "256 Vertical Gray\n"); - break; - case 1: - seq_puts(m, "1024 Vertical Gray\n"); - break; - case 2: - seq_puts(m, "256 Horizontal Gray\n"); - break; - case 3: - seq_puts(m, "1024 Horizontal Gray\n"); - break; - case 4: - seq_puts(m, "Vertical Color bars\n"); - break; - case 6: - seq_puts(m, "Frame border\n"); - break; - case 7: - seq_puts(m, "Dot moire\n"); - break; - default: - seq_puts(m, "Invalid selection\n"); - break; - } - } - - return 0; + return mtk_dpi_common_debug_tp_show(m, en, val); } =20 static ssize_t mtk_dpi_debug_tp_write(struct file *file, const char __user= *ubuf, @@ -935,23 +439,15 @@ static ssize_t mtk_dpi_debug_tp_write(struct file *fi= le, const char __user *ubuf { struct seq_file *m =3D file->private_data; u32 en, type; - char buf[6]; + ssize_t ret; =20 - if (!m || !m->private || *offp || len > sizeof(buf) - 1) - return -EINVAL; - - memset(buf, 0, sizeof(buf)); - if (copy_from_user(buf, ubuf, len)) - return -EFAULT; - - if (sscanf(buf, "%u %u", &en, &type) !=3D 2) - return -EINVAL; - - if (en < 0 || en > 1 || type < 0 || type > 7) - return -EINVAL; + /* seq_file and dpi pointers are checked by mtk_dpi_common_debug_tp_write= () */ + ret =3D mtk_dpi_common_debug_tp_write(file, ubuf, len, offp, &en, &type); + if (ret < 0) + return ret; =20 mtk_dpi_test_pattern_en((struct mtk_dpi *)m->private, type, en); - return len; + return ret; } =20 static int mtk_dpi_debug_tp_open(struct inode *inode, struct file *file) @@ -990,10 +486,6 @@ static const struct drm_bridge_funcs mtk_dpi_bridge_fu= ncs =3D { .debugfs_init =3D mtk_dpi_debugfs_init, }; =20 -static const struct drm_encoder_funcs mtk_dpi_encoder_funcs =3D { - .destroy =3D drm_encoder_cleanup, -}; - void mtk_dpi_start(struct device *dev) { struct mtk_dpi *dpi =3D dev_get_drvdata(dev); @@ -1024,56 +516,9 @@ unsigned int mtk_dpi_encoder_index(struct device *dev) return encoder_index; } =20 -static int mtk_dpi_bind(struct device *dev, struct device *master, void *d= ata) -{ - struct mtk_dpi *dpi =3D dev_get_drvdata(dev); - struct drm_device *drm_dev =3D data; - struct mtk_drm_private *priv =3D drm_dev->dev_private; - int ret; - - dpi->mmsys_dev =3D priv->mmsys_dev; - ret =3D drm_encoder_init(drm_dev, &dpi->encoder, &mtk_dpi_encoder_funcs, - DRM_MODE_ENCODER_TMDS, NULL); - if (ret) { - dev_err(dev, "Failed to initialize decoder: %d\n", ret); - return ret; - } - - ret =3D mtk_find_possible_crtcs(drm_dev, dpi->dev); - if (ret < 0) - goto err_cleanup; - dpi->encoder.possible_crtcs =3D ret; - - ret =3D drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, - DRM_BRIDGE_ATTACH_NO_CONNECTOR); - if (ret) - goto err_cleanup; - - dpi->connector =3D drm_bridge_connector_init(drm_dev, &dpi->encoder); - if (IS_ERR(dpi->connector)) { - dev_err(dev, "Unable to create bridge connector\n"); - ret =3D PTR_ERR(dpi->connector); - goto err_cleanup; - } - - return 0; - -err_cleanup: - drm_encoder_cleanup(&dpi->encoder); - return ret; -} - -static void mtk_dpi_unbind(struct device *dev, struct device *master, - void *data) -{ - struct mtk_dpi *dpi =3D dev_get_drvdata(dev); - - drm_encoder_cleanup(&dpi->encoder); -} - static const struct component_ops mtk_dpi_component_ops =3D { - .bind =3D mtk_dpi_bind, - .unbind =3D mtk_dpi_unbind, + .bind =3D mtk_dpi_common_bind, + .unbind =3D mtk_dpi_common_unbind, }; =20 static const u32 mt8173_output_fmts[] =3D { @@ -1253,84 +698,16 @@ static const struct mtk_dpi_conf mt8195_dpintf_conf = =3D { =20 static int mtk_dpi_probe(struct platform_device *pdev) { - struct device *dev =3D &pdev->dev; struct mtk_dpi *dpi; int ret; =20 - dpi =3D devm_drm_bridge_alloc(dev, struct mtk_dpi, bridge, - &mtk_dpi_bridge_funcs); + dpi =3D mtk_dpi_common_probe(pdev, &mtk_dpi_bridge_funcs); if (IS_ERR(dpi)) return PTR_ERR(dpi); =20 - dpi->dev =3D dev; - dpi->conf =3D (struct mtk_dpi_conf *)of_device_get_match_data(dev); - dpi->output_fmt =3D MEDIA_BUS_FMT_RGB888_1X24; - - dpi->pinctrl =3D devm_pinctrl_get(&pdev->dev); - if (IS_ERR(dpi->pinctrl)) { - dpi->pinctrl =3D NULL; - dev_dbg(&pdev->dev, "Cannot find pinctrl!\n"); - } - if (dpi->pinctrl) { - dpi->pins_gpio =3D pinctrl_lookup_state(dpi->pinctrl, "sleep"); - if (IS_ERR(dpi->pins_gpio)) { - dpi->pins_gpio =3D NULL; - dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n"); - } - if (dpi->pins_gpio) - pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); - - dpi->pins_dpi =3D pinctrl_lookup_state(dpi->pinctrl, "default"); - if (IS_ERR(dpi->pins_dpi)) { - dpi->pins_dpi =3D NULL; - dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n"); - } - } - dpi->regs =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(dpi->regs)) - return dev_err_probe(dev, PTR_ERR(dpi->regs), - "Failed to ioremap mem resource\n"); - - dpi->engine_clk =3D devm_clk_get(dev, "engine"); - if (IS_ERR(dpi->engine_clk)) - return dev_err_probe(dev, PTR_ERR(dpi->engine_clk), - "Failed to get engine clock\n"); - - dpi->pixel_clk =3D devm_clk_get(dev, "pixel"); - if (IS_ERR(dpi->pixel_clk)) - return dev_err_probe(dev, PTR_ERR(dpi->pixel_clk), - "Failed to get pixel clock\n"); - - dpi->tvd_clk =3D devm_clk_get(dev, "pll"); - if (IS_ERR(dpi->tvd_clk)) - return dev_err_probe(dev, PTR_ERR(dpi->tvd_clk), - "Failed to get tvdpll clock\n"); - - dpi->irq =3D platform_get_irq(pdev, 0); - if (dpi->irq < 0) - return dpi->irq; - - dpi->next_bridge =3D devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node, = 1, -1); - if (IS_ERR(dpi->next_bridge) && PTR_ERR(dpi->next_bridge) =3D=3D -ENODEV)= { - /* Old devicetree has only one endpoint */ - dpi->next_bridge =3D devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node,= 0, 0); - } - if (IS_ERR(dpi->next_bridge)) - return dev_err_probe(dpi->dev, PTR_ERR(dpi->next_bridge), - "Failed to get bridge\n"); - - platform_set_drvdata(pdev, dpi); - - dpi->bridge.of_node =3D dev->of_node; - dpi->bridge.type =3D DRM_MODE_CONNECTOR_DPI; - - ret =3D devm_drm_bridge_add(dev, &dpi->bridge); - if (ret) - return ret; - - ret =3D component_add(dev, &mtk_dpi_component_ops); + ret =3D component_add(&pdev->dev, &mtk_dpi_component_ops); if (ret) - return dev_err_probe(dev, ret, "Failed to add component.\n"); + return dev_err_probe(&pdev->dev, ret, "Failed to add component.\n"); =20 return 0; } @@ -1361,3 +738,4 @@ struct platform_driver mtk_dpi_driver =3D { .of_match_table =3D mtk_dpi_of_ids, }, }; +MODULE_IMPORT_NS("DRM_MTK_DPI"); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_common.c b/drivers/gpu/drm/me= diatek/mtk_dpi_common.c new file mode 100644 index 000000000000..603c32c28ead --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_dpi_common.c @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "mtk_ddp_comp.h" +#include "mtk_dpi_common.h" +#include "mtk_drm_drv.h" + +void mtk_dpi_power_off(struct mtk_dpi *dpi) +{ + if (WARN_ON(dpi->refcount =3D=3D 0)) + return; + + if (--dpi->refcount !=3D 0) + return; + + clk_disable_unprepare(dpi->pixel_clk); + clk_disable_unprepare(dpi->tvd_clk); + clk_disable_unprepare(dpi->engine_clk); +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_power_off, "DRM_MTK_DPI"); + +int mtk_dpi_power_on(struct mtk_dpi *dpi) +{ + int ret; + + if (++dpi->refcount !=3D 1) + return 0; + + ret =3D clk_prepare_enable(dpi->engine_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret); + goto err_refcount; + } + + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_engine; + } + + ret =3D clk_prepare_enable(dpi->pixel_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); + goto err_pixel; + } + + return 0; + +err_pixel: + clk_disable_unprepare(dpi->tvd_clk); +err_engine: + clk_disable_unprepare(dpi->engine_clk); +err_refcount: + dpi->refcount--; + return ret; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_power_on, "DRM_MTK_DPI"); + +static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode= _clk) +{ + const struct mtk_dpi_factor *dpi_factor =3D dpi->conf->dpi_factor; + int i; + + for (i =3D 0; i < dpi->conf->num_dpi_factor; i++) { + if (mode_clk <=3D dpi_factor[i].clock) + return dpi_factor[i].factor; + } + + /* If no match try the lowest possible factor */ + return dpi_factor[dpi->conf->num_dpi_factor - 1].factor; +} + +static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *v= m, int mode_clk) +{ + unsigned long pll_rate; + unsigned int factor; + + /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */ + factor =3D mtk_dpi_calculate_factor(dpi, mode_clk); + pll_rate =3D vm->pixelclock * factor; + + dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n", + pll_rate, vm->pixelclock); + + clk_set_rate(dpi->tvd_clk, pll_rate); + pll_rate =3D clk_get_rate(dpi->tvd_clk); + + /* + * Depending on the IP version, we may output a different amount of + * pixels for each iteration: divide the clock by this number. + */ + vm->pixelclock =3D pll_rate / factor; + vm->pixelclock /=3D dpi->conf->pixels_per_iter; + + if ((dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_LE) || + (dpi->output_fmt =3D=3D MEDIA_BUS_FMT_RGB888_2X12_BE)) + clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2); + else + clk_set_rate(dpi->pixel_clk, vm->pixelclock); + + vm->pixelclock =3D clk_get_rate(dpi->pixel_clk); + + dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n", + pll_rate, vm->pixelclock); +} + +int mtk_dpi_set_display_mode(struct mtk_dpi *dpi, struct videomode *vm, + struct mtk_dpi_sync *sync, + struct mtk_dpi_polarities *dpi_pol, + struct mtk_dpi_yc_limit *limit) +{ + struct drm_display_mode *mode =3D &dpi->mode; + + drm_display_mode_to_videomode(mode, vm); + + if (!dpi->conf->clocked_by_hdmi) + mtk_dpi_set_pixel_clk(dpi, vm, mode->clock); + + dpi_pol->ck_pol =3D MTK_DPI_POLARITY_FALLING; + dpi_pol->de_pol =3D MTK_DPI_POLARITY_RISING; + dpi_pol->hsync_pol =3D vm->flags & DISPLAY_FLAGS_HSYNC_HIGH ? + MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; + dpi_pol->vsync_pol =3D vm->flags & DISPLAY_FLAGS_VSYNC_HIGH ? + MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING; + + /* + * Depending on the IP version, we may output a different amount of + * pixels for each iteration: adjust the display porches accordingly. + */ + sync->hsync.sync_width =3D vm->hsync_len / dpi->conf->pixels_per_iter; + sync->hsync.back_porch =3D vm->hback_porch / dpi->conf->pixels_per_iter; + sync->hsync.front_porch =3D vm->hfront_porch / dpi->conf->pixels_per_iter; + sync->hsync.shift_half_line =3D false; + + sync->vsync_l_odd.sync_width =3D vm->vsync_len; + sync->vsync_l_odd.back_porch =3D vm->vback_porch; + sync->vsync_l_odd.front_porch =3D vm->vfront_porch; + sync->vsync_l_odd.shift_half_line =3D false; + + if (vm->flags & DISPLAY_FLAGS_INTERLACED) { + sync->vsync_l_even =3D sync->vsync_l_odd; + sync->vsync_l_even.shift_half_line =3D true; + + if (mode->flags & DRM_MODE_FLAG_3D_MASK) { + sync->vsync_r_odd =3D sync->vsync_l_odd; + sync->vsync_r_even =3D sync->vsync_l_odd; + sync->vsync_r_even.shift_half_line =3D true; + } + } else if (mode->flags & DRM_MODE_FLAG_3D_MASK) { + sync->vsync_r_odd =3D sync->vsync_l_odd; + } + + if (drm_default_rgb_quant_range(&dpi->mode) =3D=3D HDMI_QUANTIZATION_RANG= E_LIMITED) { + limit->y_bottom =3D 0x10; + limit->y_top =3D 0xfe0; + limit->c_bottom =3D 0x10; + limit->c_top =3D 0xfe0; + } else { + limit->y_bottom =3D 0; + limit->y_top =3D 0xfff; + limit->c_bottom =3D 0; + limit->c_top =3D 0xfff; + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_set_display_mode, "DRM_MTK_DPI"); + +u32 *mtk_dpi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + u32 output_fmt, + unsigned int *num_input_fmts) +{ + u32 *input_fmts; + + *num_input_fmts =3D 0; + + input_fmts =3D kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); + if (!input_fmts) + return NULL; + + *num_input_fmts =3D 1; + input_fmts[0] =3D MEDIA_BUS_FMT_RGB888_1X24; + + return input_fmts; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_bridge_atomic_get_input_bus_fmts, "DRM_MTK_DP= I"); + +u32 *mtk_dpi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + unsigned int *num_output_fmts) +{ + struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); + u32 *output_fmts; + + *num_output_fmts =3D 0; + + if (!dpi->conf->output_fmts) { + dev_err(dpi->dev, "output_fmts should not be null\n"); + return NULL; + } + + output_fmts =3D kcalloc(dpi->conf->num_output_fmts, sizeof(*output_fmts),= GFP_KERNEL); + if (!output_fmts) + return NULL; + + *num_output_fmts =3D dpi->conf->num_output_fmts; + + memcpy(output_fmts, dpi->conf->output_fmts, + sizeof(*output_fmts) * dpi->conf->num_output_fmts); + + return output_fmts; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_bridge_atomic_get_output_bus_fmts, "DRM_MTK_D= PI"); + +int mtk_dpi_bridge_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + unsigned int out_bus_format =3D bridge_state->output_bus_cfg.format; + struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); + + if (out_bus_format =3D=3D MEDIA_BUS_FMT_FIXED && dpi->conf->num_output_fm= ts) + out_bus_format =3D dpi->conf->output_fmts[0]; + + dev_dbg(dpi->dev, "input format 0x%04x, output format 0x%04x\n", + bridge_state->input_bus_cfg.format, + bridge_state->output_bus_cfg.format); + + dpi->output_fmt =3D out_bus_format; + dpi->bit_num =3D mtk_dpi_bus_fmt_bit_num(out_bus_format); + dpi->channel_swap =3D mtk_dpi_bus_fmt_channel_swap(out_bus_format); + dpi->yc_map =3D MTK_DPI_OUT_YC_MAP_RGB; + dpi->color_format =3D mtk_dpi_bus_fmt_color_format(out_bus_format); + + return 0; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_bridge_atomic_check, "DRM_MTK_DPI"); + +void mtk_dpi_bridge_mode_set(struct drm_bridge *bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct mtk_dpi *dpi =3D bridge_to_dpi(bridge); + + drm_mode_copy(&dpi->mode, adjusted_mode); +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_bridge_mode_set, "DRM_MTK_DPI"); + +static const struct drm_encoder_funcs mtk_dpi_encoder_funcs =3D { + .destroy =3D drm_encoder_cleanup, +}; + +int mtk_dpi_common_bind(struct device *dev, struct device *master, void *d= ata) +{ + struct mtk_dpi *dpi =3D dev_get_drvdata(dev); + struct drm_device *drm_dev =3D data; + struct mtk_drm_private *priv =3D drm_dev->dev_private; + int ret; + + dpi->mmsys_dev =3D priv->mmsys_dev; + ret =3D drm_encoder_init(drm_dev, &dpi->encoder, &mtk_dpi_encoder_funcs, + DRM_MODE_ENCODER_TMDS, NULL); + if (ret) { + dev_err(dev, "Failed to initialize decoder: %d\n", ret); + return ret; + } + + ret =3D mtk_find_possible_crtcs(drm_dev, dpi->dev); + if (ret < 0) + goto err_cleanup; + dpi->encoder.possible_crtcs =3D ret; + + ret =3D drm_bridge_attach(&dpi->encoder, &dpi->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) + goto err_cleanup; + + dpi->connector =3D drm_bridge_connector_init(drm_dev, &dpi->encoder); + if (IS_ERR(dpi->connector)) { + dev_err(dev, "Unable to create bridge connector\n"); + ret =3D PTR_ERR(dpi->connector); + goto err_cleanup; + } + + return 0; + +err_cleanup: + drm_encoder_cleanup(&dpi->encoder); + return ret; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_common_bind, "DRM_MTK_DPI"); + +void mtk_dpi_common_unbind(struct device *dev, struct device *master, void= *data) +{ + struct mtk_dpi *dpi =3D dev_get_drvdata(dev); + + drm_encoder_cleanup(&dpi->encoder); +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_common_unbind, "DRM_MTK_DPI"); + +int mtk_dpi_common_debug_tp_show(struct seq_file *m, bool en, u32 sel) +{ + seq_printf(m, "DPI Test Pattern: %s\n", en ? "Enabled" : "Disabled"); + + if (en) { + seq_printf(m, "Internal pattern %d: ", sel); + + switch (sel) { + case 0: + seq_puts(m, "256 Vertical Gray\n"); + break; + case 1: + seq_puts(m, "1024 Vertical Gray\n"); + break; + case 2: + seq_puts(m, "256 Horizontal Gray\n"); + break; + case 3: + seq_puts(m, "1024 Horizontal Gray\n"); + break; + case 4: + seq_puts(m, "Vertical Color bars\n"); + break; + case 6: + seq_puts(m, "Frame border\n"); + break; + case 7: + seq_puts(m, "Dot moire\n"); + break; + default: + seq_puts(m, "Invalid selection\n"); + break; + } + } + + return 0; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_common_debug_tp_show, "DRM_MTK_DPI"); + +ssize_t mtk_dpi_common_debug_tp_write(struct file *file, const char __user= *ubuf, + size_t len, loff_t *offp, u32 *en, u32 *type) +{ + struct seq_file *m =3D file->private_data; + char buf[6]; + + if (!m || !m->private || *offp || len > sizeof(buf) - 1) + return -EINVAL; + + memset(buf, 0, sizeof(buf)); + if (copy_from_user(buf, ubuf, len)) + return -EFAULT; + + if (sscanf(buf, "%u %u", en, type) !=3D 2) + return -EINVAL; + + if (*en < 0 || *en > 1 || *type < 0 || *type > 7) + return -EINVAL; + + return len; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_common_debug_tp_write, "DRM_MTK_DPI"); + +struct mtk_dpi *mtk_dpi_common_probe(struct platform_device *pdev, + const struct drm_bridge_funcs *bridge_funcs) +{ + struct device *dev =3D &pdev->dev; + struct mtk_dpi *dpi; + int ret; + + dpi =3D devm_drm_bridge_alloc(dev, struct mtk_dpi, bridge, bridge_funcs); + if (IS_ERR(dpi)) + return dpi; + + dpi->dev =3D dev; + dpi->conf =3D (struct mtk_dpi_conf *)of_device_get_match_data(dev); + dpi->output_fmt =3D MEDIA_BUS_FMT_RGB888_1X24; + + dpi->pinctrl =3D devm_pinctrl_get(dev); + if (IS_ERR_OR_NULL(dpi->pinctrl)) { + dev_dbg(dev, "Cannot find pinctrl!\n"); + dpi->pinctrl =3D NULL; + } else { + dpi->pins_gpio =3D pinctrl_lookup_state(dpi->pinctrl, "sleep"); + if (IS_ERR(dpi->pins_gpio)) { + dpi->pins_gpio =3D NULL; + dev_dbg(dev, "Cannot find pinctrl idle!\n"); + } + if (dpi->pins_gpio) + pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio); + + dpi->pins_dpi =3D pinctrl_lookup_state(dpi->pinctrl, "default"); + if (IS_ERR(dpi->pins_dpi)) { + dpi->pins_dpi =3D NULL; + dev_dbg(dev, "Cannot find pinctrl active!\n"); + } + } + + dpi->regs =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(dpi->regs)) + return dev_err_ptr_probe(dev, PTR_ERR(dpi->regs), + "Failed to ioremap mem resource\n"); + + dpi->engine_clk =3D devm_clk_get(dev, "engine"); + if (IS_ERR(dpi->engine_clk)) + return dev_err_ptr_probe(dev, PTR_ERR(dpi->engine_clk), + "Failed to get engine clock\n"); + + dpi->pixel_clk =3D devm_clk_get(dev, "pixel"); + if (IS_ERR(dpi->pixel_clk)) + return dev_err_ptr_probe(dev, PTR_ERR(dpi->pixel_clk), + "Failed to get pixel clock\n"); + + dpi->tvd_clk =3D devm_clk_get(dev, "pll"); + if (IS_ERR(dpi->tvd_clk)) + return dev_err_ptr_probe(dev, PTR_ERR(dpi->tvd_clk), + "Failed to get tvdpll clock\n"); + + dpi->irq =3D platform_get_irq(pdev, 0); + if (dpi->irq < 0) + return ERR_PTR(dpi->irq); + + dpi->next_bridge =3D devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node, = 1, -1); + if (IS_ERR(dpi->next_bridge) && PTR_ERR(dpi->next_bridge) =3D=3D -ENODEV)= { + /* Old devicetree has only one endpoint */ + dpi->next_bridge =3D devm_drm_of_get_bridge(dpi->dev, dpi->dev->of_node,= 0, 0); + } + if (IS_ERR(dpi->next_bridge)) + return dev_err_ptr_probe(dpi->dev, PTR_ERR(dpi->next_bridge), + "Failed to get bridge\n"); + + platform_set_drvdata(pdev, dpi); + + dpi->bridge.of_node =3D dev->of_node; + dpi->bridge.type =3D DRM_MODE_CONNECTOR_DPI; + + ret =3D devm_drm_bridge_add(dev, &dpi->bridge); + if (ret) + return ERR_PTR(ret); + + return dpi; +} +EXPORT_SYMBOL_NS_GPL(mtk_dpi_common_probe, "DRM_MTK_DPI"); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("MediaTek DPI/DVO Common Library"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/mediatek/mtk_dpi_common.h b/drivers/gpu/drm/me= diatek/mtk_dpi_common.h new file mode 100644 index 000000000000..c5cc26c7900d --- /dev/null +++ b/drivers/gpu/drm/mediatek/mtk_dpi_common.h @@ -0,0 +1,276 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Copyright (c) 2026 Collabora Ltd. + * AngeloGioacchino Del Regno + */ + +#ifndef _MTK_DPI_COMMON_H +#define _MTK_DPI_COMMON_H + +#include +#include +#include +#include +#include +#include +#include +#include