From nobody Sat Jul 25 20:10:44 2026 Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9CCC63F0AAC; Tue, 14 Jul 2026 07:45:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784015145; cv=none; b=X/q0Y5HS4pIf9TXtKrhwSCXJ+vfycMbJqVTMgSS9aJto+ydkggARnuX3p+4tKOtI/b3WaeQaBl693zBVHmrbM4W6Hny6QpFO7Yn6XnDiyoCL4zoRHUPuix2WVhZWjPaQnb/Umhq+tYHWEnLovIsrhwS7ZI2EOMbsYq7mwjROUaY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784015145; c=relaxed/simple; bh=n+OvI+kFDxP/yL79NSNfJcdIwV+5LLdHPtUMM8FW3EI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YMn8RM3SYQoYHTHHAKaFW6YrkB9jhNT+VT+u6wbZgf5nH2WfKWwqK0le8r5DNFDP/jopmQaHnWZeKqzPLLccPl8wtlHkYO7gdmgrAYxtfvYh2h4B6WzTAjWRTdkms1n+acD3k/2QGSp79rKrHhHafVEwn//pMYn47NEfQC/Fpxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.101.100]) by APP-05 (Coremail) with SMTP id zQCowABXq84X6VVqEs8pGA--.61698S3; Tue, 14 Jul 2026 15:45:30 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MoeLeak Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng , Icenowy Zheng Subject: [PATCH v2 1/5] riscv: dts: thead: th1520: remove pclk for I2C1 Date: Tue, 14 Jul 2026 15:45:11 +0800 Message-ID: <20260714074515.1959352-2-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> References: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABXq84X6VVqEs8pGA--.61698S3 X-Coremail-Antispam: 1UD129KBjvJXoW7ZrW3try5XFWUXF4rJryUGFg_yoW8Wryxpw 43Cr48AFn5WF1F9w13tw10gF4kA3Z5JF4kWr17WFyUZws8W3yjqFZ7KrWfXFWrt34xZw12 kr1Dtw1fCr1YvaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCY1x0262kKe7AKxVWUtVW8ZwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWU JVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67 kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY 6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0x vEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVj vjDU0xZFpf9x0JUfKs8UUUUU= X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" The I2C1 node added previously to the th1520.dtsi file has two clocks set -- one "ref" clock (CLK_I2C1) and one "pclk" (CLK_PERI_APB_PCLK). However, the CLK_I2C1 clock is just a clock gate with the CLK_PERI_APB_PCLK clock as its input. In addition, when it's gated, reading registers from the I2C controller returns fixed value (the last read value) for all registers. These facts indicate that the CLK_I2C1 clock is the true APB clock fed into the I2C controller instead of a dedicated reference clock. Leave only the CLK_I2C1 clock as the `clocks` property of the I2C1 device node and remove `clock-names` property, which represents the I2C controller only takes a single clock both as the APB clock and the reference clock. Fixes: 2f60e3516330 ("riscv: dts: thead: Add TH1520 I2C1 controller") Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index 94932c51b7e39..db23624696b73 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -415,8 +415,7 @@ i2c1: i2c@ffe7f24000 { compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; reg =3D <0xff 0xe7f24000 0x0 0x4000>; interrupts =3D <45 IRQ_TYPE_LEVEL_HIGH>; - clocks =3D <&clk CLK_I2C1>, <&clk CLK_PERI_APB_PCLK>; - clock-names =3D "ref", "pclk"; + clocks =3D <&clk CLK_I2C1>; #address-cells =3D <1>; #size-cells =3D <0>; status =3D "disabled"; --=20 2.52.0 From nobody Sat Jul 25 20:10:44 2026 Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFF613F2109; Tue, 14 Jul 2026 07:45:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784015151; cv=none; b=ja2vR+v2BsL4ZBqsufj8N+m0/ibQM28dhx1M5I3S934BxlL3JWszWpXiATnkW9PX5U/guBvWRGOW29eVtdaOb7iQRwCvwXyMcqPI3NOif0b7Da8QoukVi+GBq11IzIh554eUcTa81bE9fSTsSl/7EcpRU7FuPyas9JDOW3K/8XU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784015151; c=relaxed/simple; bh=q1mXfQ1sifixwNtqgWrpB3QytlKCueqwEROo60781MM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hjeZIKIM9117rVIYEZToQGuzN/8S36LDed7Ta7nUukYy2CRnxbGOxJSN+FD1sQrwuKGykBaUACEsNJkeQ3agmhjZIF7BB8ZO9zyKfIeI3px9RZ6WWLjtzyE5n4mPCQn2OkDdUA9hxg8q+tTx4ih/oVT5FuiKGYDrTv6Ulb3zFT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.101.100]) by APP-05 (Coremail) with SMTP id zQCowABXq84X6VVqEs8pGA--.61698S4; Tue, 14 Jul 2026 15:45:31 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MoeLeak Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng , Thomas Bonnefille , Drew Fustini , Icenowy Zheng Subject: [PATCH v2 2/5] riscv: dts: thead: Add TH1520 I2C nodes Date: Tue, 14 Jul 2026 15:45:12 +0800 Message-ID: <20260714074515.1959352-3-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> References: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABXq84X6VVqEs8pGA--.61698S4 X-Coremail-Antispam: 1UD129KBjvJXoWxXw13AF1DJF4fJw15AFWxCrg_yoW5Cr17pa srArZ5Aws5XF4a93W3XF12kFZ8Jan5uF92grnFkFWUKw1YgF4YvrW8tFyIvF18XFWUXw13 tFn3Cr10yrn8tw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmF14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAI cVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIx AIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2 KfnxnUUI43ZEXa7sRREfO5UUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Thomas Bonnefille Add nodes for the remaining five I2C controllers on the T-Head TH1520 RISCV SoC. Signed-off-by: Thomas Bonnefille Reviewed-by: Drew Fustini [Icenowy: rebase and reword commit message to exclude I2C1] Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 50 +++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/th= ead/th1520.dtsi index db23624696b73..b01a94785d870 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -411,6 +411,16 @@ uart3: serial@ffe7f04000 { status =3D "disabled"; }; =20 + i2c0: i2c@ffe7f20000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xe7f20000 0x0 0x4000>; + interrupts =3D <44 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + i2c1: i2c@ffe7f24000 { compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; reg =3D <0xff 0xe7f24000 0x0 0x4000>; @@ -421,6 +431,16 @@ i2c1: i2c@ffe7f24000 { status =3D "disabled"; }; =20 + i2c4: i2c@ffe7f28000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xe7f28000 0x0 0x4000>; + interrupts =3D <48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C4>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + gpio@ffe7f34000 { compatible =3D "snps,dw-apb-gpio"; reg =3D <0xff 0xe7f34000 0x0 0x1000>; @@ -519,6 +539,16 @@ padctrl0_apsys: pinctrl@ffec007000 { thead,pad-group =3D <3>; }; =20 + i2c2: i2c@ffec00c000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xec00c000 0x0 0x4000>; + interrupts =3D <46 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C2>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + uart2: serial@ffec010000 { compatible =3D "snps,dw-apb-uart"; reg =3D <0xff 0xec010000 0x0 0x4000>; @@ -530,6 +560,16 @@ uart2: serial@ffec010000 { status =3D "disabled"; }; =20 + i2c3: i2c@ffec014000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xec014000 0x0 0x4000>; + interrupts =3D <47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C3>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + pwm: pwm@ffec01c000 { compatible =3D "thead,th1520-pwm"; reg =3D <0xff 0xec01c000 0x0 0x4000>; @@ -735,6 +775,16 @@ uart5: serial@fff7f0c000 { status =3D "disabled"; }; =20 + i2c5: i2c@fff7f2c000 { + compatible =3D "thead,th1520-i2c", "snps,designware-i2c"; + reg =3D <0xff 0xf7f2c000 0x0 0x4000>; + interrupts =3D <49 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&clk CLK_I2C5>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "disabled"; + }; + timer4: timer@ffffc33000 { compatible =3D "snps,dw-apb-timer"; reg =3D <0xff 0xffc33000 0x0 0x14>; --=20 2.52.0 From nobody Sat Jul 25 20:10:44 2026 Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6AB963F2100; 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dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.101.100]) by APP-05 (Coremail) with SMTP id zQCowABXq84X6VVqEs8pGA--.61698S5; Tue, 14 Jul 2026 15:45:33 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MoeLeak Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng , Icenowy Zheng Subject: [PATCH v2 3/5] riscv: dts: thead: lpi4a: sort nodes Date: Tue, 14 Jul 2026 15:45:13 +0800 Message-ID: <20260714074515.1959352-4-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> References: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABXq84X6VVqEs8pGA--.61698S5 X-Coremail-Antispam: 1UD129KBjvJXoW7ur1rKrykGryDuryxWr18uFg_yoW8tr1Upa 1fXFZ3K3WkCr40grnIqry0qF1rGan5GF93KwnxC348Xr47WrW8JryrKwn5ZFyDWFWrXw13 CFs3JFy2vF1qyw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmF14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAI cVC0I7IYx2IY6xkF7I0E14v26F4j6r4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIx AIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2 KfnxnUUI43ZEXa7VU1sYFtUUUUU== X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" Although "D", "H" and "I" are earlier in the alphabet than "P", the DPU, HDMI and I2C1 nodes were added after PADCTRL nodes in the Lichee Pi 4A device tree; in addition the PADCTRL1 node is placed before the PADCTRL0 one. Sort the nodes in this device tree. Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini =20 --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 72 +++++++++---------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index af6f25ebbf607..74b120c6b063a 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -103,17 +103,31 @@ fan: pwm-fan { =20 }; =20 -&padctrl1_apsys { - i2c1_pins: i2c1-0 { - i2c-pins { - pins =3D "I2C1_SCL", "I2C1_SDA"; - function =3D "i2c"; - bias-pull-up =3D <2100>; - drive-strength =3D <7>; - input-enable; - input-schmitt-enable; - slew-rate =3D <0>; - }; +&dpu { + status =3D "okay"; +}; + +&hdmi { + status =3D "okay"; +}; + +&hdmi_out_port { + hdmi_out_con: endpoint { + remote-endpoint =3D <&hdmi_con_in>; + }; +}; + +&i2c1 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + status =3D "okay"; + + ioexp2: gpio@18 { + compatible =3D "nxp,pca9557"; + reg =3D <0x18>; + gpio-controller; + #gpio-cells =3D <2>; }; }; =20 @@ -153,17 +167,17 @@ rx-pins { }; }; =20 -&i2c1 { - clock-frequency =3D <400000>; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&i2c1_pins>; - status =3D "okay"; - - ioexp2: gpio@18 { - compatible =3D "nxp,pca9557"; - reg =3D <0x18>; - gpio-controller; - #gpio-cells =3D <2>; +&padctrl1_apsys { + i2c1_pins: i2c1-0 { + i2c-pins { + pins =3D "I2C1_SCL", "I2C1_SDA"; + function =3D "i2c"; + bias-pull-up =3D <2100>; + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; }; }; =20 @@ -179,20 +193,6 @@ &sdio1 { status =3D "okay"; }; =20 -&dpu { - status =3D "okay"; -}; - -&hdmi { - status =3D "okay"; -}; - -&hdmi_out_port { - hdmi_out_con: endpoint { - remote-endpoint =3D <&hdmi_con_in>; - }; -}; - &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_pins>; --=20 2.52.0 From nobody Sat Jul 25 20:10:44 2026 Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0DEFA3F20F4; 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charset="utf-8" From: Emil Renner Berthing Add labels for GPIOs on the IO expansion chip on the I2C1 bus. Signed-off-by: Emil Renner Berthing [Icenowy: Splitted off the patch adding all 3 IO expansions] Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini =20 --- arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 74b120c6b063a..78f5979a56c14 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -128,6 +128,14 @@ ioexp2: gpio@18 { reg =3D <0x18>; gpio-controller; #gpio-cells =3D <2>; + gpio-line-names =3D "", + "cam0_reset", + "cam1_reset", + "cam2_reset", + "wl_host_wake", + "bt_resetn", + "", + "bt_host_wake"; }; }; =20 --=20 2.52.0 From nobody Sat Jul 25 20:10:44 2026 Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C8CA3F4853; Tue, 14 Jul 2026 07:45:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784015150; cv=none; b=qBkJOaNPy34vduXjL5d2Z+NUt4vM5jef32VSFhyNggD4usYou8IHshxb1o5fCsMZnB4exrA5KAtpHzKoYIlamBJQmiSduuZUNMIUaS0oQ7904ZyAs7Mq6PC64rkqBRfqOPfg7Ae942g9e16x7/dWrx6ROJLZPC/kKiCXFFGhyew= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784015150; c=relaxed/simple; bh=Zh+tqLcF6GYgpG9FDLpPCwTm5HMFuErsnFlL03ULyzU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ctx6zzPm1V1Hs9ntuirtS63hZO5bJR5CTQmrJ0KH9LN6NwkN7XGBl/AIsjTEo/X84wHwQvnZQZ9Hg4QxDSM25PqQZOP4n7ml6AJ8EKX4jherT3FjmqiErnkPMLEV4tJdIdpCVSXcJ5bMJqCWR50heSkkKuQ9ZzaoWjdOSfADHFc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.25 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from edelgard.fodlan.icenowy.me (unknown [112.94.101.100]) by APP-05 (Coremail) with SMTP id zQCowABXq84X6VVqEs8pGA--.61698S7; Tue, 14 Jul 2026 15:45:35 +0800 (CST) From: Icenowy Zheng To: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MoeLeak Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Icenowy Zheng , Emil Renner Berthing , Icenowy Zheng Subject: [PATCH v2 5/5] riscv: dts: thead: Add remaining Lichee Pi 4A IO expansions Date: Tue, 14 Jul 2026 15:45:15 +0800 Message-ID: <20260714074515.1959352-6-zhengxingda@iscas.ac.cn> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> References: <20260714074515.1959352-1-zhengxingda@iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: zQCowABXq84X6VVqEs8pGA--.61698S7 X-Coremail-Antispam: 1UD129KBjvJXoW7AF48ZFWrKrW8XFyktr43Wrg_yoW5Jr4xpa 1xZ3yft3Wvkry2934avFy09FyrGan5JF95KrnrCFy8Xw43WFW8X34jqrn8uF1DXF4ruw13 CFsxCr929F1qv3JanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE 3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2I x0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Y z7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zV AF1VAY17CE14v26r4a6rW5MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1l IxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r 1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIY CTnIWIevJa73UjIFyTuYvjfUriihUUUUU X-CM-SenderInfo: x2kh0wp0lqwv3d6l2u1dvotugofq/ Content-Type: text/plain; charset="utf-8" From: Emil Renner Berthing Lichee Pi 4A has 3 I2C IO expansion chips onboard, connected to the I2C0/1/3 busses. The I2C1 one is already added to the device tree, but the I2C0/3 ones are not yet added. Add device tree nodes for them. Signed-off-by: Emil Renner Berthing [Icenowy: added commit description, enable SoC pull-up, remove I2C1 and aliases] Signed-off-by: Icenowy Zheng Reviewed-by: Drew Fustini =20 --- .../boot/dts/thead/th1520-lichee-pi-4a.dts | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv= /boot/dts/thead/th1520-lichee-pi-4a.dts index 78f5979a56c14..75396cafb39dc 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts @@ -117,6 +117,23 @@ hdmi_out_con: endpoint { }; }; =20 +&i2c0 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + status =3D "okay"; + + ioexp1: gpio@18 { + compatible =3D "nxp,pca9557"; + reg =3D <0x18>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "cam0_dvdd12", + "cam0_avdd28", + "cam0_dovdd18"; + }; +}; + &i2c1 { clock-frequency =3D <400000>; pinctrl-names =3D "default"; @@ -139,6 +156,28 @@ ioexp2: gpio@18 { }; }; =20 +&i2c3 { + clock-frequency =3D <400000>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + status =3D "okay"; + + ioexp3: gpio@18 { + compatible =3D "nxp,pca9557"; + reg =3D <0x18>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D "tp0_rst", + "", + "", + "vcc5v_usb", + "vdd28_tp0", + "vdd33_lcd0", + "vdd18_lcd0", + "lcd0_reset"; + }; +}; + &padctrl0_apsys { fan_pins: fan-0 { pwm1-pins { @@ -152,6 +191,18 @@ pwm1-pins { }; }; =20 + i2c3_pins: i2c3-0 { + i2c-pins { + pins =3D "I2C3_SCL", "I2C3_SDA"; + function =3D "i2c"; + bias-pull-up =3D <2100>; + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + uart0_pins: uart0-0 { tx-pins { pins =3D "UART0_TXD"; @@ -176,6 +227,18 @@ rx-pins { }; =20 &padctrl1_apsys { + i2c0_pins: i2c0-0 { + i2c-pins { + pins =3D "I2C0_SCL", "I2C0_SDA"; + function =3D "i2c"; + bias-pull-up =3D <2100>; + drive-strength =3D <7>; + input-enable; + input-schmitt-enable; + slew-rate =3D <0>; + }; + }; + i2c1_pins: i2c1-0 { i2c-pins { pins =3D "I2C1_SCL", "I2C1_SDA"; --=20 2.52.0