From nobody Sat Jul 25 20:06:04 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABD5E2EBB8C for ; Tue, 14 Jul 2026 05:47:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.178 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784008029; cv=none; b=bXml8NygPoX4NcpcHi01LY8OW1hRicVOCyiF5NE6Sf/D1uxHV9jlGYFNC+rdHQ7qiqfxWRIJYEsKIF/gy48VqBxIMHJqXFxB+kGHWY/oqhBAEWcS/shrhyqAhIScdb9yE2rKM92Wxo9OTW3qSqJOg7Hx+HqAINQnWxFTnD1brxg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784008029; c=relaxed/simple; bh=PjeAyVzdrmEPvru5WSS2hywp+olcq5EiYjAbVoPzIDc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KIsIQa+ZbN9FLEI8RIzIh5sDbM3WS8kiqHwbU0f+9JGIb/RFt/tveWe9bPacdW6ek+nQCNXLFLfiI+5OY4tYpOqcL8/yAxvuK72pCOMjAJtmNurkBIA6kYZRqvJG2Q0ZYQmcmklxYgdQTpA958xx2i1fDLjaYRbWZTwi9cFu8oI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=AgH1VwVl; arc=none smtp.client-ip=209.85.214.178 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="AgH1VwVl" Received: by mail-pl1-f178.google.com with SMTP id d9443c01a7336-2cea3004256so35367205ad.0 for ; Mon, 13 Jul 2026 22:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784008028; x=1784612828; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=YtSd3Xc+ifVj14PL2Jkw0taP79/hnT+MmHpMwaXVGFE=; b=AgH1VwVluJ4+TyWH6EXqMBYV0DUCO/jMAQJqtZoehFeKjW/ZhVL3GdVt/Bxt7+eIGn g/lhWTrYFERZA07N4c52VYCsiySpaWC2/ohCu/cDIgnHN4DI5zPQUil1bI/mYLKSdkWw pC0tBp3Gh6d5Yk1WnpIDHU4tWcyOvhCE5vivZU5gbULPA4fJp20tnnC5Kg574I9hBJaX rSNRaJBUbBpogRWZDFzDeltZjsD1MmitnZWbQSZM2t+MVU8a36uj4MXq/RRtPWW/WlMU eQ2dMCYt6ocFBT9AsSpCJgvWTGd+BJXYDAyrcS997KBe4A1qzOkhIB7eN1mqeJqfRRVe QupQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784008028; x=1784612828; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=YtSd3Xc+ifVj14PL2Jkw0taP79/hnT+MmHpMwaXVGFE=; b=MDngYvu+9DYsiBAFajzOTLUEZ6fncixX9jDrj9tdKUmwiuRgS92BDG1KFNafq9fh4w FZFwtWxe8g83Tj9Jvsk9fSHKv1aJHueMz6/RwJ/yltiBoI6vxPa3yOtVjURM7Pxfv9GX i9MhJ+uF0MJm0DpdYHwk8fZnO5pfmzrdpiwQFXkLiFB6mTaovs1N924e/KH1jTQ71i9P MjjTlNloaR4kpOoA0eG4i4qdwFuG2qsRm2JTHCkqc6ym2APqbU33nhgMEuvKack1zVjg DT66c5IG9/vyvhYKgKWNBYxb79SRk3wHz3RoKvrap/8pSrzOtDt1ntp1ACDf5JXTZNdA Fbhw== X-Forwarded-Encrypted: i=1; AHgh+RoAqKqPP6d98QdFMOEQzUPM5W1PfEPoeAYzntn2Z7Ft5cFxbRqSqAbKIBtEv7S7Bv7rNpq46KYmvgW8F9I=@vger.kernel.org X-Gm-Message-State: AOJu0YyEo97Q/7cGqDjbFI+EY2FH1Cxo7BzQgRQgPYHT/u4VBEBcmxtE PAo3yAC4DIg38212cu0i++CJWPiyvgkp/ouJhb5CVkyOIVhLrDcPjKXL X-Gm-Gg: AfdE7cl+bp14LhNv00siHZcw+r3gs/WNwTdr2EaIvf7qW1EQqP+UU4QDHGWipCrNuZ7 7lw3HK9CpHXjLPjdwrTsygjDGjd8pAsvXqyVIFkIkCN1FTtX5+at42cYUXyOh2JTr9vKfhTrxJO jFP3aPSUwRaOamJJeWhcOculwavIe/jQzhEJTv4AYiAQmVBd4NOmFDeVyUp9tYPAN4z6pxmRUz5 cZ9LyOGV8Rb55SEoScir5eDbu7x6cPYbywwCLNj0R02tSeqUgCL1th79WoiSiyl/V1IRfT+qGq4 qkX/6AIrLOuNhSHEdiAZUyK8v2jMDzpDW3Mwx0u+dMPzgqu0WwsfYb7keRA2bsrZcpPuJKBw/nM BTelUjGAZAXsUYhbC+neapZ0piHbWSW9QInTcBKo+66RLKcxkH01rk4yj66RyKC8D8Vitd3ZtqN cNwCcmBZoceKIx0d2EmeA= X-Received: by 2002:a05:6a21:689:b0:3bf:e2f1:1b17 with SMTP id adf61e73a8af0-3c35723202fmr1160592637.50.1784008027983; Mon, 13 Jul 2026 22:47:07 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:9c6f:e28:3da8:7980]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3117483dec6sm77965054eec.11.2026.07.13.22.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 22:47:07 -0700 (PDT) From: Hrushiraj Gandhi To: linux-rockchip@lists.infradead.org Cc: heiko@sntech.de, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v4 1/2] dt-bindings: arm: rockchip: Add Vicharak Vaaman2 Date: Tue, 14 Jul 2026 11:16:52 +0530 Message-ID: <20260714054653.266842-2-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260714054653.266842-1-hrushirajg23@gmail.com> References: <20260714054653.266842-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree binding documentation for the Vicharak Vaaman2, a single-board computer based on the Rockchip RK3588 SoC. Signed-off-by: Hrushiraj Gandhi Acked-by: Conor Dooley --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index b023d4cc9842..b5a43fd5e546 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -1311,6 +1311,11 @@ properties: - const: vicharak,axon - const: rockchip,rk3588 =20 + - description: Vicharak Vaaman2 + items: + - const: vicharak,vaaman2 + - const: rockchip,rk3588 + - description: WolfVision PF5 mainboard items: - const: wolfvision,rk3568-pf5 --=20 2.47.3 From nobody Sat Jul 25 20:06:04 2026 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF33932B13A for ; Tue, 14 Jul 2026 05:47:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784008035; cv=none; b=QU8f+CU5JN7/OH146UgEub2/fbBOoikaq/AdpP2MpQynbVJk1noLE2dQ3F4dqX2zCnFP/mdc1hWuvFZ7wuDjMFk7CUiCOCsXb7+NCwhGyH59v1o2cWZSGogAsIKy6VgR8/+AUhTOmtE0rY8XrRMfTMq/g0YrfKszDHGg3NDw8OY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784008035; c=relaxed/simple; bh=YruFWoqCSpLtg6Yv7gJYWNsyYN9UmtI2GgUQOZFb7rk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jU3CaYo2QzUi4AyjyfA8aDyKsXfm29iChOID0FhyGgdtcUlsVanlR0Pje+jX2x21ZlHPKTWMqg+byili3xO3Ch6lipP/ern5vWlpHICsFWfjT+MOesQgx6bjc7UrF0UxifhF35Y/u0B8yDeDFMt9xTjXgYFQpgJgD4pcW7cGy74= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=lWonCeT6; arc=none smtp.client-ip=209.85.216.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="lWonCeT6" Received: by mail-pj1-f54.google.com with SMTP id 98e67ed59e1d1-38511175ad3so3137807a91.2 for ; Mon, 13 Jul 2026 22:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784008033; x=1784612833; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=gzRBzQNIlPOcB9+UJSW/ZjK3CK6H+ocXVlUvjqfeJYA=; b=lWonCeT66FfKSOi6JvYhuygZqllX6IUbfVjBBrSaC0sOTNBY/zOjf3WdqNq7YtW4Kn 63K0ASF8xIXve0pRs+vr2peAWfDr2P/dkVtaaDPEtTMaTO6DgL5hFVrT5F2XGiRMMigk 5zD0CTFx/aq13JH0hvCOPTaUJwPMSJK2ohDeARF6dnbYQR91Dth7QVcfa9OKt9EraylK aHhcDf510bDjAVs2S8suRo5VVo//FreNlVFYwstZDu6v3n+y3dItqYaNfYjFekCvLE8U zRCeiL/O0nNefHGLd2PfBe1aUPWxIoQIZe+3xBnNa1sn9tIg0rXNpYoX7Ueueip2WuMW +42Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784008033; x=1784612833; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=gzRBzQNIlPOcB9+UJSW/ZjK3CK6H+ocXVlUvjqfeJYA=; b=Zu+RxkgEJSZJ4uFxfGgbSjhXmrx0V7EOIjC72VBOyhpMp2PbFCuCJqHcA+byg06zMt Zx9Ua4N8+g6g2bZ+b6t9Ch4cy9sEZ96IgeRII+yvI74c39XuQU2fZd+OZ8J/GIRV/mll hd4YJf8nz/xPlmrpBRwFZ5K6fgUQ8BqClOQAb9XKrRHyQgnAXkbb255zDsdgfrxv0rtm V8StydGrgbjM8qjJwxcas4PVKO4RpMAnop3ndNfYGrzUhJTFkPFAjR0InTaoEinKwPJ3 BQC8FS4GdXnZ4IB9fEQTvkFG/GAkl0FnXXwTGdzfRQZpDgkHbq1JZ9QNWBJACT7FuKnH NQFg== X-Forwarded-Encrypted: i=1; AHgh+Rr9hoEHTRCayrSQdarTDPnBIFyqovsLdhJDWA2rKn7hlBlhtR+RtRZCSvT0Ex+n3gbBg5/tl77MLI3E3Jk=@vger.kernel.org X-Gm-Message-State: AOJu0YwxhgBTsi9xMtBbhsPU7sM5/KYfJJgL9kSNBlJmfzpf2/RIrulx XNFCz1pHxKNQC/5wkiyysNGqBM4prfxpsDvSl8ldQlu/PEUMai6Xzw82XA+GvoqI X-Gm-Gg: AfdE7cloKhipkMY0SJfbFYegGWCn7TcqyaAjB487p6TxvO90x6S/GghVKTzMqSZsR17 I/nWM2/EWpnU/NPVcKWrz7On/T3pM3G4wuQJkRHcW7AMgKF1uUbH2BcZZsNWCveZCNqKVBbuo7K fP+92sHROW1cFQiOtsBv6MpqyuXx06N3mVMOSoTWWoYti9S0EXWu7nTlb+dM02DdsZ5HqjDM4NN dmmlnDJFDxTH5fqi/9wX4UArkabDpgL9jpZZgKpqiKKwb86+erYjsrvTwezUR65H/2zNPCKvk04 7ew0vEMUThZOiOQ0OaJHrQnCno4ogHLLMh3ztr6eUHS3ap7oSA5tZK2x5pBqP0B+I/qfzJtSZSL 7VGaZyVoEHK4drity18l9mqlqfAH9EAXLMh274gUv0h5KvSKTqMOC41AhmpoYahJku3RMQCZ92U XEzaBSC5KMnUQSi9ykUgI= X-Received: by 2002:a05:6a21:7a8b:b0:3bf:6f30:1ccd with SMTP id adf61e73a8af0-3c35754eec2mr1116078637.42.1784008032645; Mon, 13 Jul 2026 22:47:12 -0700 (PDT) Received: from i386.168.1.127 ([2402:a00:163:2ce9:9c6f:e28:3da8:7980]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3117483dec6sm77965054eec.11.2026.07.13.22.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 22:47:11 -0700 (PDT) From: Hrushiraj Gandhi To: linux-rockchip@lists.infradead.org Cc: heiko@sntech.de, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Hrushiraj Gandhi Subject: [PATCH v4 2/2] arm64: dts: rockchip: Add Vicharak Vaaman2 board Date: Tue, 14 Jul 2026 11:16:53 +0530 Message-ID: <20260714054653.266842-3-hrushirajg23@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260714054653.266842-1-hrushirajg23@gmail.com> References: <20260714054653.266842-1-hrushirajg23@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device tree for the Vicharak Vaaman2, a single-board computer based on the Rockchip RK3588 SoC. The board features: - RK3588 SoC with 4x Cortex-A76 (big) + 4x Cortex-A55 (little) - eMMC storage via SDHCI (HS400) - microSD card via SDMMC - RK806 PMIC on SPI2 providing all required power domains - Two RK8602/RK8603 CPU regulators on I2C0 (big clusters) - RK8602 NPU regulator on I2C1 - HYM8563 RTC on I2C0 - Status LED on GPIO2_C5 (active-low, heartbeat trigger) - UART2 as serial console at 1500000 baud - SARADC with 1.8V reference Signed-off-by: Hrushiraj Gandhi --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../dts/rockchip/rk3588-vicharak-vaaman2.dts | 547 ++++++++++++++++++ 2 files changed, 548 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 92114cb757cc..9213280d831b 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -214,6 +214,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-tiger-haikou-vi= deo-demo.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-turing-rk1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-vicharak-axon.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-vicharak-vaaman2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-coolpi-4b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-gameforce-ace.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts b/arc= h/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts new file mode 100644 index 000000000000..c176a969a268 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-vicharak-vaaman2.dts @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3588.dtsi" + +/ { + model =3D "Vicharak Vaaman2"; + compatible =3D "vicharak,vaaman2", "rockchip,rk3588"; + + aliases { + mmc0 =3D &sdmmc; + mmc1 =3D &sdhci; + serial2 =3D &uart2; + }; + + chosen { + stdout-path =3D "serial2:1500000n8"; + }; + + leds { + compatible =3D "gpio-leds"; + + status_led: status-led { + gpios =3D <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + function =3D LED_FUNCTION_STATUS; + default-state =3D "on"; + retain-state-suspended; + linux,default-trigger =3D "heartbeat"; + }; + + }; + + vcc20v_dcin: regulator-vcc20v-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc20v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <20000000>; + regulator-max-microvolt =3D <20000000>; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc20v_dcin>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc5v0_sys>; + }; + +}; + +&cpu_b0 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply =3D <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply =3D <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + + +&i2c0 { + pinctrl-0 =3D <&i2c0m2_xfer>; + pinctrl-names =3D "default"; + status =3D "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + fcs,suspend-voltage-selector =3D <1>; + reg =3D <0x42>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <550000>; + regulator-name =3D "vdd_cpu_big0_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible =3D "rockchip,rk8603", "rockchip,rk8602"; + fcs,suspend-voltage-selector =3D <1>; + reg =3D <0x43>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt =3D <1050000>; + regulator-min-microvolt =3D <550000>; + regulator-name =3D "vdd_cpu_big1_s0"; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + #clock-cells =3D <0>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_int>; + wakeup-source; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1m2_xfer>; + status =3D "okay"; + + vdd_npu_s0: regulator@42 { + compatible =3D "rockchip,rk8602"; + reg =3D <0x42>; + fcs,suspend-voltage-selector =3D <1>; + regulator-name =3D "vdd_npu_s0"; + regulator-boot-on; + regulator-enable-ramp-delay =3D <500>; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <2300>; + vin-supply =3D <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width =3D <8>; + full-pwr-cycle-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + no-sd; + no-sdio; + non-removable; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vcc_1v8_s3>; + status =3D "okay"; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios =3D <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency =3D <200000000>; + no-mmc; + no-sdio; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&spi2 { + assigned-clock-rates =3D <200000000>; + assigned-clocks =3D <&cru CLK_SPI2>; + num-cs =3D <1>; + pinctrl-0 =3D <&spi2m2_cs0 &spi2m2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic@0 { + compatible =3D "rockchip,rk806"; + reg =3D <0>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&gpio0>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency =3D <1000000>; + + vcc1-supply =3D <&vcc5v0_sys>; + vcc2-supply =3D <&vcc5v0_sys>; + vcc3-supply =3D <&vcc5v0_sys>; + vcc4-supply =3D <&vcc5v0_sys>; + vcc5-supply =3D <&vcc5v0_sys>; + vcc6-supply =3D <&vcc5v0_sys>; + vcc7-supply =3D <&vcc5v0_sys>; + vcc8-supply =3D <&vcc5v0_sys>; + vcc9-supply =3D <&vcc5v0_sys>; + vcc10-supply =3D <&vcc5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <750000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_vdenc_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <675000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + regulator-name =3D "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + hym8563 { + rtc_int: rtc-int { + rockchip,pins =3D + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply =3D <&avcc_1v8_s0>; + status =3D "okay"; +}; + +&tsadc { + status =3D "okay"; +}; + +&uart2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart2m0_xfer>; + status =3D "okay"; +}; --=20 2.47.3