From nobody Sat Jul 25 20:06:06 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DDF052A1B2 for ; Tue, 14 Jul 2026 04:31:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784003467; cv=none; b=Y/U/p4ptrSt2/mypymcvCKk7Eiv6im4IAZB5kCZ2JfMXPviIsrCFKpmJu91jbSlNpKwlbaFB2bxVgYK6oh3GO0WnhnlMSjz4SAkHCjbNiEktw0mJ69jDbqMH4sQ55zc/qv1wNgJJinysbObwZ3sIiPmtpAkSowarX4VGgFUdiQo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784003467; c=relaxed/simple; bh=wwOd20lXbLyFUgLp6XlXF5kS4CMEjRqPUxQPJNBNrbo=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=BdEBTWwqkSFTxLihrgQQNFRaVX96ypOuI2KppKlR3h4PfHSl/47glLDfu7lzrVyf+PW/JbpOGLOWl6SuxxFdSrV5LSUx7NzRVmrGgvvXAp+wfsDE8KCH/pFelp5tCCTiwWk5HEOgbphfqZMkAq3yWHeSIFgER11hpYchOfoLjmc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=C10YY+lQ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="C10YY+lQ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CC9111570; Mon, 13 Jul 2026 21:30:58 -0700 (PDT) Received: from a085714.blr.arm.com (a085714.arm.com [10.164.19.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E48EE3F7B4; Mon, 13 Jul 2026 21:31:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1784003463; bh=wwOd20lXbLyFUgLp6XlXF5kS4CMEjRqPUxQPJNBNrbo=; h=From:To:Cc:Subject:Date:From; b=C10YY+lQANwP9BvipjJwfSbpL3ww8YkQuFwwkdNfPa+SBVVLk/JuII3UHRuDMtZFL 4xf+PJymhCPMd0a47lNZQqBAvPgvJw/iGjeSZy4etup3mWjQQDhmfqWA+z5tyIPvbc zeL4XHyKuV7xz8+G2R62OOhhRkdXpBxcfTYK3ahU= From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , David Hildenbrand , linux-kernel@vger.kernel.org Subject: [PATCH] arm64/mm: Rename PGD_SIZE as PGD_TABLE_SIZE Date: Tue, 14 Jul 2026 10:00:50 +0530 Message-ID: <20260714043050.2984188-1-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" PXD_SIZE represents the virtual address range size covered by a single page table entry on a given page table level. On arm64 PGD entry address span is represented with PGDIR_XXX macros instead while PGD_SIZE has been referring to size of the PGD table itself. So PGD_SIZE has been some what confusing. Rename PGD_SIZE as PGD_TABLE_SIZE making it explicit that it represents PGD table size rather than virtual address range covered by a single PGD entry. While here, also move PGD_TABLE_SIZE inside pgtable-hwdef.h header. No functional change. Cc: Catalin Marinas Cc: Will Deacon Cc: Ryan Roberts Cc: David Hildenbrand (Arm) Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/pgalloc.h | 2 -- arch/arm64/include/asm/pgtable-hwdef.h | 1 + arch/arm64/mm/mmu.c | 2 +- arch/arm64/mm/pgd.c | 6 +++--- 4 files changed, 5 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgal= loc.h index 1b4509d3382c..d81df17663ee 100644 --- a/arch/arm64/include/asm/pgalloc.h +++ b/arch/arm64/include/asm/pgalloc.h @@ -17,8 +17,6 @@ #define __HAVE_ARCH_PUD_FREE #include =20 -#define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) - #if CONFIG_PGTABLE_LEVELS > 2 =20 static inline void __pud_populate(pud_t *pudp, phys_addr_t pmdp, pudval_t = prot) diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/as= m/pgtable-hwdef.h index 72f31800c703..241fc749455d 100644 --- a/arch/arm64/include/asm/pgtable-hwdef.h +++ b/arch/arm64/include/asm/pgtable-hwdef.h @@ -83,6 +83,7 @@ #define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) #define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT)) +#define PGD_TABLE_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) =20 /* * Contiguous page definitions. diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index a25d8beacc83..bd9330fef173 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -1356,7 +1356,7 @@ static int __init map_entry_trampoline(void) pgprot_val(prot) &=3D ~PTE_NG; =20 /* Map only the text into the trampoline page table */ - memset(tramp_pg_dir, 0, PGD_SIZE); + memset(tramp_pg_dir, 0, PGD_TABLE_SIZE); early_create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, entry_tramp_text_size(), prot, pgd_pgtable_alloc_init_mm, NO_BLOCK_MAPPINGS); diff --git a/arch/arm64/mm/pgd.c b/arch/arm64/mm/pgd.c index bf5110b91e2f..4f7c6416158b 100644 --- a/arch/arm64/mm/pgd.c +++ b/arch/arm64/mm/pgd.c @@ -19,7 +19,7 @@ static struct kmem_cache *pgd_cache __ro_after_init; =20 static bool pgdir_is_page_size(void) { - if (PGD_SIZE =3D=3D PAGE_SIZE) + if (PGD_TABLE_SIZE =3D=3D PAGE_SIZE) return true; if (CONFIG_PGTABLE_LEVELS =3D=3D 4) return !pgtable_l4_enabled(); @@ -56,12 +56,12 @@ void __init pgtable_cache_init(void) * With 52-bit physical addresses, the architecture requires the * top-level table to be aligned to at least 64 bytes. */ - BUILD_BUG_ON(!IS_ALIGNED(PGD_SIZE, 64)); + BUILD_BUG_ON(!IS_ALIGNED(PGD_TABLE_SIZE, 64)); #endif =20 /* * Naturally aligned pgds required by the architecture. */ - pgd_cache =3D kmem_cache_create("pgd_cache", PGD_SIZE, PGD_SIZE, + pgd_cache =3D kmem_cache_create("pgd_cache", PGD_TABLE_SIZE, PGD_TABLE_SI= ZE, SLAB_PANIC, NULL); } --=20 2.43.0