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Tue, 14 Jul 2026 03:30:59 +0000 From: Hal Feng To: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Palmer Dabbelt , Paul Walmsley , Albert Ou Cc: Hal Feng , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v22 1/3] dt-bindings: pwm: opencores: Update compatibles, examples and maintainers Date: Tue, 14 Jul 2026 11:30:48 +0800 Message-ID: <20260714033050.44952-2-hal.feng@starfivetech.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20260714033050.44952-1-hal.feng@starfivetech.com> References: <20260714033050.44952-1-hal.feng@starfivetech.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SH0PR01CA0023.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:5::35) To ZQ2PR01MB1307.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:7::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ2PR01MB1307:EE_|ZQ2PR01MB1324:EE_ X-MS-Office365-Filtering-Correlation-Id: 0abcb16a-01ff-4a7f-e9b4-08dee15852bd X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|52116014|376014|1800799024|366016|56012099006|38350700014|18002099003|3023799007|22082099003; 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charset="utf-8" Remove the jh8100 compatible since the JH8100 SoC has been canceled and will not be released. Add the jhb100 compatible to replace it. Change the register size in examples to 0x10, since an OpenCores PTC IP has only 4 32-bit registers: CNTR, HRC, LRC and CTRL. I will maintain this pwm module in place of William. Acked-by: Conor Dooley Fixes: 2529085831b0 ("dt-bindings: pwm: Add bindings for OpenCores PWM Cont= roller") Signed-off-by: Hal Feng --- Documentation/devicetree/bindings/pwm/opencores,pwm.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Doc= umentation/devicetree/bindings/pwm/opencores,pwm.yaml index 52a59d245cdb..42c5d2b6326d 100644 --- a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: OpenCores PWM controller =20 maintainers: - - William Qiu + - Hal Feng =20 description: The OpenCores PTC ip core contains a PWM controller. When operating in P= WM @@ -23,7 +23,7 @@ properties: - enum: - starfive,jh7100-pwm - starfive,jh7110-pwm - - starfive,jh8100-pwm + - starfive,jhb100-pwm - const: opencores,pwm-v1 =20 reg: @@ -49,7 +49,7 @@ examples: - | pwm@12490000 { compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; - reg =3D <0x12490000 0x10000>; + reg =3D <0x12490000 0x10>; clocks =3D <&clkgen 181>; resets =3D <&rstgen 109>; #pwm-cells =3D <3>; --=20 2.43.2 From nobody Sat Jul 25 20:03:47 2026 Received: from CHN02-SH0-obe.outbound.protection.partner.outlook.cn (mail-sh0chn02on2095.outbound.protection.partner.outlook.cn [139.219.146.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1616930F927; Tue, 14 Jul 2026 04:04:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=139.219.146.95 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784001890; 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charset="utf-8" Each of the StarFive JH7100/JH7110 SoCs has 8 OpenCores PTC IP cores. One OpenCores PTC IP core can output one PWM channel. Change the register size to 0x10, since an OpenCores PTC IP has only 4 32-bit registers: CNTR, HRC, LRC and CTRL. Fixes: 8d01f741a046 ("riscv: dts: starfive: jh7110: Add PWM node and pins c= onfiguration") Fixes: 5e598b99fedf ("riscv: dts: starfive: jh7100: Add PWM node and pins c= onfiguration") Signed-off-by: Hal Feng --- .../boot/dts/starfive/jh7100-common.dtsi | 28 ++++++-- arch/riscv/boot/dts/starfive/jh7100.dtsi | 67 ++++++++++++++++++- .../boot/dts/starfive/jh7110-common.dtsi | 27 ++++++-- .../boot/dts/starfive/jh7110-milkv-mars.dts | 6 +- .../dts/starfive/jh7110-milkv-marscm.dtsi | 6 +- .../dts/starfive/jh7110-pine64-star64.dts | 6 +- .../jh7110-starfive-visionfive-2-lite.dtsi | 6 +- .../jh7110-starfive-visionfive-2.dtsi | 6 +- arch/riscv/boot/dts/starfive/jh7110.dtsi | 67 ++++++++++++++++++- 9 files changed, 198 insertions(+), 21 deletions(-) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7100-common.dtsi index ae1a6aeb0aea..85106545090e 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -199,13 +199,23 @@ GPO_I2C2_PAD_SDA_OEN, }; }; =20 - pwm_pins: pwm-0 { - pwm-pins { + pwm0_pins: pwm0-0 { + pwm0-pins { pinmux =3D , - ; + bias-disable; + drive-strength =3D <35>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + pwm1_pins: pwm1-0 { + pwm1-pins { + pinmux =3D ; @@ -359,9 +369,15 @@ &osc_aud { clock-frequency =3D <27000000>; }; =20 -&pwm { +&pwm0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm0_pins>; + status =3D "okay"; +}; + +&pwm1 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&pwm_pins>; + pinctrl-0 =3D <&pwm1_pins>; status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts= /starfive/jh7100.dtsi index 7de0732b8eab..90438df1f74d 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -360,9 +360,72 @@ watchdog@12480000 { <&rstgen JH7100_RSTN_WDT>; }; =20 - pwm: pwm@12490000 { + pwm0: pwm@12490000 { compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; - reg =3D <0x0 0x12490000 0x0 0x10000>; + reg =3D <0x0 0x12490000 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm1: pwm@12490010 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12490010 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm2: pwm@12490020 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12490020 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm3: pwm@12490030 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12490030 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm4: pwm@12498000 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12498000 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm5: pwm@12498010 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12498010 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm6: pwm@12498020 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12498020 0x0 0x10>; + clocks =3D <&clkgen JH7100_CLK_PWM_APB>; + resets =3D <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm7: pwm@12498030 { + compatible =3D "starfive,jh7100-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x12498030 0x0 0x10>; clocks =3D <&clkgen JH7100_CLK_PWM_APB>; resets =3D <&rstgen JH7100_RSTN_PWM_APB>; #pwm-cells =3D <3>; diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/b= oot/dts/starfive/jh7110-common.dtsi index a7a1c09a2c90..64de468f2c31 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -326,9 +326,14 @@ uboot@100000 { }; }; =20 -&pwm { +&pwm0 { pinctrl-names =3D "default"; - pinctrl-0 =3D <&pwm_pins>; + pinctrl-0 =3D <&pwm0_pins>; +}; + +&pwm1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pwm1_pins>; }; =20 &spi0 { @@ -528,12 +533,22 @@ GPOEN_ENABLE, }; }; =20 - pwm_pins: pwm-0 { - pwm-pins { + pwm0_pins: pwm0-0 { + pwm0-pins { pinmux =3D , - ; + bias-disable; + drive-strength =3D <12>; + input-disable; + input-schmitt-disable; + slew-rate =3D <0>; + }; + }; + + pwm1_pins: pwm1-0 { + pwm1-pins { + pinmux =3D ; bias-disable; diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts b/arch/risc= v/boot/dts/starfive/jh7110-milkv-mars.dts index 21873612d993..54013c70f4b4 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts @@ -68,7 +68,11 @@ &phy0 { motorcomm,tx-clk-adj-enabled; }; =20 -&pwm { +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi b/arch/r= iscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi index 025471061d43..31afac27b86d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm.dtsi @@ -87,7 +87,11 @@ &phy0 { motorcomm,tx-clk-adj-enabled; }; =20 -&pwm { +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts b/arch/r= iscv/boot/dts/starfive/jh7110-pine64-star64.dts index aec7ae3d1f5b..a9e82f25efde 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts @@ -95,7 +95,11 @@ &phy1 { motorcomm,tx-clk-100-inverted; }; =20 -&pwm { +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite= .dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi index f8797a666dbf..85b56a72dff7 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-lite.dtsi @@ -74,7 +74,11 @@ &phy0 { tx-internal-delay-ps =3D <1500>; }; =20 -&pwm { +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi= b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index edc8f4588133..35208f95cd3d 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -73,7 +73,11 @@ &pcie1 { status =3D "okay"; }; =20 -&pwm { +&pwm0 { + status =3D "okay"; +}; + +&pwm1 { status =3D "okay"; }; =20 diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 9c3e4598747e..82ea63f715b0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -846,9 +846,72 @@ i2stx1: i2s@120c0000 { status =3D "disabled"; }; =20 - pwm: pwm@120d0000 { + pwm0: pwm@120d0000 { compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; - reg =3D <0x0 0x120d0000 0x0 0x10000>; + reg =3D <0x0 0x120d0000 0x0 0x10>; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm1: pwm@120d0010 { + compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x120d0010 0x0 0x10>; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm2: pwm@120d0020 { + compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x120d0020 0x0 0x10>; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm3: pwm@120d0030 { + compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x120d0030 0x0 0x10>; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm4: pwm@120d8000 { + compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x120d8000 0x0 0x10>; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm5: pwm@120d8010 { + compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg =3D <0x0 0x120d8010 0x0 0x10>; + clocks =3D <&syscrg JH7110_SYSCLK_PWM_APB>; + resets =3D <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + pwm6: pwm@120d8020 { + compatible =3D "starfive,jh7110-pwm", "opencores,pwm-v1"; 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charset="utf-8" Add PWM driver for OpenCores PTC IP core. Signed-off-by: Hal Feng --- MAINTAINERS | 6 + drivers/pwm/Kconfig | 12 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ocores.c | 298 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 317 insertions(+) create mode 100644 drivers/pwm/pwm-ocores.c diff --git a/MAINTAINERS b/MAINTAINERS index 806bd2d80d15..6443c2be49d1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20271,6 +20271,12 @@ F: Documentation/i2c/busses/i2c-ocores.rst F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h =20 +OPENCORES PWM DRIVER +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/opencores,pwm.yaml +F: drivers/pwm/pwm-ocores.c + OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index e8886a9b64d9..1268c07d07f1 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -546,6 +546,18 @@ config PWM_NTXEC controller found in certain e-book readers designed by the original design manufacturer Netronix. =20 +config PWM_OCORES + tristate "OpenCores PTC PWM support" + depends on HAS_IOMEM && OF + depends on COMMON_CLK + depends on ARCH_STARFIVE || COMPILE_TEST + help + PWM driver for OpenCores PTC IP core. + For details see https://opencores.org/projects/ptc. + + To compile this driver as a module, choose M here: the module + will be called pwm-ocores. + config PWM_OMAP_DMTIMER tristate "OMAP Dual-Mode Timer PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 5630a521a7cf..4d2d14c4852f 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) +=3D pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) +=3D pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) +=3D pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) +=3D pwm-ntxec.o +obj-$(CONFIG_PWM_OCORES) +=3D pwm-ocores.o obj-$(CONFIG_PWM_OMAP_DMTIMER) +=3D pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) +=3D pwm-pca9685.o obj-$(CONFIG_PWM_PXA) +=3D pwm-pxa.o diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode 100644 index 000000000000..f873089a385b --- /dev/null +++ b/drivers/pwm/pwm-ocores.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OpenCores PTC PWM Driver + * + * https://opencores.org/projects/ptc + * + * Copyright (C) 2018-2026 StarFive Technology Co., Ltd. + * + * Limitations: + * - The hardware only supports inverted polarity. + * - The hardware minimum period / non-zero duty_cycle is (1 / pwm_apb clo= ck frequency). + * - The hardware maximum period / duty_cycle of PWM is (U32_MAX / pwm_apb= clock frequency). + * - The output is immediately set to low when the module is disabled. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define OCPWM_HRC 0x4 +#define OCPWM_LRC 0x8 +#define OCPWM_CTRL 0xC + +#define OCPWM_CTRL_EN BIT(0) +#define OCPWM_CTRL_OE BIT(3) +#define OCPWM_CTRL_RST BIT(7) + +#define OCPWM_NUM_SAVED_REGS 3 + +struct ocores_pwm_device { + void __iomem *base; + struct clk *clk; + unsigned long clk_rate; + struct reset_control *rst; + u32 saved_regs[OCPWM_NUM_SAVED_REGS]; +}; + +static int ocores_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct ocores_pwm_device *ddata =3D pwmchip_get_drvdata(chip); + u32 period_data, duty_data, ctrl_data; + int ret; + + ret =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); + if (ret < 0) + return ret; + + period_data =3D readl(ddata->base + OCPWM_LRC); + duty_data =3D readl(ddata->base + OCPWM_HRC); + ctrl_data =3D readl(ddata->base + OCPWM_CTRL); + + state->period =3D DIV_ROUND_UP_ULL((u64)period_data * NSEC_PER_SEC, ddata= ->clk_rate); + state->duty_cycle =3D DIV_ROUND_UP_ULL((u64)duty_data * NSEC_PER_SEC, dda= ta->clk_rate); + if (state->duty_cycle > state->period) + state->duty_cycle =3D state->period; + + state->polarity =3D PWM_POLARITY_INVERSED; + state->enabled =3D (ctrl_data & OCPWM_CTRL_EN) ? true : false; + + pm_runtime_put(pwmchip_parent(chip)); + + return 0; +} + +static int ocores_pwm_apply(struct pwm_chip *chip, + struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct ocores_pwm_device *ddata =3D pwmchip_get_drvdata(chip); + bool was_enabled =3D pwm_is_enabled(pwm); + u64 period_data, duty_data; + int ret; + + if (state->polarity !=3D PWM_POLARITY_INVERSED) + return -EINVAL; + + if (!state->enabled) { + if (was_enabled) { + writel(0, ddata->base + OCPWM_CTRL); + pm_runtime_put(pwmchip_parent(chip)); + } + return 0; + } + + period_data =3D mul_u64_u32_div(state->period, ddata->clk_rate, NSEC_PER_= SEC); + if (period_data > U32_MAX) + period_data =3D U32_MAX; + + duty_data =3D mul_u64_u32_div(state->duty_cycle, ddata->clk_rate, NSEC_PE= R_SEC); + if (duty_data > U32_MAX) + duty_data =3D U32_MAX; + + if (!period_data) + return -EINVAL; + + if (!was_enabled) { + ret =3D pm_runtime_resume_and_get(pwmchip_parent(chip)); + if (ret < 0) + return ret; + } + + writel(0, ddata->base + OCPWM_CTRL); + writel(OCPWM_CTRL_RST, ddata->base + OCPWM_CTRL); + + writel(period_data, ddata->base + OCPWM_LRC); + writel(duty_data, ddata->base + OCPWM_HRC); + writel(OCPWM_CTRL_OE | OCPWM_CTRL_EN, ddata->base + OCPWM_CTRL); + + return 0; +} + +static const struct pwm_ops ocores_pwm_ops =3D { + .get_state =3D ocores_pwm_get_state, + .apply =3D ocores_pwm_apply, +}; + +static int ocores_pwm_runtime_suspend(struct device *dev) +{ + struct ocores_pwm_device *ddata =3D dev_get_drvdata(dev); + + clk_disable_unprepare(ddata->clk); + + return 0; +} + +static int ocores_pwm_runtime_resume(struct device *dev) +{ + struct ocores_pwm_device *ddata =3D dev_get_drvdata(dev); + int ret; + + ret =3D clk_prepare_enable(ddata->clk); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable clock\n"); + + return 0; +} + +static int __maybe_unused ocores_pwm_suspend(struct device *dev) +{ + struct ocores_pwm_device *ddata =3D dev_get_drvdata(dev); + int ret, i; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + for (i =3D 0; i < OCPWM_NUM_SAVED_REGS; i++) + ddata->saved_regs[i] =3D readl(ddata->base + 4 + 4 * i); + + pm_runtime_put_sync(dev); + + return pm_runtime_force_suspend(dev); +} + +static int __maybe_unused ocores_pwm_resume(struct device *dev) +{ + struct ocores_pwm_device *ddata =3D dev_get_drvdata(dev); + int ret, i; + + ret =3D pm_runtime_force_resume(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) + return ret; + + writel(0, ddata->base + OCPWM_CTRL); + writel(OCPWM_CTRL_RST, ddata->base + OCPWM_CTRL); + for (i =3D 0; i < OCPWM_NUM_SAVED_REGS; i++) + writel(ddata->saved_regs[i], ddata->base + 4 + 4 * i); + + pm_runtime_put_sync(dev); + + return 0; +} + +static const struct dev_pm_ops ocores_pwm_pm_ops =3D { + RUNTIME_PM_OPS(ocores_pwm_runtime_suspend, + ocores_pwm_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(ocores_pwm_suspend, ocores_pwm_resume) +}; + +static void ocores_pwm_pm_disable(void *data) +{ + struct device *dev =3D data; + struct ocores_pwm_device *ddata =3D dev_get_drvdata(dev); + + pm_runtime_disable(dev); + + if (!pm_runtime_status_suspended(dev)) { + /* Balance the reference held while the PWM is enabled. */ + if (readl(ddata->base + OCPWM_CTRL) & OCPWM_CTRL_EN) + pm_runtime_put_noidle(dev); + + ocores_pwm_runtime_suspend(dev); + } + + reset_control_assert(ddata->rst); +} + +static int ocores_pwm_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct ocores_pwm_device *ddata; + struct pwm_chip *chip; + int ret; + + chip =3D devm_pwmchip_alloc(dev, 1, sizeof(*ddata)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + + chip->ops =3D &ocores_pwm_ops; + ddata =3D pwmchip_get_drvdata(chip); + + ddata->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(ddata->base)) + return dev_err_probe(dev, PTR_ERR(ddata->base), + "Failed to map IO resources\n"); + + ddata->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(ddata->clk)) + return dev_err_probe(dev, PTR_ERR(ddata->clk), + "Failed to get clock\n"); + + ddata->clk_rate =3D clk_get_rate(ddata->clk); + if (!ddata->clk_rate || ddata->clk_rate > NSEC_PER_SEC) + return dev_err_probe(dev, -EINVAL, + "Invalid clock rate: %lu\n", ddata->clk_rate); + + ddata->rst =3D devm_reset_control_get_optional_shared(dev, NULL); + if (IS_ERR(ddata->rst)) + return dev_err_probe(dev, PTR_ERR(ddata->rst), + "Failed to get reset\n"); + + platform_set_drvdata(pdev, ddata); + + ret =3D ocores_pwm_runtime_resume(dev); + if (ret) + return ret; + + ret =3D reset_control_deassert(ddata->rst); + if (ret) + goto err_clk_disable; + + ret =3D pm_runtime_set_active(dev); + if (ret) + goto err_reset_assert; + + pm_runtime_get_noresume(dev); + pm_runtime_enable(dev); + + if (!(readl(ddata->base + OCPWM_CTRL) & OCPWM_CTRL_EN)) + pm_runtime_put_sync(dev); + + ret =3D devm_add_action_or_reset(dev, ocores_pwm_pm_disable, dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to add pm disable action\n"); + + ret =3D devm_pwmchip_add(dev, chip); + if (ret < 0) + return dev_err_probe(dev, ret, "Could not register PWM chip\n"); + + return 0; + +err_reset_assert: + reset_control_assert(ddata->rst); +err_clk_disable: + ocores_pwm_runtime_suspend(dev); + return dev_err_probe(dev, ret, "Failed to init pwm power\n"); +} + +static const struct of_device_id ocores_pwm_of_match[] =3D { + { .compatible =3D "opencores,pwm-v1" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); + +static struct platform_driver ocores_pwm_driver =3D { + .probe =3D ocores_pwm_probe, + .driver =3D { + .name =3D "ocores-pwm", + .of_match_table =3D ocores_pwm_of_match, + .pm =3D pm_ptr(&ocores_pwm_pm_ops), + }, +}; +module_platform_driver(ocores_pwm_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("OpenCores PTC PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.43.2