From nobody Sat Jul 25 20:48:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 722CA1F0995; Tue, 14 Jul 2026 00:44:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783989852; cv=none; b=aFH0hyTtR//NyKYssNExLraUBU6gIRHJ8pJwuXlSWGzEWx1iaE5fqx+4SHnMuMkrQbtNZB73Je4vZy3TqUpdcIAksXpuU6rSu17feZOUxtW5eHlDK78JnB90qT+drfUMS3GhUPBZTOExpHj+me2K7cvAvuHYGZtLyrBvTv9F9gY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783989852; c=relaxed/simple; bh=7K+mVOAfd7O7mBrvuCC+ocZBM74EZhw605+3UoxF3Sg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IfWpiblyXqLW0y+mbSBUFa9oLrhMzhDtJdtEF2mlf1Hsd/kLhYGrXggfZpHolemcWPMdC2ebloJfzHdsbBY+3m04O+p/jv/M/rIGsWKaNPidk9GbF3XdZOX+rZ5UwYHe1kZ8Dpe9oSlRvap5b4Rnmf7+rNgBP95O+KfKs58Pbv8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Eb+JFn7g; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Eb+JFn7g" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783989850; x=1815525850; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7K+mVOAfd7O7mBrvuCC+ocZBM74EZhw605+3UoxF3Sg=; b=Eb+JFn7g/I3URuOTvI8fQEIqpPxmtk+g4UEhcfhYMVjTsValX7h7+B9m T2IFWT59ZX7QATchiGi1/ghG046z4LBcEr4kuBbk2aI7XYoJ2l6RC4aC8 Ocp/1/SZQUBlBpGP4gVC4Ao45NIgyv3Z06f3Ns4XBSyWcuQXAjOFQiacv V7ma9gcqegPwPN73mdDpIKRGMXbXGz/EvWbXABYn8lfiX6kb7XkMIB1GQ hIG3O3XTrpG958XFr3zbHU9y9cnbCbYZTJU1UV6uTDVv9af1B8jdaV9Ie eldaIgdJREVo5835yNvFcoaXP1EJmdM5BWvGeCsFPkmKJZT3/iVUAY8VT Q==; X-CSE-ConnectionGUID: I65hdH9MR7SjXbqW14Khfw== X-CSE-MsgGUID: BFsOsyUiRI2o498vUSI8Mw== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="72130633" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="72130633" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:10 -0700 X-CSE-ConnectionGUID: 6phinN0KSYSqEIXX3odJcg== X-CSE-MsgGUID: 4ZyhoFBHTneRZsWvhqCSZA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="260582114" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.attlocal.net) ([10.124.220.48]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:09 -0700 From: Thomas Falcon To: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v2 1/6] perf mem: Fix size tracking for mem_lvl's in perf_script__meminfo_scnprintf() Date: Mon, 13 Jul 2026 19:43:54 -0500 Message-ID: <20260714004359.179451-2-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714004359.179451-1-thomas.falcon@intel.com> References: <20260714004359.179451-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When printing memory info in perf script, the entire size of the buffer is passed to perf_mem__lvl_scnprintf() instead of the remaining size. Pass the remaining buffer size instead. This issue was detected by sashiko during an internal code review. Assisted-by: Sashiko:gemini-3.1-pro-preview Fixes: fdefc3750e847 ("perf mem: Print memory operation type") Signed-off-by: Thomas Falcon Reviewed-by: Dapeng Mi --- tools/perf/util/mem-events.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 0b49fce251fc..4e490f9cd348 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -610,7 +610,7 @@ int perf_script__meminfo_scnprintf(char *out, size_t sz= , const struct mem_info * i +=3D scnprintf(out, sz, "|OP "); i +=3D perf_mem__op_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|LVL "); - i +=3D perf_mem__lvl_scnprintf(out + i, sz, mem_info); + i +=3D perf_mem__lvl_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|SNP "); i +=3D perf_mem__snp_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|TLB "); --=20 2.43.0 From nobody Sat Jul 25 20:48:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEE841FECCD; Tue, 14 Jul 2026 00:44:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.16 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783989854; cv=none; b=ETUjSaRvERSfAWpWfXOOo/TxVBZtw7QbIKqvF8L6YkcCSTvh9+Uc8G1iSTbHWHxI+w2XAxc9J62fHhiUjO0wX5ebZFJst5Sp0reK24/v2Oh2QGC4AuuGhGh1gGPn39sjH4Lto6/Fltbizg/UYA9GG+DUC7B9hB5MFlZ1+zNI0qI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783989854; c=relaxed/simple; bh=/5hsfENeOEAJaPXIi53/k71Z8g4IBYqmgq7Y9Imm1AY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DXZNobP9YX98HxFHqlV4E5d/6WlUG6mGKUEpbMyeGCByYwC/G0288wsno2f0yZxpAnw1mO8ITyhNIPuIIhjDgiBg+W0PtXaRKmGDRblwIBcljIbQZKRGjkuSB9TyPPY0+sEeAuY5lTcPJycWSyCPZQwFP+vVCgzuacXofiTLaQ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PwMOneHC; arc=none smtp.client-ip=192.198.163.16 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PwMOneHC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783989852; x=1815525852; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/5hsfENeOEAJaPXIi53/k71Z8g4IBYqmgq7Y9Imm1AY=; b=PwMOneHCxhp3KDXiiC4j+/2uz0i54sGysUXXTCIbJlG6RFzWBQqHF9oZ c+QGfaCbJnY2z+zQHctSO4yXSl1HhEbpLcxp6JqOhGUaqIIakGKaF76dx Cg+hxiIWOmEHQSXkYpn709lQDgxdH8s7vEIHqcfWQ8c1hDY0hF6Rb7FsD OVhdYiP6/uc52vFm4jBN59rcKJgWETQUrDfIy2oeQlrOs8YAbFxWbJ5EU t/7nxKEIhAJPBTDUWpQ6oksPOlCcJ2IQYuMon1KamKur6Sb/Z104p9aS9 7I7jaE/KPtT1Nl8/z409s0TWnANxe/eLxfKgs3Ubif89iBvWYh6i93zd0 Q==; X-CSE-ConnectionGUID: 6SWhznH0TYm5kQn6bm0Mvw== X-CSE-MsgGUID: zCdG/7kTTou8ompgLYxi5g== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="72130642" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="72130642" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:11 -0700 X-CSE-ConnectionGUID: VkgeOWDHTqyb86n8BjvBjQ== X-CSE-MsgGUID: 3z8dPtrqSnKuTfXCtxmbWw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="260582123" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.attlocal.net) ([10.124.220.48]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:10 -0700 From: Thomas Falcon To: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v2 2/6] perf mem: Add support for printing PERF_MEM_LVLNUM_L0 Date: Mon, 13 Jul 2026 19:43:55 -0500 Message-ID: <20260714004359.179451-3-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714004359.179451-1-thomas.falcon@intel.com> References: <20260714004359.179451-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Add support for printing PERF_MEM_LVLNUM_L0 in perf mem report. Assisted-by: Sashiko:gemini-3.1-pro-preview Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon Reviewed-by: Dapeng Mi --- tools/perf/Documentation/perf-record.txt | 2 +- tools/perf/util/bpf-filter.l | 1 + tools/perf/util/mem-events.c | 5 +++++ tools/perf/util/mem-events.h | 1 + 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Document= ation/perf-record.txt index 178f483140ed..b54032efe41c 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -212,7 +212,7 @@ OPTIONS The can be one of: (for any term) na, load, store, pfetch, exec (for mem_op) - l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) + l0, l1, l2, l3, l4, cxl, io, any_cache, lfb, ram, pmem (for mem_lvl) na, none, hit, miss, hitm, fwd, peer (for mem_snoop) remote (for mem_remote) na, locked (for mem_locked) diff --git a/tools/perf/util/bpf-filter.l b/tools/perf/util/bpf-filter.l index 6aa65ade3385..1be9df6550fc 100644 --- a/tools/perf/util/bpf-filter.l +++ b/tools/perf/util/bpf-filter.l @@ -131,6 +131,7 @@ store { return constant(PERF_MEM_OP_STORE); } pfetch { return constant(PERF_MEM_OP_PFETCH); } exec { return constant(PERF_MEM_OP_EXEC); } =20 +l0 { return constant(PERF_MEM_LVLNUM_L0); } l1 { return constant(PERF_MEM_LVLNUM_L1); } l2 { return constant(PERF_MEM_LVLNUM_L2); } l3 { return constant(PERF_MEM_LVLNUM_L3); } diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 4e490f9cd348..4fd48fd20055 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -391,6 +391,7 @@ static const char * const mem_lvlnum[] =3D { [PERF_MEM_LVLNUM_L4] =3D "L4", [PERF_MEM_LVLNUM_L2_MHB] =3D "L2 MHB", [PERF_MEM_LVLNUM_MSC] =3D "Memory-side Cache", + [PERF_MEM_LVLNUM_L0] =3D "L0", [PERF_MEM_LVLNUM_UNC] =3D "Uncached", [PERF_MEM_LVLNUM_CXL] =3D "CXL", [PERF_MEM_LVLNUM_IO] =3D "I/O", @@ -831,6 +832,8 @@ int mem_stat_index(const enum mem_stat_type mst, const = u64 val) } case PERF_MEM_STAT_CACHE: switch (src.mem_lvl_num) { + case PERF_MEM_LVLNUM_L0: + return MEM_STAT_CACHE_L0; case PERF_MEM_LVLNUM_L1: return MEM_STAT_CACHE_L1; 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13 Jul 2026 17:44:13 -0700 X-CSE-ConnectionGUID: A4/PyUzvSkOdompSr62JhQ== X-CSE-MsgGUID: xnTdkCtqRTuyhtjmiB6SXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="260582131" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.attlocal.net) ([10.124.220.48]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:11 -0700 From: Thomas Falcon To: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v2 3/6] perf tools: Show memory region in perf-c2c subcommand Date: Mon, 13 Jul 2026 19:43:56 -0500 Message-ID: <20260714004359.179451-4-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714004359.179451-1-thomas.falcon@intel.com> References: <20260714004359.179451-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Dapeng Mi Add memory region field to the cacheline list view to help users identify the memory region to which the cacheline belongs. The memory region field was included with the introduction of support for the Off-module Response facility (OMR) [1] in Intel's Diamond Rapids and Nova Lake architectures. An example of the new perf c2c output including the memory region field is shown below: Shared Data Cache Line Table (112 entries, sorted on Total HITMs) --------------- Cacheline -------------- Tot ------- Load Hitm= ------- Total Total Total Index Address Region Node PA cnt Hitm Total LclHitm = RmtHitm records Loads Stores 0 0xff1b7032a1e8c5c0 N/A 1 47 2.25% 50 44 = 6 1024 1023 1 1 0xff1b6ff3255bb880 N/A 0 11 1.62% 36 34 = 2 96 93 4 2 0xff1b70328e3b9880 N/A 1 13 1.49% 33 33 = 0 100 91 9 3 0xff1b70328b023800 N/A 1 1 1.40% 31 14 = 17 52 48 4 4 0xff1b70328e3b9c00 N/A 1 1 1.31% 29 27 = 2 67 33 34 5 0xff1b70328b0237c0 N/A 1 1 1.26% 28 10 = 18 154 150 4 6 0xff1b6ff3255bbc00 N/A 0 1 1.13% 25 25 = 0 48 25 23 7 0xff1b6ff3255bba40 N/A 0 1 0.99% 22 22 = 0 46 23 23 8 0xff3ab9ba50255c80 N/A N/A 0 0.77% 17 15 = 2 35 35 0 9 0xff3ab9ba503e3040 N/A N/A 0 0.77% 17 11 = 6 37 37 1 10 0xff1b703289e88f40 N/A 1 33 0.72% 16 9 = 7 69 63 6 11 0xff1b70328e3b9a40 N/A 1 1 0.68% 15 15 = 0 43 17 26 12 0xff1b7032c9fd6a40 N/A 1 15 0.68% 15 15 = 0 57 54 4 13 0xff1b7032a1e8c980 N/A 1 27 0.54% 12 11 = 1 761 761 0 14 0xff1b70727ffd57c0 N/A 1 7 0.54% 12 12 = 0 219 218 1 15 0xffffffffaefe2380 N/A 1 1 0.50% 11 8 = 3 14 14 0 Note: DMR simics does not support memory regions. Since the output is captured on SPR, the memory region field shows "N/A" for all cachelines. [1]: https://lore.kernel.org/all/20260114011750.350569-1-dapeng1.mi@linux.i= ntel.com/ Assisted-by: Sashiko:gemini-3.1-pro-preview Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon --- Changes in v2: -- Added missing new line in WARN_ONCE message in c2c_he__set_mem_region() --- tools/perf/builtin-c2c.c | 56 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 54 insertions(+), 2 deletions(-) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index c9584dbedf77..cba2e9f21ae7 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -74,6 +74,7 @@ struct c2c_hist_entry { unsigned long *nodeset; struct c2c_stats *node_stats; unsigned int cacheline_idx; + unsigned int mem_region; =20 struct compute_stats cstats; =20 @@ -281,6 +282,18 @@ static void c2c_he__set_node(struct c2c_hist_entry *c2= c_he, } } =20 +static void c2c_he__set_mem_region(struct c2c_hist_entry *c2c_he, + unsigned int mem_region) +{ + if (WARN_ONCE(mem_region > PERF_MEM_REGION_MEM7, + "WARNING: invalid memory region ID\n")) + return; + + /* Update mem_region only if it really accesses memory */ + if (mem_region >=3D PERF_MEM_REGION_MMIO) + c2c_he->mem_region =3D mem_region; +} + static void compute_stats(struct c2c_hist_entry *c2c_he, struct c2c_stats *stats, u64 weight) @@ -339,6 +352,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, struct addr_location al; struct mem_info *mi =3D NULL; struct callchain_cursor *cursor; + unsigned int mem_region; int ret; =20 addr_location__init(&al); @@ -366,6 +380,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, } =20 c2c_decode_stats(&stats, mi); + mem_region =3D mem_info__data_src(mi)->mem_region; =20 he =3D hists__add_entry_ops(&c2c_hists->hists, &c2c_entry_ops, &al, NULL, NULL, mi, NULL, @@ -382,6 +397,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, c2c_he__set_cpu(c2c_he, sample); c2c_he__set_node(c2c_he, sample); c2c_he__set_evsel(c2c_he, evsel); + c2c_he__set_mem_region(c2c_he, mem_region); =20 hists__inc_nr_samples(&c2c_hists->hists, he->filtered); =20 @@ -435,6 +451,7 @@ static int process_sample_event(const struct perf_tool = *tool __maybe_unused, c2c_he__set_cpu(c2c_he, sample); c2c_he__set_node(c2c_he, sample); c2c_he__set_evsel(c2c_he, evsel); + c2c_he__set_mem_region(c2c_he, mem_region); =20 hists__inc_nr_samples(&c2c_hists->hists, he->filtered); ret =3D hist_entry__append_callchain(he, sample); @@ -603,6 +620,29 @@ dcacheline_node_count(struct perf_hpp_fmt *fmt, struct= perf_hpp *hpp, return scnprintf(hpp->buf, hpp->size, "%*lu", width, c2c_he->paddr_cnt); } =20 +static int +dcacheline_node_mem_region(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, + struct hist_entry *he) +{ + int width =3D c2c_width(fmt, hpp, he->hists); + struct c2c_hist_entry *c2c_he; + unsigned int mem_region; + char buf[20]; + + c2c_he =3D container_of(he, struct c2c_hist_entry, he); + mem_region =3D c2c_he->mem_region; + + if (mem_region =3D=3D PERF_MEM_REGION_NA) + scnprintf(buf, sizeof(buf), "N/A"); + /* mem_region could only be >=3D PERF_MEM_REGION_MMIO */ + else if (mem_region =3D=3D PERF_MEM_REGION_MMIO) + scnprintf(buf, sizeof(buf), "MMIO"); + else + scnprintf(buf, sizeof(buf), "0x%x", mem_region - 0x8); + + return scnprintf(hpp->buf, hpp->size, "%*s", width, buf); +} + static int offset_entry(struct perf_hpp_fmt *fmt, struct perf_hpp *hpp, struct hist_entry *he) { @@ -1425,7 +1465,7 @@ cl_idx_empty_entry(struct perf_hpp_fmt *fmt, struct p= erf_hpp *hpp, } =20 static struct c2c_dimension dim_dcacheline =3D { - .header =3D HEADER_SPAN("--- Cacheline ----", "Address", 2), + .header =3D HEADER_SPAN("--- Cacheline ----", "Address", 3), .name =3D "dcacheline", .cmp =3D dcacheline_cmp, .entry =3D dcacheline_entry, @@ -1440,6 +1480,14 @@ static struct c2c_dimension dim_dcacheline_node =3D { .width =3D 4, }; =20 +static struct c2c_dimension dim_dcacheline_mem_region =3D { + .header =3D HEADER_LOW("Region"), + .name =3D "dcacheline_mem_region", + .cmp =3D empty_cmp, + .entry =3D dcacheline_node_mem_region, + .width =3D 6, +}; + static struct c2c_dimension dim_dcacheline_count =3D { .header =3D HEADER_LOW("PA cnt"), .name =3D "dcacheline_count", @@ -1871,6 +1919,7 @@ static struct c2c_dimension dim_dcacheline_num_empty = =3D { =20 static struct c2c_dimension *dimensions[] =3D { &dim_dcacheline, + &dim_dcacheline_mem_region, &dim_dcacheline_node, &dim_dcacheline_count, &dim_offset, @@ -2898,8 +2947,9 @@ static int ui_quirks(void) /* Fix the zero line for dcacheline column. */ buf =3D fill_line(chk_double_cl ? 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Memory region is found in the mem_region field of the memory information data source. This field was included with the introduction of support for the Off-module Response facility (OMR) [1] in Intel's Diamond Rapids and Nova Lake Architectures. An example of perf-script output with the new memory region field is shown below: random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2ec random 2411a68201042 |OP LOAD|LVL RAM hit|SNP Hit|TLB L1 or L2 hit|LCK N= o|BLK N/A|Region Mem-1 561de7f8910a random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 random 20e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK Data|Region N/A 7f32ae64a2d0 random 20e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK Data|Region N/A 7f32ae64a2d0 random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2ec random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 random 2411a68201042 |OP LOAD|LVL RAM hit|SNP Hit|TLB L1 or L2 hit|LCK N= o|BLK N/A|Region Mem-1 561de7f8910a random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2ec random 10e6a100042 |OP LOAD|LVL L0 hit|SNP None|TLB L1 or L2 hit|LCK Y= es|BLK N/A|Region N/A 7f32ae64a2d0 [1]: https://lore.kernel.org/all/20260114011750.350569-1-dapeng1.mi@linux.i= ntel.com/ Signed-off-by: Dapeng Mi Signed-off-by: Thomas Falcon --- Changes in v2: -- increased buffers passed to perf_script__meminfo_scnprintf() from 150 to 200 bytes to avoid silent truncation --- tools/perf/builtin-script.c | 8 +-- tools/perf/util/mem-events.c | 68 +++++++++++++++++++ .../scripting-engines/trace-event-python.c | 4 +- 3 files changed, 74 insertions(+), 6 deletions(-) diff --git a/tools/perf/builtin-script.c b/tools/perf/builtin-script.c index f91d8b1fbd01..ba8ec0093f4f 100644 --- a/tools/perf/builtin-script.c +++ b/tools/perf/builtin-script.c @@ -2081,8 +2081,8 @@ static int evlist__max_name_len(struct evlist *evlist) static int data_src__fprintf(u64 data_src, FILE *fp) { struct mem_info *mi =3D mem_info__new(); - char decode[100]; - char out[100]; + char decode[200]; + char out[200]; static int maxlen; int len; =20 @@ -2090,10 +2090,10 @@ static int data_src__fprintf(u64 data_src, FILE *fp) return -ENOMEM; =20 mem_info__data_src(mi)->val =3D data_src; - perf_script__meminfo_scnprintf(decode, 100, mi); + perf_script__meminfo_scnprintf(decode, 200, mi); mem_info__put(mi); =20 - len =3D scnprintf(out, 100, "%16" PRIx64 " %s", data_src, decode); + len =3D scnprintf(out, 200, "%16" PRIx64 " %s", data_src, decode); if (maxlen < len) maxlen =3D len; =20 diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c index 4fd48fd20055..ff08f1fee0e3 100644 --- a/tools/perf/util/mem-events.c +++ b/tools/perf/util/mem-events.c @@ -604,6 +604,72 @@ int perf_mem__blk_scnprintf(char *out, size_t sz, cons= t struct mem_info *mem_inf return l; } =20 +static int perf_mem__region_scnprintf(char *out, size_t sz, const struct m= em_info *mem_info) +{ + size_t l =3D 0; + u64 mem =3D PERF_MEM_REGION_NA; + + sz -=3D 1; /* -1 for null termination */ + out[0] =3D '\0'; + + if (mem_info) + mem =3D mem_info__const_data_src(mem_info)->mem_region; + + switch (mem) { + case PERF_MEM_REGION_NA: + case PERF_MEM_REGION_RSVD: + l +=3D scnprintf(out + l, sz - l, " N/A"); + break; + case PERF_MEM_REGION_L_SHARE: + l +=3D scnprintf(out + l, sz - l, " Local-shared-cache"); + break; + case PERF_MEM_REGION_L_NON_SHARE: + l +=3D scnprintf(out + l, sz - l, " Local-non-shared-cache"); + break; + case PERF_MEM_REGION_O_IO: + l +=3D scnprintf(out + l, sz - l, " Other-IO"); + break; + case PERF_MEM_REGION_O_SHARE: + l +=3D scnprintf(out + l, sz - l, " Other-shared-cache"); + break; + case PERF_MEM_REGION_O_NON_SHARE: + l +=3D scnprintf(out + l, sz - l, " Other-non-shared-cache"); + break; + case PERF_MEM_REGION_MMIO: + l +=3D scnprintf(out + l, sz - l, " MMIO"); + break; + case PERF_MEM_REGION_MEM0: + l +=3D scnprintf(out + l, sz - l, " Mem-0"); + break; + case PERF_MEM_REGION_MEM1: + l +=3D scnprintf(out + l, sz - l, " Mem-1"); + break; + case PERF_MEM_REGION_MEM2: + l +=3D scnprintf(out + l, sz - l, " Mem-2"); + break; + case PERF_MEM_REGION_MEM3: + l +=3D scnprintf(out + l, sz - l, " Mem-3"); + break; + case PERF_MEM_REGION_MEM4: + l +=3D scnprintf(out + l, sz - l, " Mem-4"); + break; + case PERF_MEM_REGION_MEM5: + l +=3D scnprintf(out + l, sz - l, " Mem-5"); + break; + case PERF_MEM_REGION_MEM6: + l +=3D scnprintf(out + l, sz - l, " Mem-6"); + break; + case PERF_MEM_REGION_MEM7: + l +=3D scnprintf(out + l, sz - l, " Mem-7"); + break; + default: + l +=3D scnprintf(out + l, sz - l, " N/A"); + break; + } + + return l; +} + int perf_script__meminfo_scnprintf(char *out, size_t sz, const struct mem_= info *mem_info) { int i =3D 0; @@ -620,6 +686,8 @@ int perf_script__meminfo_scnprintf(char *out, size_t sz= , const struct mem_info * i +=3D perf_mem__lck_scnprintf(out + i, sz - i, mem_info); i +=3D scnprintf(out + i, sz - i, "|BLK "); i +=3D perf_mem__blk_scnprintf(out + i, sz - i, mem_info); + i +=3D scnprintf(out + i, sz - i, "|Region "); + i +=3D perf_mem__region_scnprintf(out + i, sz - i, mem_info); =20 return i; } diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools= /perf/util/scripting-engines/trace-event-python.c index 8f832ae316ca..57ec259897e4 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -695,7 +695,7 @@ static void set_sample_datasrc_in_dict(PyObject *dict, struct perf_sample *sample) { struct mem_info *mi =3D mem_info__new(); - char decode[100]; + char decode[200]; =20 if (!mi) Py_FatalError("couldn't create mem-info"); @@ -704,7 +704,7 @@ static void set_sample_datasrc_in_dict(PyObject *dict, PyLong_FromUnsignedLongLong(sample->data_src)); =20 mem_info__data_src(mi)->val =3D sample->data_src; - perf_script__meminfo_scnprintf(decode, 100, mi); + perf_script__meminfo_scnprintf(decode, 200, mi); mem_info__put(mi); =20 pydict_set_item_string_decref(dict, "datasrc_decode", --=20 2.43.0 From nobody Sat Jul 25 20:48:39 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.16]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2561A257452; 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a="72130668" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="72130668" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:16 -0700 X-CSE-ConnectionGUID: +mhml6qOQvSnn/efFhRg/w== X-CSE-MsgGUID: 37fSUZ5xR0ml/jRD019QUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="260582154" Received: from rodrigoa-mobl1.amr.corp.intel.com (HELO tfalcon-desk.attlocal.net) ([10.124.220.48]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 17:44:14 -0700 From: Thomas Falcon To: linux-perf-users@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Dapeng Mi Subject: [PATCH v2 5/6] perf header: Support memory ranges Date: Mon, 13 Jul 2026 19:43:58 -0500 Message-ID: <20260714004359.179451-6-thomas.falcon@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260714004359.179451-1-thomas.falcon@intel.com> References: <20260714004359.179451-1-thomas.falcon@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Memory ranges were created to track different types of memory, such as persistent, high bandwidth, or CXL-attached, that may be present on a system for performance monitoring and resource control purposes. Memory range data are parsed from the ACPI MRRM table and exposed to userspace tools via sysfs [1]. Memory range data is read from: /sys/firmware/acpi/memory_ranges/rangeX With the following attributes: u64 base; u64 length; int node; u8 local_region_id; u8 remote_region_id; Read memory range data from sysfs if present and save it in the header of the perf data file under a new feature bit, HEADER_MEMORY_RANGES (35). Memory range data can be viewed with the --header or --header-only options of perf-report and perf-script. [1]: https://lore.kernel.org/lkml/20250505173819.419271-1-tony.luck@intel.c= om/ Assisted-by: Sashiko:gemini-3.1-pro-preview Signed-off-by: Thomas Falcon --- Changes in v2:=20 -- Added check for NULL return of sysfs__mountpoint() when parsing memory ranges in sysfs -- increased MAX_MEMORY_RANGES sanity check from 64 to 256 based on=20 ACPI MRRM table implementation in Linux kernel -- added comment for MAX_MEMORY_RANGES to clarify that it is a sanity check for malformed perf.data files -- removed a line of code was removed from util/env.h but was added back in v1 due to bad rebase --- .../Documentation/perf.data-file-format.txt | 13 ++ tools/perf/builtin-inject.c | 1 + tools/perf/util/env.c | 1 + tools/perf/util/env.h | 10 + tools/perf/util/header.c | 195 ++++++++++++++++++ tools/perf/util/header.h | 1 + 6 files changed, 221 insertions(+) diff --git a/tools/perf/Documentation/perf.data-file-format.txt b/tools/per= f/Documentation/perf.data-file-format.txt index b90cba9168f8..1f8e7d8e9ae2 100644 --- a/tools/perf/Documentation/perf.data-file-format.txt +++ b/tools/perf/Documentation/perf.data-file-format.txt @@ -478,6 +478,19 @@ The size of the cacheline in bytes. Format: =20 unsigned int cln_size; =20 + HEADER_MEMORY_RANGES =3D 35, + +List of memory ranges. The format of the data is as below. + +u32 nr_memory_ranges; +struct memory_range { + u64 base; + u64 length; + int node; + u8 local_region_id; + u8 remote_region_id; +}; [nr_memory_ranges] + other bits are reserved and should be ignored for now HEADER_FEAT_BITS =3D 256, =20 diff --git a/tools/perf/builtin-inject.c b/tools/perf/builtin-inject.c index 70bbfad5653e..169617a884d3 100644 --- a/tools/perf/builtin-inject.c +++ b/tools/perf/builtin-inject.c @@ -2306,6 +2306,7 @@ static bool keep_feat(struct perf_inject *inject, int= feat) case HEADER_PMU_CAPS: case HEADER_CPU_DOMAIN_INFO: case HEADER_CLN_SIZE: + case HEADER_MEMORY_RANGES: return true; /* Information that can be updated */ case HEADER_BUILD_ID: diff --git a/tools/perf/util/env.c b/tools/perf/util/env.c index c0e2b9d5f0b2..50993b0dedc5 100644 --- a/tools/perf/util/env.c +++ b/tools/perf/util/env.c @@ -297,6 +297,7 @@ void perf_env__exit(struct perf_env *env) zfree(&env->pmu_caps[i].pmu_name); } zfree(&env->pmu_caps); + zfree(&env->memory_ranges); free_cpu_domain_info(env->cpu_domain, env->schedstat_version, env->nr_cpu= s_avail); } =20 diff --git a/tools/perf/util/env.h b/tools/perf/util/env.h index 7acca39b42ff..23d35425efe3 100644 --- a/tools/perf/util/env.h +++ b/tools/perf/util/env.h @@ -68,6 +68,14 @@ struct cpu_domain_map { struct domain_info **domains; }; =20 +struct memory_range { + u64 base; + u64 length; + int node; + u8 local_region_id; + u8 remote_region_id; +}; + struct perf_env { char *hostname; char *os_release; @@ -100,6 +108,7 @@ struct perf_env { int nr_cpu_pmu_caps; int nr_hybrid_nodes; int nr_pmus_with_caps; + int nr_memory_ranges; char *cmdline; const char **cmdline_argv; char *sibling_cores; @@ -122,6 +131,7 @@ struct perf_env { unsigned long long memory_bsize; struct hybrid_node *hybrid_nodes; struct pmu_caps *pmu_caps; + struct memory_range *memory_ranges; #ifdef HAVE_LIBBPF_SUPPORT /* * bpf_info_lock protects bpf rbtrees. This is needed because the diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index e90e541f546b..0669898362d6 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -92,6 +92,7 @@ #define MAX_PMU_CAPS 512 #define MAX_PMU_MAPPINGS 4096 #define MAX_SCHED_DOMAINS 64 +#define MAX_MEMORY_RANGES 256 =20 /* * magic2 =3D "PERFILE2" @@ -1891,6 +1892,130 @@ static int write_cpu_domain_info(struct feat_fd *ff, return ret; } =20 +static int memory_range__read(struct memory_range *range, int idx) +{ + char path[PATH_MAX], file[PATH_MAX]; + struct stat st; + int tmp; + + scnprintf(path, PATH_MAX, "firmware/acpi/memory_ranges/range%d", idx); + scnprintf(file, PATH_MAX, "%s/%s", sysfs__mountpoint(), path); + if (stat(file, &st)) + return -1; + + scnprintf(file, PATH_MAX, "%s/base", path); + if (sysfs__read_xll(file, (unsigned long long *) &range->base)) + return -1; + + scnprintf(file, PATH_MAX, "%s/length", path); + if (sysfs__read_xll(file, (unsigned long long *) &range->length)) + return -1; + + scnprintf(file, PATH_MAX, "%s/node", path); + if (sysfs__read_int(file, (int *) &range->node)) + return -1; + + scnprintf(file, PATH_MAX, "%s/local_region_id", path); + if (sysfs__read_int(file, &tmp)) + return -1; + + if (tmp < 0 || tmp > 255) + return -1; + range->local_region_id =3D tmp; + + scnprintf(file, PATH_MAX, "%s/remote_region_id", path); + if (sysfs__read_int(file, &tmp)) + return -1; + + if (tmp < 0 || tmp > 255) + return -1; + range->remote_region_id =3D tmp; + + return 0; +} + +static int memory_range__parse(struct memory_range **ranges) +{ + const char *sysfs =3D sysfs__mountpoint(); + int i, err, nr_memory_ranges =3D 0; + char path[PATH_MAX]; + struct stat st; + + if (!sysfs) + return 0; + + scnprintf(path, PATH_MAX, "%s/firmware/acpi/memory_ranges", sysfs); + if (stat(path, &st)) + return 0; + + while (1) { + scnprintf(path, PATH_MAX, "%s/firmware/acpi/memory_ranges/range%d", sysf= s, nr_memory_ranges); + if (stat(path, &st)) + break; + + nr_memory_ranges++; + } + + if (nr_memory_ranges =3D=3D 0) + return 0; + + *ranges =3D zalloc(nr_memory_ranges * sizeof(struct memory_range)); + if (!(*ranges)) + return -ENOMEM; + + for (i =3D 0; i < nr_memory_ranges; i++) { + struct memory_range range; + + err =3D memory_range__read(&range, i); + if (err < 0) + goto out_error; + + (*ranges)[i] =3D range; + } + + return nr_memory_ranges; + +out_error: + zfree(ranges); + return -1; +} + +static int write_memory_ranges(struct feat_fd *ff, + struct evlist *evlist __maybe_unused) +{ + struct memory_range *ranges =3D NULL; + int nr_memory_ranges =3D 0, ret; + + nr_memory_ranges =3D memory_range__parse(&ranges); + if (nr_memory_ranges < 0) + return nr_memory_ranges; + + ret =3D do_write(ff, &nr_memory_ranges, sizeof(nr_memory_ranges)); + if (ret < 0) + goto out; + + for (int i =3D 0; i < nr_memory_ranges; i++) { + ret =3D do_write(ff, &ranges[i].base, sizeof(u64)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].length, sizeof(u64)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].node, sizeof(u32)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].local_region_id, sizeof(u8)); + if (ret < 0) + goto out; + ret =3D do_write(ff, &ranges[i].remote_region_id, sizeof(u8)); + if (ret < 0) + goto out; + } +out: + zfree(&ranges); + return ret; +} + static void print_hostname(struct feat_fd *ff, FILE *fp) { fprintf(fp, "# hostname : %s\n", ff->ph->env.hostname); @@ -2628,6 +2753,23 @@ static void print_cpu_domain_info(struct feat_fd *ff= , FILE *fp) } } =20 +static void print_memory_ranges(struct feat_fd *ff, FILE *fp) +{ + struct memory_range *ranges =3D ff->ph->env.memory_ranges; + int nr_memory_ranges =3D ff->ph->env.nr_memory_ranges; + int i; + + fprintf(fp, "# memory ranges (nr %d):\n", nr_memory_ranges); + + for (i =3D 0; i < nr_memory_ranges; i++) { + fprintf(fp, "# range%u: 0x%16" PRIx64 "-0x%16" PRIx64, + i, ranges[i].base, ranges[i].base + ranges[i].length - 1); + fprintf(fp, ", node =3D %d, local_region_id =3D %d, remote_region_id =3D= %d\n", + ranges[i].node, ranges[i].local_region_id, + ranges[i].remote_region_id); + } +} + static int __event_process_build_id(struct perf_record_header_build_id *be= v, char *filename, struct perf_session *session) @@ -4201,6 +4343,58 @@ static int process_cpu_domain_info(struct feat_fd *f= f, void *data __maybe_unused return ret; } =20 +static int process_memory_ranges(struct feat_fd *ff, void *data __maybe_un= used) +{ + struct perf_env *env =3D &ff->ph->env; + struct memory_range *ranges, *r; + u32 nr_memory_ranges, i; + + if (do_read_u32(ff, &nr_memory_ranges)) + return -1; + + if (!nr_memory_ranges) { + pr_debug("memory ranges not available\n"); + return 0; + } + + /* According to version 1.1 of the ACPI MRRM table, the maximum + * number of memory regions can be at most 255. Do a sanity check + * here to guard against a malformed perf.data file. + */ + if (nr_memory_ranges >=3D MAX_MEMORY_RANGES) { + pr_err("Invalid memory_ranges: nr_memory_ranges (%u) > %u\n", + nr_memory_ranges, MAX_MEMORY_RANGES); + return -1; + } + + ranges =3D zalloc(nr_memory_ranges * sizeof(*ranges)); + if (!ranges) + return -1; + + for (i =3D 0; i < nr_memory_ranges; i++) { + r =3D &ranges[i]; + + if (do_read_u64(ff, &r->base)) + goto error; + if (do_read_u64(ff, &r->length)) + goto error; + if (do_read_u32(ff, (u32 *) &r->node)) + goto error; + if (__do_read(ff, &r->local_region_id, sizeof(u8))) + goto error; + if (__do_read(ff, &r->remote_region_id, sizeof(u8))) + goto error; + } + + env->memory_ranges =3D ranges; + env->nr_memory_ranges =3D nr_memory_ranges; + + return 0; +error: + zfree(&ranges); + return -1; +} + #define FEAT_OPR(n, func, __full_only) \ [HEADER_##n] =3D { \ .name =3D __stringify(n), \ @@ -4265,6 +4459,7 @@ const struct perf_header_feature_ops feat_ops[HEADER_= LAST_FEATURE] =3D { FEAT_OPR(CPU_DOMAIN_INFO, cpu_domain_info, true), FEAT_OPR(E_MACHINE, e_machine, false), FEAT_OPR(CLN_SIZE, cln_size, false), + FEAT_OPR(MEMORY_RANGES, memory_ranges, false), }; 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charset="utf-8" Print memory range data in perf-c2c subcommand. Only available in stdio mode currently. If memory ranges are not supported or present, print nothing. Assisted-by: Sashiko:gemini-3.1-pro-preview Signed-off-by: Thomas Falcon --- tools/perf/builtin-c2c.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c index cba2e9f21ae7..68348a93bd33 100644 --- a/tools/perf/builtin-c2c.c +++ b/tools/perf/builtin-c2c.c @@ -2634,6 +2634,34 @@ static void print_c2c_info(FILE *out, struct perf_se= ssion *session) fprintf(out, " Cacheline data grouping : %s\n", c2c.cl_sort); } =20 + +static void print_memory_ranges_info(FILE *out, struct perf_session *sessi= on) +{ + struct perf_env *env =3D perf_session__env(session); + int nr_ranges =3D 0; + + if (!perf_header__has_feat(&session->header, HEADER_MEMORY_RANGES)) + return; + nr_ranges =3D env->nr_memory_ranges; + if (nr_ranges =3D=3D 0) { + pr_debug("No memory ranges found, skipping\n"); + return; + } + + fprintf(out, "\n"); + fprintf(out, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"); + fprintf(out, " Memory Ranges \n"); + fprintf(out, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"); + + for (int i =3D 0; i < nr_ranges; i++) { + struct memory_range *r =3D &env->memory_ranges[i]; + + fprintf(out, "Range %d: [0x%016" PRIx64 "-0x%016" PRIx64 "] Node %d, loc= al region id %u, remote region id %u\n", + i, r->base, r->base + r->length - 1, r->node, + r->local_region_id, r->remote_region_id); + } +} + static void perf_c2c__hists_fprintf(FILE *out, struct perf_session *sessio= n) { setup_pager(); @@ -2647,6 +2675,8 @@ static void perf_c2c__hists_fprintf(FILE *out, struct= perf_session *session) if (c2c.stats_only) return; =20 + print_memory_ranges_info(out, session); + fprintf(out, "\n"); fprintf(out, "=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D\n"); fprintf(out, " Shared Data Cache Line Table \n"); --=20 2.43.0