From nobody Sat Jul 25 20:49:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F30B935CB87; Tue, 14 Jul 2026 01:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783991484; cv=none; b=MwfnXA8l9ZFrFygzF94bLmiZ33glI/ZMJUezMzXa0DnSiz0O3MgMxQROO33iygGt3th8PAX5573WR7Q0i7SG1eSaba6shSVTfs23W1Z1eobgEMswgTCatrp8+IxYU2EE6vk6l2Gd6fBSV7eGlHX5+q5NzRdFJxusZP7/n8JjhUs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783991484; c=relaxed/simple; bh=664nbVN/z/Nh13dTvS9ukzYiJiV3KLMrcH0uSAw82eY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gN62r8o0vMg8M2nfTuFFRFjgdcYuJlhHCGx+QYwbKO+4Zlzbkp37FNXpxJ1y5z2pjwZcZoQgpIJeVF4jWLeQkyEEatuJKeVPia5hQMxCZi+RbvivvGW/kwdaFO0my5d51HolHX0h2uSNNwUp/exWS7vl36k/2At17/I5Y+e9tqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=m7kJ4Sxe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="m7kJ4Sxe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 87627C2BCF5; Tue, 14 Jul 2026 01:11:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1783991483; bh=664nbVN/z/Nh13dTvS9ukzYiJiV3KLMrcH0uSAw82eY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=m7kJ4SxeIuX+wp43CN0G9xZPzEGyuIX1ip8ssV3BWODKZ8zdrzmh8uih404CMCGy3 M1vfSd1NCf1nGWMcLBkOLrHZ3EV7qjhH/0hmPYNcUlmaOAS73vDujNIN+qTjMG0uB+ JkSqcdNgMxrncXT8owkWXtmR5exkxyzTmYJgwgvXvBfFs9TOOTI045aQLau7n4YtNV 4clvP9bFK+/JGeAcVw7KEvLXmSpooKlwOi+V7G2Cf1XPLoLz90HD1BuXIoWecmrRTh oob/2vy4kyy94A1WiedN/5QV7/YCGT1bucwuadOneJ/hL3OmqVd1bR0eXIKMtDcfqO 543o6ZxWz9DHQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6926EC43458; Tue, 14 Jul 2026 01:11:23 +0000 (UTC) From: Jia Wang via B4 Relay Date: Tue, 14 Jul 2026 09:11:02 +0800 Subject: [PATCH v3 1/3] dt-bindings: pci: ultrarisc: add required DP1000 PCIe clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-ultrarisc-pci-clk-v3-1-e72723fc0ef1@ultrarisc.com> References: <20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com> In-Reply-To: <20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com> To: Xincheng Zhang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jia Wang , Krzysztof Kozlowski , Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783991481; l=1883; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=MadaMzsEQt3m33Yn04ygfcyKkX6JurLuStxQ8qHRs6U=; b=XxdL7yZX//LcNbb9nViGu1d8at7DF0oB5I7hH7dWtIgnglHcf3tPIstyNgZHZwq6BcXHZLFfY 6okUD7/8jK4D+4MEj0tbZjWhtA/36FFQ9xLBwd2Oiv42WrsY6dqqMix X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Require the DP1000 PCIe controller nodes to provide clocks and clock-names, using the standard DesignWare clock names "core", "dbi", and "aux". Fixes: d9ff07f45955 ("dt-bindings: PCI: Add UltraRISC DP1000 PCIe controlle= r") Signed-off-by: Jia Wang Acked-by: Conor Dooley --- .../devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.ya= ml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml index 512b935bf5d1..d9d1488e915a 100644 --- a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml @@ -43,6 +43,18 @@ properties: - description: Legacy INTC interrupt - description: Legacy INTD interrupt =20 + clocks: + items: + - description: PCIe core clock + - description: Data Bus Interface (DBI) clock + - description: Auxiliary clock + + clock-names: + items: + - const: core + - const: dbi + - const: aux + interrupt-names: items: - const: msi @@ -55,6 +67,8 @@ required: - compatible - reg - reg-names + - clocks + - clock-names - interrupts - interrupt-names =20 @@ -71,6 +85,8 @@ examples: reg =3D <0x0 0x21000000 0x0 0x01000000>, <0x0 0x4fff0000 0x0 0x00010000>; reg-names =3D "dbi", "config"; + clocks =3D <&clkc 9>, <&clkc 7>, <&clkc 10>; + clock-names =3D "core", "dbi", "aux"; ranges =3D <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x0040000= 0>, <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x0000000= 0>; --=20 2.34.1 From nobody Sat Jul 25 20:49:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F1FDF35B633; Tue, 14 Jul 2026 01:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783991484; cv=none; b=S91YkGp8XKl1N9u2ppRqH+41ZRIe0mOpK4Nzp7PnvlzOTdreVjtIXgkUB9oYhv1i90AuhCwDIkJY6kDzs7EOWiLakwPMszW5gdYnKGaCZSOmQTm7wKzYfJqh9Suc9lWLjjAYn8rXzVFZNot108y7dlE6bu+dWM5/SYy9USj6KBo= ARC-Message-Signature: i=1; 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b=FIV+jg6f6m1E51cK74qvNunkQ3+D0Sldw3rPDtPnEmnQVUP6LzVAtBOHKjpEmkqE/ Nwz3VAe6VKn77n3/7da2GF5BBbGTVetYuivFb+Xv/8XBHLA6WJsnmTmGCyraBMylHu GNadBPho3sw6MagDnUdm72UlTMwrKMUaRijljvcXeUReUN/LhAN0aFTZvVuLv3EEpF f0Z5XzS7EMXMKq+YBgIeRcqDqcdsuRTyxRr9taT0kXg1mPDQIYyngbUJSJ1iBaLzHe +JH38qPfC/fj7d5zPG0UrjuMVkn6Jv6ylTebXNKCCfHFJi+qJgeUH1Ccynnwom8ar3 KHW2gAedS4EBQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76900C44508; Tue, 14 Jul 2026 01:11:23 +0000 (UTC) From: Jia Wang via B4 Relay Date: Tue, 14 Jul 2026 09:11:03 +0800 Subject: [PATCH v3 2/3] PCI: ultrarisc: get and enable DP1000 PCIe clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-ultrarisc-pci-clk-v3-2-e72723fc0ef1@ultrarisc.com> References: <20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com> In-Reply-To: <20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com> To: Xincheng Zhang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jia Wang , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783991481; l=4440; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=m+XMwYjThEBR9HkyTKk+8n3D+poPz9TbOd8MBs90krs=; b=uPyJ9G0ozRw1SRhj2FX3YezvpT615dJUP9ltztUsjj2sacDF81K3wmwfajd73iquM7V8CFOVM knKbDPq0rKdAjMsRhUT5TXGo0C2VWjzMaHx5ZMVG3yGOu69E7ABWxCJ X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang Add the required core, dbi, and aux clocks for the DP1000 PCIe controller and enable them before initializing the DesignWare host. Also manage the clocks across system suspend and resume. Fixes: 5fc35740c3b3 ("PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Comple= x driver") Signed-off-by: Jia Wang --- drivers/pci/controller/dwc/pcie-ultrarisc.c | 102 ++++++++++++++++++++++++= ++-- 1 file changed, 95 insertions(+), 7 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c index 6ee661ceff67..72ba5840b62d 100644 --- a/drivers/pci/controller/dwc/pcie-ultrarisc.c +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -5,6 +5,7 @@ * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. */ =20 +#include #include #include #include @@ -23,6 +24,12 @@ =20 #define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 =20 +struct ultrarisc_pcie { + struct dw_pcie pci; + struct clk_bulk_data clks[3]; + bool clks_enabled; +}; + static struct pci_ops ultrarisc_pci_ops =3D { .map_bus =3D dw_pcie_own_conf_map_bus, .read =3D pci_generic_config_read32, @@ -98,17 +105,66 @@ static const struct dw_pcie_ops dw_pcie_ops =3D { .start_link =3D ultrarisc_pcie_start_link, }; =20 +static int ultrarisc_pcie_enable_clks(struct ultrarisc_pcie *ultra) +{ + int ret; + + if (ultra->clks_enabled) + return 0; + + ret =3D clk_bulk_prepare_enable(ARRAY_SIZE(ultra->clks), ultra->clks); + if (ret) + return ret; + + ultra->clks_enabled =3D true; + + return 0; +} + +static void ultrarisc_pcie_disable_clks(void *data) +{ + struct ultrarisc_pcie *ultra =3D data; + + if (!ultra->clks_enabled) + return; + + clk_bulk_disable_unprepare(ARRAY_SIZE(ultra->clks), ultra->clks); + ultra->clks_enabled =3D false; +} + +static int ultrarisc_pcie_init_clks(struct ultrarisc_pcie *ultra) +{ + struct device *dev =3D ultra->pci.dev; + int ret; + + ultra->clks[0].id =3D "core"; + ultra->clks[1].id =3D "dbi"; + ultra->clks[2].id =3D "aux"; + + ret =3D devm_clk_bulk_get(dev, ARRAY_SIZE(ultra->clks), ultra->clks); + if (ret) + return dev_err_probe(dev, ret, "Failed to get clocks\n"); + + ret =3D ultrarisc_pcie_enable_clks(ultra); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable clocks\n"); + + return devm_add_action_or_reset(dev, ultrarisc_pcie_disable_clks, ultra); +} + static int ultrarisc_pcie_probe(struct platform_device *pdev) { + struct ultrarisc_pcie *ultra; struct device *dev =3D &pdev->dev; struct dw_pcie_rp *pp; struct dw_pcie *pci; int ret; =20 - pci =3D devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); - if (!pci) + ultra =3D devm_kzalloc(dev, sizeof(*ultra), GFP_KERNEL); + if (!ultra) return -ENOMEM; =20 + pci =3D &ultra->pci; pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; =20 @@ -117,7 +173,11 @@ static int ultrarisc_pcie_probe(struct platform_device= *pdev) =20 pp =3D &pci->pp; =20 - platform_set_drvdata(pdev, pci); + platform_set_drvdata(pdev, ultra); + + ret =3D ultrarisc_pcie_init_clks(ultra); + if (ret) + return ret; =20 pp->num_vectors =3D MAX_MSI_IRQS; /* No L2/L3 Ready indication is available on this platform */ @@ -135,16 +195,44 @@ static int ultrarisc_pcie_probe(struct platform_devic= e *pdev) =20 static int ultrarisc_pcie_suspend_noirq(struct device *dev) { - struct dw_pcie *pci =3D dev_get_drvdata(dev); + struct ultrarisc_pcie *ultra =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &ultra->pci; + int ret; + + if (pci->suspended) { + ultrarisc_pcie_disable_clks(ultra); + return 0; + } + + ret =3D dw_pcie_suspend_noirq(pci); + if (ret) + return ret; =20 - return dw_pcie_suspend_noirq(pci); + if (pci->suspended) + ultrarisc_pcie_disable_clks(ultra); + + return 0; } =20 static int ultrarisc_pcie_resume_noirq(struct device *dev) { - struct dw_pcie *pci =3D dev_get_drvdata(dev); + struct ultrarisc_pcie *ultra =3D dev_get_drvdata(dev); + struct dw_pcie *pci =3D &ultra->pci; + int ret; + + if (pci->suspended) { + ret =3D ultrarisc_pcie_enable_clks(ultra); + if (ret) + return ret; =20 - return dw_pcie_resume_noirq(pci); + ret =3D dw_pcie_resume_noirq(pci); + if (ret) { + ultrarisc_pcie_disable_clks(ultra); + return ret; + } + } + + return 0; } =20 static const struct dev_pm_ops ultrarisc_pcie_pm_ops =3D { --=20 2.34.1 From nobody Sat Jul 25 20:49:16 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FC263033DF; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-ultrarisc-pci-clk-v3-3-e72723fc0ef1@ultrarisc.com> References: <20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com> In-Reply-To: <20260714-ultrarisc-pci-clk-v3-0-e72723fc0ef1@ultrarisc.com> To: Xincheng Zhang , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Jia Wang , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783991482; l=1888; i=wangjia@ultrarisc.com; s=20260515; h=from:subject:message-id; bh=XcTZmVoSZFS2n0hsc4SvpU5AR+j0HF5sHlxgI3DxZTg=; b=lVeYRfT+j1fweGZ2YwkwrOX/iivL/LBom7hfF+EFD1hMgVtG3nOi2X5aj2adhEPBAw53sdwu8 Qg31WSd9KxkBIFZWImmIbCltSqkCAIziZGU4ry6MavZ/eoInRn8bV75 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=wGVm18siRScehKOkOz0WKxgxDy7IezHEszhnN4/TUCY= X-Endpoint-Received: by B4 Relay for wangjia@ultrarisc.com/20260515 with auth_id=779 X-Original-From: Jia Wang Reply-To: wangjia@ultrarisc.com From: Jia Wang CONFIG_PCIE_ULTRARISC is a tristate option, so the driver can be selected as a module when COMPILE_TEST or platform configuration allows it. Using builtin_platform_driver() leaves the module build without the module init/exit plumbing and causes modpost failures for the generated .ko. Use module_platform_driver() so the driver works for both module and built-in builds while keeping the existing tristate Kconfig entry. Add a remove callback and call dw_pcie_host_deinit() during removal so the root bus is torn down before devres releases the controller data. Fixes: 5fc35740c3b3 ("PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Comple= x driver") Signed-off-by: Jia Wang --- drivers/pci/controller/dwc/pcie-ultrarisc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c index 72ba5840b62d..9bee522a20e9 100644 --- a/drivers/pci/controller/dwc/pcie-ultrarisc.c +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -193,6 +193,13 @@ static int ultrarisc_pcie_probe(struct platform_device= *pdev) return 0; } =20 +static void ultrarisc_pcie_remove(struct platform_device *pdev) +{ + struct ultrarisc_pcie *ultra =3D platform_get_drvdata(pdev); + + dw_pcie_host_deinit(&ultra->pci.pp); +} + static int ultrarisc_pcie_suspend_noirq(struct device *dev) { struct ultrarisc_pcie *ultra =3D dev_get_drvdata(dev); @@ -256,8 +263,9 @@ static struct platform_driver ultrarisc_pcie_driver =3D= { .pm =3D &ultrarisc_pcie_pm_ops, }, .probe =3D ultrarisc_pcie_probe, + .remove =3D ultrarisc_pcie_remove, }; -builtin_platform_driver(ultrarisc_pcie_driver); +module_platform_driver(ultrarisc_pcie_driver); =20 MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); MODULE_LICENSE("GPL"); --=20 2.34.1