From nobody Sat Jul 25 20:08:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8839530AAB8; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; cv=none; b=NA3wqKNw2AgXdFWjwQWGWiT4++lqLIPefdeeW7Fe7qREaQeS/CaczJswIGFwJ0wfwRBm95r+BevYLzx+V4/Zj9q1nMXM/mg8RaWNYZC6RfsgpdLP2tQ0FmciKgvECIc4vSwGgR/6ZXE8SRMb/rDI8vYfzV09vqTQeBlES5FWViU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; c=relaxed/simple; bh=cBuG9qIm4T9+ewT4unUQMAxwPyLKUDr1oTf2cMuk8gg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Z2mbIgP3wczCQ7bbcpiVISgqKpRd5brqmVBmpTG6+Cw/l36QnNfzjjrhBHTDwdlkDdz4eeykA0GOf/KhTlnCYtskw+b3hbRMeJm7vdi0VD3i3v+bfZPYIDhXw4hm/MVG4KK5nJ7geYv4NnIUBifyjlljpUnRWjK0xgPBmpEbmtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=hXEPa2uz; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="hXEPa2uz" Received: by smtp.kernel.org (Postfix) with ESMTPS id 415FDC4AF0C; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784011015; bh=cBuG9qIm4T9+ewT4unUQMAxwPyLKUDr1oTf2cMuk8gg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=hXEPa2uzVzFD/KTgy16pH7ZzhUYxih6jhhwix2Qqqey2lgH6duX7xA+GGGnZvGb+0 mG+X68GsX87XvhQhzT+cR0fTJJhbl+ln+1097RsB5cxO0K8V6JjCHHHnZtL83/5A2J PcQYpldV2bLm9nfueyebTsbk1pGeeHZZ04ysGSXxYW4cyTnzrJYE9MIt6LH2bu1Am+ g0wnGUn61HCCLNW0U+4SyT3lusIbxcigN0A0pRzsbfyDK3HNCuQ8GQzs91AVhp2uP7 4vMV4ic23/couB/GVQgpBbF+pFCAuTY+PComyao2OCaa6jSu05wrnljiXV6BOMshe+ EZgwKPRJwRF7Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DAB7C44501; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Tue, 14 Jul 2026 02:36:39 -0400 Subject: [PATCH 1/6] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add SM8475 QMP PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-sm8475-bup-v1-1-b2871be2b4ec@proton.me> References: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> In-Reply-To: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784011013; l=1401; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=L4xMCLonX6m0jP1wAaA1TnmKHswCpMfIQy+ivLlYcQI=; b=u4PImQ3F7GkRpTteaHa6Wzd/Dj9d2hWYFwbCyrVusVmJ84ESsI2HspoHwZJk9l5TfxsT6hmQX JfhvrIZYNQlAwT74SVFKZ2YP4xxmulB6h7kKZ001imsCZuVCt1bTtK2 X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia SM8450 init sequence for this PHY varies significantly and can't be reused in SM8475. Add proper init sequence and bindings for the PHY found in this SoC. Signed-off-by: Esteban Urrutia --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 = ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.= yaml index 108cf9dc86ea..8850d5ebac03 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -43,6 +43,7 @@ properties: - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen4x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy @@ -175,6 +176,7 @@ allOf: - qcom,sm8350-qmp-gen3x2-pcie-phy - qcom,sm8450-qmp-gen3x1-pcie-phy - qcom,sm8450-qmp-gen3x2-pcie-phy + - qcom,sm8475-qmp-gen3x1-pcie-phy - qcom,sm8550-qmp-gen3x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen3x2-pcie-phy --=20 2.55.0 From nobody Sat Jul 25 20:08:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8842B3254AE; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; cv=none; b=Yjng81En2NmZRmMCnVQ5W4xUpo2LNRdXg21FoHnI/g5m17a+DmIJ+6mZETqbAiKglKan7VIGGXlC4xoprxBO2wJmk5MloRqEjqTargnWRdfrlnTTmJuu6SLDGfTmMtRp+hwiiRtgrf5i2ILuV0ylxcdqu7+mbzeFtdt1IjAF4Cg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; c=relaxed/simple; bh=M5rHWWsk2ebtN6p/G0BoVZWqMTBYIdjkLJ07rqFgImI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FmnWJiZlC9DVVaraqCFFFgNYbopGgHdWTglO9MRcT4ItT4BHWf4DcfbHHtC52jp58NUht/cGE+R/OpJ5awOKckOFlb4eT4sdejlTvQMierTw3399JF1cd2BFgdq73jqsXRDREoIfCw1bNTZO56KyY6jxdm9w1mmmS6uWzf6KiCo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H8uNhDPf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H8uNhDPf" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4F847C2BCF7; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784011015; bh=M5rHWWsk2ebtN6p/G0BoVZWqMTBYIdjkLJ07rqFgImI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=H8uNhDPfLjxRYjAaHl8ppsA29U3sRdpmwYKj8aql5ZMFZHqTYTcm/AIFA7mhDmLd2 RCqD84iW6EiV/cayqN95ZBqzAREdsNdRsVL8Znj6FbOHD8jnnTWfsUMxv9LyYxCS+1 3j55NJKlXLWjASk8U0fkwGRezvgdceNsaKXBuV52oDLFHLnjFSCBIhuE/h2bONDbFg Z//dGMCrHBtym19gvdBZFtCXGD8+PodFktvuEHoATjfz8hyyBTHNIkMvNdeR/aDmks 79Ci40kNLuPwEAr4Viu/yGyBdOhM1f3xrpfr8yFtcqZi3mYmru33Ml+YR3igiljnfM I4V5uwsAKSKSw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 339D0C44507; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Tue, 14 Jul 2026 02:36:40 -0400 Subject: [PATCH 2/6] phy: qcom: qmp-pcie: Add pcs_lane1 offset to V5 offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-sm8475-bup-v1-2-b2871be2b4ec@proton.me> References: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> In-Reply-To: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784011013; l=843; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=F5UdqLwC15G2UvXxjasu1py1N0XW4szUwdIBq6LGK4E=; b=ukvHRLACirQxzxbOSPAUlwEJxKSXdNkzqU6q+GVamPSQ3lpZuOe5DzquAmqEfaNvWl8yf1oIP sFQ68JpJZt7AtJNyt3vGciWQpBB+WnTuLnfQR8W+8tuIRbWVlrZMOjV X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia Some SoCs such as SM8475 write data to registers using this offset, specifically SW_CTRL2 and MX_CTRL2. Add pcs_lane1 offset to V5 offsets using the proper offset, otherwise these registers would be part of RX and would not be defined. Signed-off-by: Esteban Urrutia --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index d3effad7a074..3618812e84d5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3554,6 +3554,7 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets= _v5 =3D { .pcs_misc =3D 0x0600, .tx =3D 0x0e00, .rx =3D 0x1000, + .pcs_lane1 =3D 0x1400, .tx2 =3D 0x1600, .rx2 =3D 0x1800, }; --=20 2.55.0 From nobody Sat Jul 25 20:08:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9687934B1B0; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; cv=none; b=GndL+O1/X4nM1HZwu8wGy71la0U5Tx2wNF7v22y+XSglLwtmFlIlBJAW2xZDSlEvKl1FXDYbLhHGS4yTQdgL2urUqXnO8cqBP+QfOpZ3HoV31QLjbSHIXO1kS+rz4eB7GiJ82ckV/pU5+G6SWLLRK47ZpJKHiMM5Uv5bTB5G6q4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; c=relaxed/simple; bh=y0CnPP7mxupqVofK7JjimHQy7LWbh6NFh1EFHs8+aw4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BxtTrmiTBlhvgL747iIaf88t1KoFJ44nQguCZIU7UrkNGeW5feqekaVWn+PGD5dWF5y05hwGNtgB01GdUrBdTlhr0QY6SINo8fciaWM9Me4fG0Z1jH/kwN9g10T3nLblpsEPKGrCpD0G3SurmxCMJddXzIz3+/Cty/7pbhVHgg0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MrpzX81L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MrpzX81L" Received: by smtp.kernel.org (Postfix) with ESMTPS id 5D44AC2BCFA; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784011015; bh=y0CnPP7mxupqVofK7JjimHQy7LWbh6NFh1EFHs8+aw4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=MrpzX81LFNAl7E35iuSh9h+Xy/r3JBuo38GDJP6QrtoAkrmivCDqnBArWHlMlaowy Wmiodhvco8dgiZ/p5t/PCzLmnfz0GKtVaS1XUl1XHRovZfJ43kjKngaRozg/MpsCY4 jSSZIv1gh9CPTVbGV5xcX0KKDmgy4OdMnC6XpWLyN3Bb3Zx1c1NphgNU48vj0LEN65 3Y5LaVpJBxPqYTxh/day14hPc4BnXBSp4axgeIdwEBfedkYU6pq01Z3S40uY2Km4tY l9Beb7237IifqQUmh8xp0EOF4vbQI3dYe5sZkWWMrdk9xqim6zuNzigG2V3aQ+74qM +wM3NcaT9xpdA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4534EC44508; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Tue, 14 Jul 2026 02:36:41 -0400 Subject: [PATCH 3/6] phy: qcom: qmp-pcie: Add support for SM8475 Gen3x1 PCIe0 port Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-sm8475-bup-v1-3-b2871be2b4ec@proton.me> References: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> In-Reply-To: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784011013; l=7014; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=BoefUjBF0F79KKjrYCZRV0KO0xB2WEhrR2N6MJvYzTU=; b=w8cox2YZKV7eN+d6x+URcJmZImtyqOZVNgu4B784OroA7DGY3We2Q2ZVIzGuDuavb+/mQ/+Dg IVYFC/KhsU8Dc1G4vkQP8tnhgNjMO3KaltbA80A8KyWUHl5H5C8aIOx X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia This gets the port working. Tested with WCN6856 WLAN capabilities. Serdes, RX and PCS Misc tables had to be added, while TX and PCS tables were reused from SM8550, and PCS Lane1 was reused from SAR2130P. Despite this, all offsets and values match. Signed-off-by: Esteban Urrutia --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 108 +++++++++++++++++++++++++++= ++++ 1 file changed, 108 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 3618812e84d5..47d7196460ee 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -2454,6 +2454,82 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4= x2_pcie_ep_pcs_misc_tbl[] =3D QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08), }; =20 +static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_serdes_tbl[] = =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x4c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0), +}; + +static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_phy_init_tbl sm8475_qmp_gen3x1_pcie_pcs_misc_tbl[]= =3D { + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1), + QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00), +}; + static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), @@ -4406,6 +4482,35 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pc= iephy_cfg =3D { .aux_clock_rate =3D 20000000, }; =20 +static const struct qmp_phy_cfg sm8475_qmp_gen3x1_pciephy_cfg =3D { + .lanes =3D 1, + + .offsets =3D &qmp_pcie_offsets_v5, + + .tbls =3D { + .serdes =3D sm8475_qmp_gen3x1_pcie_serdes_tbl, + .serdes_num =3D ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_serdes_tbl), + .tx =3D sm8550_qmp_gen3x2_pcie_tx_tbl, + .tx_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl), + .rx =3D sm8475_qmp_gen3x1_pcie_rx_tbl, + .rx_num =3D ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_rx_tbl), + .pcs =3D sm8550_qmp_gen3x2_pcie_pcs_tbl, + .pcs_num =3D ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl), + .pcs_misc =3D sm8475_qmp_gen3x1_pcie_pcs_misc_tbl, + .pcs_misc_num =3D ARRAY_SIZE(sm8475_qmp_gen3x1_pcie_pcs_misc_tbl), + .pcs_lane1 =3D sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl, + .pcs_lane1_num =3D ARRAY_SIZE(sar2130p_qmp_gen3x2_pcie_pcs_lane1_tbl), + }, + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .regs =3D pciephy_v6_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS, +}; + static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg =3D { .lanes =3D 2, =20 @@ -5631,6 +5736,9 @@ static const struct of_device_id qmp_pcie_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,sm8450-qmp-gen4x2-pcie-phy", .data =3D &sm8450_qmp_gen4x2_pciephy_cfg, + }, { + .compatible =3D "qcom,sm8475-qmp-gen3x1-pcie-phy", + .data =3D &sm8475_qmp_gen3x1_pciephy_cfg, }, { .compatible =3D "qcom,sm8550-qmp-gen3x2-pcie-phy", .data =3D &sm8550_qmp_gen3x2_pciephy_cfg, --=20 2.55.0 From nobody Sat Jul 25 20:08:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A322137AA95; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-sm8475-bup-v1-4-b2871be2b4ec@proton.me> References: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> In-Reply-To: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784011013; l=1034; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=PFP6IUISjVGd8cu9nI1mb8qZCo6FrND8DguB7XWFWvU=; b=Knlwubmm3cj+tjfc+xBpN8HYB1V46nzV6q3q+6JzCvyRUeRuUxRW9y10afVId2G8FiX1ImDZ6 KipU2bPxOM6CpEpyjm4CljVsDSfrZV8o0mJIHoVfVGhl+VcTHijG28d X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia SM8450 init sequence for this PHY varies significantly and can't be used in SM8475. Add proper init sequence and bindings for the PHY found in this SoC. Signed-off-by: Esteban Urrutia --- Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml |= 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43d= p-phy.yaml index 4eff92343ce4..b9d0de25f43c 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.y= aml @@ -37,6 +37,7 @@ properties: - qcom,sm8250-qmp-usb3-dp-phy - qcom,sm8350-qmp-usb3-dp-phy - qcom,sm8450-qmp-usb3-dp-phy + - qcom,sm8475-qmp-usb3-dp-phy - qcom,sm8550-qmp-usb3-dp-phy - qcom,sm8650-qmp-usb3-dp-phy - qcom,sm8750-qmp-usb3-dp-phy --=20 2.55.0 From nobody Sat Jul 25 20:08:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B55373DB329; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; cv=none; b=oY1do52ytc8rZ+4hkHMxqmqGx9bGhImZrIOMISYBggSlsSGe2/E4I6PMwaLD1KutMkzOxhfnnHrVggr6rFxeg5iD5uAJviTGjc6H8oMYKlrCornHTyGDweciWXsxcc64KoHbNMmIjY39o0azpscrpTNpGIiCztpsHY5GbjZWejs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; c=relaxed/simple; bh=BmjNwW2GrvmbXnV3xY6LBLF+hBmbOUehz7dVQDQK/xg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=g/qtEOg2OHr5f1AvnHaiBrLcs7ch9rfdYshBcnVkztd98LK2lWFQPpYBb5tHLdS37//736ZcSdva92Grpc6yXQSyuPLoush4RVv9iLDDyEHmIpBNdMYuodgwCY0lnFlcRJKs667reJd3Zn7wVGijSPnMghQC70fDBR5iw8e2gck= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=FziAKfl0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="FziAKfl0" Received: by smtp.kernel.org (Postfix) with ESMTPS id 7DBD6C2BCC9; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784011015; bh=BmjNwW2GrvmbXnV3xY6LBLF+hBmbOUehz7dVQDQK/xg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=FziAKfl0Rc+7F1FE6UmI2RYMK2tnVYHBMBnTPRlbcLxjQOAt3lhu36VwZDhOQ2FK1 0TO64Q1LF7bZsh0W9OsyTspQ4O/fvivlBJD4PGbTb1WCS6Ze6pw4N1jTrbewuLXgHo 5YnFBpOQgzs1au8rZNdK2pWg08yTCcsCXDApR52QTiI8YXw3PO1sdHkUB5btAF1hcP jGukkpuwrEy5rmMtV78FVUVRsLNS+dX+H932G+SeTyvzw9MF9WZIrow2J8itEZeins vf0BoBlMgSuhDvnJe8TspxrJuuXgjKtWtvsqIJb5Ot+ZEa+mySZTSJKFuxCHZAkJlb e65YELv8mOphQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B7AFC44507; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Tue, 14 Jul 2026 02:36:43 -0400 Subject: [PATCH 5/6] phy: qcom: qmp-combo: Add serdes and RBR/HBR/HBR2/HBR3 tables for v1 DP PLLs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-sm8475-bup-v1-5-b2871be2b4ec@proton.me> References: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> In-Reply-To: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784011013; l=13250; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=+/TDxSqbOiuBRvtOrwuUu9yWXKYD8U5nmYomWVInFUA=; b=lb2/Z/G7lyHJucs9SVtG2+7buZ0P/obAciorxxqaE3QXzsyuXGyxyH3jq7cmXBldUPhUw6J5u uB2BvK7d3FKAuMM7C9OVAIps9gbLDW+ZW7u3P9jasd/NIW2p/7bdeZN X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia These tables for v6 PHYs only cover PLL v1.1. For serdes, the difference between v1 and v1.1 is the value written to the BG_TIMER offset. This value is set to 0x0e for v1 PLLs and 0x0a for v1.1 PLLs. (SM8550, SM8650 use a v1.1 PLL) For RBR/HBR/HBR2/HBR3, most values change. Add support for v1 DP PLLs to accommodate SM8475 support, since SM8475 uses a v1 PLL. Signed-off-by: Esteban Urrutia --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 161 +++++++++++++++++++++-----= ---- 1 file changed, 116 insertions(+), 45 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index cdcfad2e86b1..8c09d4c1594d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1337,7 +1337,30 @@ static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_t= x_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), @@ -1471,7 +1494,55 @@ static const struct qmp_phy_init_tbl qmp_v8_n3p_dp_t= x_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V8_LALB_TX1_RESTRIM_POST_CAL_OFFSET, 0x10), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_rbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x6f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr2[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x1f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1c), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x2e), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x21), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_serdes_tbl_hbr3[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x2a), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xe2), + QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x18), +}; + +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), @@ -1483,7 +1554,7 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes= _tbl_rbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), @@ -1495,7 +1566,7 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes= _tbl_hbr[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), @@ -1507,7 +1578,7 @@ static const struct qmp_phy_init_tbl qmp_v6_dp_serdes= _tbl_hbr2[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), }; =20 -static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] =3D { +static const struct qmp_phy_init_tbl qmp_v6_dp_v1_1_serdes_tbl_hbr3[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), @@ -2443,19 +2514,19 @@ static const struct qmp_phy_cfg sar2130p_usb3dpphy_= cfg =3D { .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v5_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, @@ -2859,19 +2930,19 @@ static const struct qmp_phy_cfg sm8550_usb3dpphy_cf= g =3D { .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v5_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, @@ -2905,19 +2976,19 @@ static const struct qmp_phy_cfg sm8650_usb3dpphy_cf= g =3D { .pcs_usb_tbl =3D sm8550_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v6_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, @@ -2951,19 +3022,19 @@ static const struct qmp_phy_cfg sm8750_usb3dpphy_cf= g =3D { .pcs_usb_tbl =3D sm8750_usb3_pcs_usb_tbl, .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl), =20 - .dp_serdes_tbl =3D qmp_v6_dp_serdes_tbl, - .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl), + .dp_serdes_tbl =3D qmp_v6_dp_v1_1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl), .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), =20 - .serdes_tbl_rbr =3D qmp_v6_dp_serdes_tbl_rbr, - .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), - .serdes_tbl_hbr =3D qmp_v6_dp_serdes_tbl_hbr, - .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), - .serdes_tbl_hbr2 =3D qmp_v6_dp_serdes_tbl_hbr2, - .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), - .serdes_tbl_hbr3 =3D qmp_v6_dp_serdes_tbl_hbr3, - .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), + .serdes_tbl_rbr =3D qmp_v6_dp_v1_1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_1_serdes_tbl_hbr3), =20 .swing_hbr_rbr =3D &qmp_dp_v6_voltage_swing_hbr_rbr, .pre_emphasis_hbr_rbr =3D &qmp_dp_v6_pre_emphasis_hbr_rbr, --=20 2.55.0 From nobody Sat Jul 25 20:08:04 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B22AF3DB313; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; cv=none; b=bK0eGA9QOxcO0wEtQBFnjVvYOqXr4QfeYXQu7R91Q90qwe9lpKYXiU2wgAavtAbCy1djWAS/8x5+kZbLXAa4ktaegwTfhDSt8JK3FM8xcrHDhXBSKjf38Iu8u9Uli9dM4VTbcsfJsEF/73tvh/ZrocmEDTz5FcCQHYZtCwUNcNg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784011015; c=relaxed/simple; bh=9aEnL+es+MSH6q7UQRCE8ic9gcmU2MDfIJWI1DuScJs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kye4+RedfbAO4CXY/GyWMz8Rm3lQWNUQFZMK/OsQelW5bqwHoa+A5VaQzLciFAXkWK9C8imQrEbKlAI61aTw8wZ0gz7zkDJYswd6rXGOePhFqC4TP4bJo4EZJ8UKOiUeGQgtpdcnkIydb0jy5R9PQjz81zuZGuQKnUpka+Ey/Vg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=M4zS94v9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M4zS94v9" Received: by smtp.kernel.org (Postfix) with ESMTPS id 90A94C2BCF4; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1784011015; bh=9aEnL+es+MSH6q7UQRCE8ic9gcmU2MDfIJWI1DuScJs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=M4zS94v9gwVyJ9KQNZSrpxo/np7SdXXlsyOSegmrpwFqjlvHpw6OucMfaHGsYISzy hFu64WIiCEqMwMZT91Yua5XD7Uns5K7FNYPSNEV7wXpQRzN4JkDukZkS/zVSHqaZQt lZQRzpTS4K5ml2X4maABEKWet0Q4x3sA8/Qv8QK1qSm7YTb54EiH+Yg32qUXrXpsuy qKleKpPVX8BjvLGJTfDCs0xUMFS4VKQ+0ojpmw5qMDwuvWaCJP5Byc8kr4SxcpEpoc VxdZoEWwb79K6EgdSMEqJ+gV0n28RBvUMQAakL/xEh8G2x6Ev0cFzNPD9QiWEQWT8F FCUXztty4t/CA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D937C44501; Tue, 14 Jul 2026 06:36:55 +0000 (UTC) From: Esteban Urrutia via B4 Relay Date: Tue, 14 Jul 2026 02:36:44 -0400 Subject: [PATCH 6/6] phy: qcom: qmp-combo: Add SM8475 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-sm8475-bup-v1-6-b2871be2b4ec@proton.me> References: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> In-Reply-To: <20260714-sm8475-bup-v1-0-b2871be2b4ec@proton.me> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, Esteban Urrutia X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784011013; l=6273; i=esteuwu@proton.me; s=20260622; h=from:subject:message-id; bh=l8Rkej+0h7wvF/bIVM/iuKPbfudwVU2u2ZL1EKqHYPE=; b=Us3Oxq4zoWIevlYgF8eNL6nRPLW++WOfNB3pZqLG7kwzuH5COO52F6y9cWVvzLIM7O6wiKcYy 3sicrjHOzgYBSWDpZwfthW5zfmQ+KS3nbalsWa9yRyWjV/C4tj1jqwK X-Developer-Key: i=esteuwu@proton.me; a=ed25519; pk=wToFt4mOAWkzbqb15Ye1hrhevI13vK9BcMUFiQ/me1M= X-Endpoint-Received: by B4 Relay for esteuwu@proton.me/20260622 with auth_id=835 X-Original-From: Esteban Urrutia Reply-To: esteuwu@proton.me From: Esteban Urrutia Has been tested with the following capabilities: - USB Type-C at 10Gb/s - DP Alt Mode, using HBR2 - USB Type-C at 480Mb/s + DP Alt Mode, using HBR2 RX and PCS USB tables had to be added, while serdes, TX and PCS tables were reused from other SoCs. Signed-off-by: Esteban Urrutia --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 98 +++++++++++++++++++++++++++= ++++ 1 file changed, 98 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualco= mm/phy-qcom-qmp-combo.c index 8c09d4c1594d..2a58a1c3cb64 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -1063,6 +1063,55 @@ static const struct qmp_phy_init_tbl sm8350_usb3_pcs= _usb_tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), }; =20 +static const struct qmp_phy_init_tbl sm8475_usb3_rx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x08), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfe), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), + QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), +}; + +static const struct qmp_phy_init_tbl sm8475_usb3_pcs_usb_tbl[] =3D { + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), + QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), +}; + static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), @@ -2916,6 +2965,51 @@ static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg= =3D { .has_pwrdn_delay =3D true, }; =20 +static const struct qmp_phy_cfg sm8475_usb3dpphy_cfg =3D { + .offsets =3D &qmp_combo_offsets_v3, + + .serdes_tbl =3D sar2130p_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(sar2130p_usb3_serdes_tbl), + .tx_tbl =3D sm8550_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(sm8550_usb3_tx_tbl), + .rx_tbl =3D sm8475_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(sm8475_usb3_rx_tbl), + .pcs_tbl =3D sm8550_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(sm8550_usb3_pcs_tbl), + .pcs_usb_tbl =3D sm8475_usb3_pcs_usb_tbl, + .pcs_usb_tbl_num =3D ARRAY_SIZE(sm8475_usb3_pcs_usb_tbl), + + .dp_serdes_tbl =3D qmp_v6_dp_v1_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl), + .dp_tx_tbl =3D qmp_v6_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qmp_v6_dp_tx_tbl), + + .serdes_tbl_rbr =3D qmp_v6_dp_v1_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qmp_v6_dp_v1_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qmp_v6_dp_v1_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr2), + .serdes_tbl_hbr3 =3D qmp_v6_dp_v1_serdes_tbl_hbr3, + .serdes_tbl_hbr3_num =3D ARRAY_SIZE(qmp_v6_dp_v1_serdes_tbl_hbr3), + + .swing_hbr_rbr =3D &qmp_dp_v4_voltage_swing_hbr_rbr, + .pre_emphasis_hbr_rbr =3D &qmp_dp_v4_pre_emphasis_hbr_rbr, + .swing_hbr3_hbr2 =3D &qmp_dp_v3_voltage_swing_hbr3_hbr2, + .pre_emphasis_hbr3_hbr2 =3D &qmp_dp_v4_pre_emphasis_hbr3_hbr2, + + .dp_aux_init =3D qmp_v4_dp_aux_init, + .configure_dp_tx =3D qmp_v4_configure_dp_tx, + .configure_dp_clocks =3D qmp_v3_configure_dp_clocks, + .configure_dp_phy =3D qmp_v4_configure_dp_phy, + + .regs =3D qmp_v6_usb3phy_regs_layout, + .reset_list =3D msm8996_usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(msm8996_usb3phy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), +}; + static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg =3D { .offsets =3D &qmp_combo_offsets_v3, =20 @@ -5103,6 +5197,10 @@ static const struct of_device_id qmp_combo_of_match_= table[] =3D { .compatible =3D "qcom,sm8450-qmp-usb3-dp-phy", .data =3D &sm8350_usb3dpphy_cfg, }, + { + .compatible =3D "qcom,sm8475-qmp-usb3-dp-phy", + .data =3D &sm8475_usb3dpphy_cfg, + }, { .compatible =3D "qcom,sm8550-qmp-usb3-dp-phy", .data =3D &sm8550_usb3dpphy_cfg, --=20 2.55.0