From nobody Sat Jul 25 20:48:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA5A1352C52; Mon, 13 Jul 2026 20:05:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783973134; cv=none; b=aYGvnpBG0b+RUwnQNP3UDwpQjahBOwgXNa6k8Dfe0/8vmX2o4dWg9BxuXZSWJRFWFuVpf+HE+D2oyJvfQWc8Y640gzUBxoADZlXvSl1b02jCFTQ7m7cLfEWP1Iv7IjHm0rNuS1YfmWZ6rZ9zccO58rwt4IzgpzuulPMxMsAlfYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783973134; c=relaxed/simple; bh=J4U5ckGUKDpq/URapFQppuBePtObl8xHnE3TqwFFM6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nkhflz6ELW9Kiv6M7hDUM065hHt6lzIihKHCMXnjXCdlCNfLyL0Mw0OlWUhik1u1YEqeQVjrdK//MyF7hpEKSmXXt4pSDat3qYobLae5uxZULnYICmv9MRqR0cTsWUKK6OFw6FIp8BDbhUozq3nIsrXr27QKdwvQVnSPf4zmZo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bxtzzwDR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bxtzzwDR" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8F66AC2BCF4; Mon, 13 Jul 2026 20:05:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1783973133; bh=J4U5ckGUKDpq/URapFQppuBePtObl8xHnE3TqwFFM6Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bxtzzwDRJuZKs3HqAv3B5Ti5c5CgPtq0U1qiFhXQkT1qmWOj6d67DBUdYTLCDJlGo 7muKa27lKjopyHNU/PN5Zr3saigt0jiwsxf4aOOg9jGO5avlcGPzk4V1ZbKeYTnS4Y 2yPahQc4MTeEtC5ylaXviFslKPjdb2ECrq9uJkSJGqc5ZznRUqCHpWMFXi9jbI809n U5eC1o1UfcM/2yhip9BKx/vyaqZO8AUas1GxPz6W79pEXsC6PYtLSLXC35ie0ExDzL r88Y6Pd7ITfMXFpTbiEczoTlJdz4AsEe66hAQVOxMUtVK8R9KEJNp1td+6cW73wNZ3 /a/NXJOiIUVyg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6EFF3C44507; Mon, 13 Jul 2026 20:05:33 +0000 (UTC) From: Sarath Ganapathiraju via B4 Relay Date: Tue, 14 Jul 2026 01:35:32 +0530 Subject: [PATCH 1/2] ASoC: dt-bindings: qcom,lpass-va-csr: Add HeartBeat pulse clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-master-v1-1-1ebe5993225e@oss.qualcomm.com> References: <20260714-master-v1-0-1ebe5993225e@oss.qualcomm.com> In-Reply-To: <20260714-master-v1-0-1ebe5993225e@oss.qualcomm.com> To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: Srinivas Kandagatla , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com, Sarath Ganapathiraju X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783973132; l=3495; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=RbD5mg4ILVqZOMn1H2IVY7wxyZAxnDGJwjZKThdsa64=; b=h3h+596bSMJnpGEJ84mEFcm+pQkY7CCeRfkm8dGQ24+MDwGMQ+Q1j/rhGLSiF1S6Ex07exWgr z3yrEBKvxqMASu4TBX0yutnTs3PWaOdG9ELJHnO5UzTRVgThETZXSpw X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com From: Sarath Ganapathiraju Add Qualcomm LPASS VA CSR rate generator node that exposes the lpass_heartbeat_pulse clock on hawi. Also extend the qcom,lpass-va-macro binding to add qcom,hawi-lpass-va-macro with its four-clock constraint (mclk, macro, dcodec, heartbeatpulse). The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecase and can serve as a periodic wakeup source for the DSP. Signed-off-by: Sarath Ganapathiraju --- .../bindings/sound/qcom,lpass-va-csr.yaml | 47 ++++++++++++++++++= ++++ .../bindings/sound/qcom,lpass-va-macro.yaml | 18 +++++++++ 2 files changed, 65 insertions(+) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-csr.yaml= b/Documentation/devicetree/bindings/sound/qcom,lpass-va-csr.yaml new file mode 100644 index 000000000..794da92ad --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-csr.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,lpass-va-csr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm LPASS VA CSR heartbeat pulse clock provider + +maintainers: + - Srinivas Kandagatla + - Sarath Ganapathiraju + +description: + The LPASS VA CSR block contains the rate generator hardware which + produces the heartbeatpulse consumed by the Bolero codec macros + (rx, tx, wsa, va). It is modelled as a clock provider + so consumers can reference it by name in their clocks list. + +properties: + compatible: + enum: + - qcom,hawi-lpass-va-csr + + reg: + maxItems: 1 + description: Must cover the full VA CSR block (base 0x7EE0000, size 0x= E000). + + "#clock-cells": + const: 0 + description: + Single clock output "lpass_heartbeat_pulse". Consumers reference + it by clock-name "heartbeatpulse" in their clocks list. + +required: + - compatible + - reg + - "#clock-cells" + +unevaluatedProperties: false + +examples: + - | + va-csr@7ee0000 { + compatible =3D "qcom,hawi-lpass-va-csr"; + reg =3D <0x0 0x07ee0000 0x0 0xe000>; + #clock-cells =3D <0>; + }; diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index aea31fbda..ae4df8967 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -19,6 +19,7 @@ properties: - qcom,sm8450-lpass-va-macro - qcom,sm8550-lpass-va-macro - qcom,sc8280xp-lpass-va-macro + - qcom,hawi-lpass-va-macro - items: - enum: - qcom,eliza-lpass-va-macro @@ -168,6 +169,23 @@ allOf: - const: macro - const: dcodec =20 + - if: + properties: + compatible: + contains: + const: qcom,hawi-lpass-va-macro + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: mclk + - const: macro + - const: dcodec + - const: heartbeatpulse + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Sat Jul 25 20:48:39 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA4A32D46B3; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-master-v1-2-1ebe5993225e@oss.qualcomm.com> References: <20260714-master-v1-0-1ebe5993225e@oss.qualcomm.com> In-Reply-To: <20260714-master-v1-0-1ebe5993225e@oss.qualcomm.com> To: Srinivas Kandagatla , Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jaroslav Kysela , Takashi Iwai Cc: Srinivas Kandagatla , linux-sound@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, prasad.kumpatla@oss.qualcomm.com, Sarath Ganapathiraju X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1783973132; l=6958; i=sarath.ganapathiraju@oss.qualcomm.com; s=default; h=from:subject:message-id; bh=ypNbWhmhzRsGcz5RvLQ5KhScCqzC7URlIIzBE8KzUXI=; b=jWXpRi8qLEsCDpGs2R6QKLBtDQk4IyUTfcDPlrAlxRTTyCCZ928q3c0qQxjMrF4WR4+pz5iXF JUKHA4nbeKHBchnSagbHeaPQ8gxJSjduHsSAb8bDp2qnSFVGguuddYQ X-Developer-Key: i=sarath.ganapathiraju@oss.qualcomm.com; a=ed25519; pk=4p2FWGXM+F2sir13Lu5stw5aKX5trUymK/ttESvgxQg= X-Endpoint-Received: by B4 Relay for sarath.ganapathiraju@oss.qualcomm.com/default with auth_id=870 X-Original-From: Sarath Ganapathiraju Reply-To: sarath.ganapathiraju@oss.qualcomm.com From: Sarath Ganapathiraju The HeartBeat Pulse (also known as RateGen Pulse) synchronizes the start of the DMAs and Codec Interfaces for the audio usecases and can serve as a periodic wakeup source for the DSP. Add the LPASS VA CSR driver that models the rate generator as a clock provider so it is enabled and disabled automatically alongside the other clocks during runtime PM resume and suspend. Signed-off-by: Sarath Ganapathiraju --- sound/soc/codecs/Kconfig | 13 ++++ sound/soc/codecs/Makefile | 2 + sound/soc/codecs/lpass-va-csr.c | 143 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 158 insertions(+) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index a41d0f508..e898c34a6 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -2902,11 +2902,24 @@ config SND_SOC_LPASS_WSA_MACRO select SND_SOC_LPASS_MACRO_COMMON tristate "Qualcomm WSA Macro in LPASS(Low Power Audio SubSystem)" =20 +config SND_SOC_LPASS_VA_CSR + depends on COMMON_CLK + select REGMAP_MMIO + tristate "Qualcomm LPASS VA CSR heartbeat pulse clock provider" + help + Qualcomm LPASS VA CSR block contains the rate generator hardware + that produces the HeartBeat Pulse (also known as RateGen Pulse). + This driver models the rate generator as a clock provider so + that consumers can enable or disable it via the common clock + framework, and it can be used to synchronize the start of DMAs + and Codec Interfaces or as a periodic wakeup source for the DSP. + config SND_SOC_LPASS_VA_MACRO depends on COMMON_CLK depends on PM_CLK select REGMAP_MMIO select SND_SOC_LPASS_MACRO_COMMON + select SND_SOC_LPASS_VA_CSR tristate "Qualcomm VA Macro in LPASS(Low Power Audio SubSystem)" =20 config SND_SOC_LPASS_RX_MACRO diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile index aa0396e5b..3e86c1bbf 100644 --- a/sound/soc/codecs/Makefile +++ b/sound/soc/codecs/Makefile @@ -163,6 +163,7 @@ snd-soc-lpass-rx-macro-y :=3D lpass-rx-macro.o snd-soc-lpass-tx-macro-y :=3D lpass-tx-macro.o snd-soc-lpass-wsa-macro-y :=3D lpass-wsa-macro.o snd-soc-lpass-va-macro-y :=3D lpass-va-macro.o +snd-soc-lpass-va-csr-y :=3D lpass-va-csr.o snd-soc-madera-y :=3D madera.o snd-soc-max9759-y :=3D max9759.o snd-soc-max9768-y :=3D max9768.o @@ -886,6 +887,7 @@ obj-$(CONFIG_SND_SOC_TPA6130A2) +=3D snd-soc-tpa6130a2.o obj-$(CONFIG_SND_SOC_LPASS_MACRO_COMMON) +=3D snd-soc-lpass-macro-common.o obj-$(CONFIG_SND_SOC_LPASS_WSA_MACRO) +=3D snd-soc-lpass-wsa-macro.o obj-$(CONFIG_SND_SOC_LPASS_VA_MACRO) +=3D snd-soc-lpass-va-macro.o +obj-$(CONFIG_SND_SOC_LPASS_VA_CSR) +=3D snd-soc-lpass-va-csr.o obj-$(CONFIG_SND_SOC_LPASS_RX_MACRO) +=3D snd-soc-lpass-rx-macro.o obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO) +=3D snd-soc-lpass-tx-macro.o =20 diff --git a/sound/soc/codecs/lpass-va-csr.c b/sound/soc/codecs/lpass-va-cs= r.c new file mode 100644 index 000000000..14aec8f94 --- /dev/null +++ b/sound/soc/codecs/lpass-va-csr.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#define LPASS_RATE_GEN_CTRL 0xD000 +#define LPASS_RATE_GEN_COUNTER_0 0xD004 +#define LPASS_RATE_GEN_DELAY 0xD010 + +#define LPASS_RATE_GEN_MAX_REG LPASS_RATE_GEN_DELAY + +#define LPASS_RG_CTRL_EN BIT(0) + +struct lpass_va_csr_data { + u32 counter_0; + u32 delay; +}; + +static const struct lpass_va_csr_data hawi_csr_data =3D { + .counter_0 =3D 0x960, + .delay =3D 0x16, +}; + +static const struct regmap_config lpass_rate_gen_regmap_config =3D { + .name =3D "lpass_rate_gen", + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .max_register =3D LPASS_RATE_GEN_MAX_REG, + .cache_type =3D REGCACHE_MAPLE, +}; + +struct lpass_va_csr { + struct regmap *regmap; + const struct lpass_va_csr_data *data; + struct clk_hw hb_hw; +}; + +#define to_lpass_va_csr(_hw) container_of(_hw, struct lpass_va_csr, hb_hw) + +static int heartbeat_pulse_enable(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + regmap_write(csr->regmap, LPASS_RATE_GEN_COUNTER_0, csr->data->counter_0); + regmap_write(csr->regmap, LPASS_RATE_GEN_DELAY, csr->data->delay); + regmap_update_bits(csr->regmap, LPASS_RATE_GEN_CTRL, + LPASS_RG_CTRL_EN, LPASS_RG_CTRL_EN); + + return 0; +} + +static void heartbeat_pulse_disable(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + + regmap_update_bits(csr->regmap, LPASS_RATE_GEN_CTRL, + LPASS_RG_CTRL_EN, 0); +} + +static int heartbeat_pulse_is_enabled(struct clk_hw *hw) +{ + struct lpass_va_csr *csr =3D to_lpass_va_csr(hw); + unsigned int val; + + regmap_read(csr->regmap, LPASS_RATE_GEN_CTRL, &val); + + return !!(val & LPASS_RG_CTRL_EN); +} + +static const struct clk_ops heartbeat_pulse_ops =3D { + .enable =3D heartbeat_pulse_enable, + .disable =3D heartbeat_pulse_disable, + .is_enabled =3D heartbeat_pulse_is_enabled, +}; + +static int lpass_va_csr_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct lpass_va_csr *csr; + struct clk_init_data init =3D { + .name =3D "lpass_heartbeat_pulse", + .ops =3D &heartbeat_pulse_ops, + }; + void __iomem *base; + int ret; + + csr =3D devm_kzalloc(dev, sizeof(*csr), GFP_KERNEL); + if (!csr) + return -ENOMEM; + + csr->data =3D of_device_get_match_data(dev); + if (!csr->data) + return dev_err_probe(dev, -EINVAL, "no variant data for compatible\n"); + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + csr->regmap =3D devm_regmap_init_mmio(dev, base, + &lpass_rate_gen_regmap_config); + if (IS_ERR(csr->regmap)) + return dev_err_probe(dev, PTR_ERR(csr->regmap), + "failed to init regmap\n"); + + csr->hb_hw.init =3D &init; + + ret =3D devm_clk_hw_register(dev, &csr->hb_hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register heartbeat clock\n"); + + ret =3D devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &csr->hb_h= w); + if (ret) + return dev_err_probe(dev, ret, "failed to add clock provider\n"); + + return 0; +} + +static const struct of_device_id lpass_va_csr_dt_match[] =3D { + { .compatible =3D "qcom,hawi-lpass-va-csr", .data =3D &hawi_csr_data }, + {} +}; +MODULE_DEVICE_TABLE(of, lpass_va_csr_dt_match); + +static struct platform_driver lpass_va_csr_driver =3D { + .driver =3D { + .name =3D "qcom-lpass-va-csr", + .of_match_table =3D lpass_va_csr_dt_match, + }, + .probe =3D lpass_va_csr_probe, +}; + +module_platform_driver(lpass_va_csr_driver); + +MODULE_DESCRIPTION("Qualcomm LPASS VA CSR heartbeat pulse clock provider"); +MODULE_LICENSE("GPL"); --=20 2.34.1