From nobody Sat Jul 25 20:10:45 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AF052E2663 for ; Tue, 14 Jul 2026 04:29:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784003374; cv=none; b=eEPo7k9PEJhVb/G3YsLYlLaHIU5iptfVU6ljxfNMnrVxphJq5znt8kBXhfHmW0Bkdf29BK5vm/3D/U3WPGXtf3PxJlXVL2GkOffwBAWSuelxDDO1GAMjcQtaq5jIPvSmAqDE+UykEiss9ZUkvWU0QPVN/Y4jFXhSORBRGfAVfcw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784003374; c=relaxed/simple; bh=ZQvK0C6JiF+FMSs4PbOUu2p+wZuOV8/Ns8q6nnz3kZE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=O6pQVMM8rT4sN0SNRnmLmRWhptOxNgJ0Gy/QIUmbPgqBP26UffH+1NtXlatLSc9sqNHR2YcWtKvEevqzQdkTPNtm9+ZXPwg1KQeUFOAU2oseBMhEXntuvVNCVNut2RKw1X9wuljyv0WAlUOe0aFJYPNOrQjNIo/NQv897eCtYIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=DP8zWPF2; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=SPwIlsGP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="DP8zWPF2"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="SPwIlsGP" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66E3ep4C3365288 for ; Tue, 14 Jul 2026 04:29:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= u1/Y33mFmGDlMS3sYpBNbK/O0k52IHx7NX0nZ2tZh8s=; b=DP8zWPF2CELWEpuR w0ItZF8vWcZW+CHqw39l7epbuhoyOJVgebtRS3dHpvobPQL3xhOvOFXxCbkRCZfU kmv/+M40H1dp8od3Y9OfSZD2IC0K8vupdfpjC4NEv3roDrg1v1W3hu09Jmt1iLPe 8w9quJ3C8T7dvy6YyZMEpW9BN3nwIkmyMS7BBMxKwSqGbJcqSAOd4FKgkce0xeZP DT2W4v8iEg5jTFo6HMh9m35GbMx1weLxyconMZQ++cMemMts1O+lp4a+OBnzWyO7 ZzVJ5rTJn9QKzo2TJvhKb/qAM6npFrSpmtMQaK7gMV+UWhJjzgRiiAsx8k4zSXTd JI/aTw== Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fdde084v0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 04:29:30 +0000 (GMT) Received: by mail-pg1-f199.google.com with SMTP id 41be03b00d2f7-c9d5a5b63c5so5734388a12.1 for ; Mon, 13 Jul 2026 21:29:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784003370; x=1784608170; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=u1/Y33mFmGDlMS3sYpBNbK/O0k52IHx7NX0nZ2tZh8s=; b=SPwIlsGPTpA6FJ6To7MgxiyppoIw4OjqpHszdnXgM+svnNmxu5LnlX5/WYE5Z8/e/s OLukWiX4oHCwCuPcO9W5jyA+4T1jbXvzROD7xgiq0+MFAaPspraoZ4T/aP4KQMhnm3W6 X5ZhWQ0vb+d2Z1fYZStK/hx3KKMyCVhOf/aefDzcdq9zWHcxYRr0K1EmYCLoEnLWRxfU gOLXJ5oPB2qJRxWN3dITccbBKp6DKJSLTVvikCxXMpcsB439kufNtM0Vn59XIgwcp6sB KQjRXhEbZSVHSELpOted4PLDdCgGPE3MJycyQYwLQD6O/QXcBJXpfneSbttuznGvDrcF S6sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784003370; x=1784608170; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=u1/Y33mFmGDlMS3sYpBNbK/O0k52IHx7NX0nZ2tZh8s=; b=lnXHbS25oo8JN9fDprWc/MM7MDgLDTDtMSzpja8VqeZmqdkdHeDPHq+EYB+mWDJO83 E2VZdIsm5HJeJXWUJIoiV0pBgoYb+a25GOb40/DGrGpD+QrxjiuvijbJKBcviRouVFNB x9XeiR0XPEECcCpgwMFm37PJi8Ib1XUJBW9xvHdvTDz5i9rWxhu3w/Rjenzel5fl7LIJ yX3l6dyDcL/2U8ffB6EEUdMQaod05nFuV/9OgnpSXrv8a63snrcM1ubdkInstx2JvYBN JbbkyZVft855lwmKsnEE1SAn73NbJMwbXfMA8Lbg1kMqFoQkBptfqZEZsx1vK1uG0YN5 narg== X-Forwarded-Encrypted: i=1; AHgh+Ro0j56zXLPoWBhPFzRKuo6W4A0F5uj1ZzgwHlLa1ZIC94p+qkcL8ev6vuj/z9YaWOh/eLSLiIO5FeQbOu4=@vger.kernel.org X-Gm-Message-State: AOJu0Yyk3JhPL++/l6ZWmihgaYZ9UZGlWbuAkbcrIV2ND0m72sy3GIf9 Yjgumvu6ue8r1HvjMnR2UMRGdZiHN1xN5gqK5Sq8+RnCNPpr+GCol4wFr6rPAH6Dj+OyVjfVZL0 UMdu4BLcZss5GDhGLSOcgErBZtXNwR1oBz2C5ROc/kk7e6G2ek8FtijWwiYZkC9L5LMo= X-Gm-Gg: AfdE7cmwXNJ8au83H69G9MV3mUDlaaGvjthQHl9Fk9Txq7CuH40foB2Pdz+4gvwayys S4gHRkKRQhT7O0KxIqxR1mDGxunduAs+w2/kA0UMSuaOia4zEaZ6mJi7axbZpQpm5vdaGvA1pYp Wj4s8mP9nQwFawceoI9QobLRZSoP4hlJVLFdNwP9XXVDLGudmyrTNqX67W7PTz8SZ6i27l8ipbA dkE++jY9TVyrY3cQFMnZV45KU7O8B8gP3dgOIBozXAU0Qf295oH9yWnkDhZwQYyRyZs1i/lvq+R b6EWzrjVDflZlRLu/3W/NTzcmMoUiUagi+eqqdeSkukeL+wazik5GvxXlMvJ64p1LyBPya6nX/c CNgkuG6PVNJdLbrIUn0KPkUoyLLZVnI7Etg+935kCmpgL1pWOD3VtHifJp4kfVIVREXAKquyU9c pXDnIJCY1OdlNLMPR8gNl86e8tkjoRv0+DWVBCIt5mTm/Zdw== X-Received: by 2002:a05:6a20:729c:b0:3c0:9c18:d5a8 with SMTP id adf61e73a8af0-3c35729f575mr953917637.69.1784003369868; Mon, 13 Jul 2026 21:29:29 -0700 (PDT) X-Received: by 2002:a05:6a20:729c:b0:3c0:9c18:d5a8 with SMTP id adf61e73a8af0-3c35729f575mr953875637.69.1784003369309; Mon, 13 Jul 2026 21:29:29 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-313b4cbafa1sm64388999eec.6.2026.07.13.21.29.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 21:29:28 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 09:59:16 +0530 Subject: [PATCH 1/2] arm64: dts: qcom: ipq9650: add the PCIe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-ipq9650_pcie-v1-1-4197749d06bd@oss.qualcomm.com> References: <20260714-ipq9650_pcie-v1-0-4197749d06bd@oss.qualcomm.com> In-Reply-To: <20260714-ipq9650_pcie-v1-0-4197749d06bd@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Manivannan Sadhasivam X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDA0MyBTYWx0ZWRfXyUJT0PuRpGQE ZhCCZhGFwe5cqfFHVI9jeqdkjcQ2oLoiqIJ6IdUKc3S8lALEoPonSQXKh+sTE4cdf/DJpH2NaGk c9RyIuxnHuf+BM1yn4hOo1nBouZnfjE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDA0MyBTYWx0ZWRfX5RO4atJ3LHXQ r/ehw2W7VftmxH6r7EGdvr1gC1R8YZVEBykNMDZV6eMKIsI9ZvvhrniRFPFtjrFPxQydnhS1Z7y ZFwS5JjuODo6seKfCPUgLt41k0nZ+52E/WAYU1S5lrkuXJajx+4U0+u3E/EfNk2e5p0xeILmrzr LoC6foPSzH9/9DjO3806Wv2c7uk23h+s9lUJ+Hl2Tjk0oVbmJgVsV6sa54vkvJv73N54OfaK0QG QBnWAN8tn6NOi7NrMbjJaQ71GSU5YX5JGCVi+9/4KYVEWDsWwOirDqT0l7gC3GS+ddXGySa4oOV Eedqn3WiorIkNSrnpfgp5DhCmDJ3zkA8UHNbrolsNXvIk3hBZqI/CWVUa0Vbwtj2NDDti5ICLmw WIa7rVJfLAuZP24yQZesVbYehaKd65ZE+eiKnQtLuBfTvt/rE8LtXi/DtMRl3UYkeFFmt9DFYQa A9cEGiTpGyJleQLr4gA== X-Proofpoint-ORIG-GUID: UTPSPY6Cj5xTjVQPijyvuHPK6OAt-Pi6 X-Proofpoint-GUID: UTPSPY6Cj5xTjVQPijyvuHPK6OAt-Pi6 X-Authority-Analysis: v=2.4 cv=F/FnsKhN c=1 sm=1 tr=0 ts=6a55bb2b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Jp5qG-MpaqbX_UUodeIA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_01,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140043 IPQ9650 has 5 Gen3 PCIe controllers - PCIe0 and PCIe4 are single lane and the remaining instances are dual lane. Add support for the same. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq9650.dtsi | 665 ++++++++++++++++++++++++++++++= +++- 1 file changed, 660 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq9650.dtsi b/arch/arm64/boot/dts/qc= om/ipq9650.dtsi index 3d3b317c6a3c..8301a4090395 100644 --- a/arch/arm64/boot/dts/qcom/ipq9650.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9650.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include =20 / { @@ -200,6 +201,160 @@ soc@0 { dma-ranges =3D <0 0 0 0 0x10 0>; ranges =3D <0 0 0 0 0x10 0>; =20 + refgen_pcie: regulator@6c000 { + compatible =3D "qcom,ipq9650-refgen-regulator"; + reg =3D <0x0 0x0006c000 0x0 0x84>; + clocks =3D <&gcc GCC_REFGEN_PCIE_CORE_CLK>, + <&gcc GCC_REFGEN_PCIE_HCLK>; + clock-names =3D "core", + "hclk"; + }; + + pcie0_phy: phy@84000 { + compatible =3D "qcom,ipq9650-qmp-gen3x1-pcie-phy"; + reg =3D <0x0 0x00084000 0x0 0x1000>; + + clocks =3D <&gcc GCC_PCIE0_AUX_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE0_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE0_PHY_BCR>, + <&gcc GCC_PCIE0PHY_PHY_BCR>; + reset-names =3D "phy", + "common"; + + refgen-supply =3D <&refgen_pcie>; + + clock-output-names =3D "pcie0_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie4_phy: phy@8c000 { + compatible =3D "qcom,ipq9650-qmp-gen3x1-pcie-phy"; + reg =3D <0x0 0x0008c000 0x0 0x1000>; + + clocks =3D <&gcc GCC_PCIE4_AUX_CLK>, + <&gcc GCC_PCIE4_AHB_CLK>, + <&gcc GCC_PCIE4_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE4_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE4_PHY_BCR>, + <&gcc GCC_PCIE4PHY_PHY_BCR>; + reset-names =3D "phy", + "common"; + + refgen-supply =3D <&refgen_pcie>; + + clock-output-names =3D "pcie4_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie3_phy: phy@b4000 { + compatible =3D "qcom,ipq9650-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x000b4000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE3_AUX_CLK>, + <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE3_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE3_PHY_BCR>, + <&gcc GCC_PCIE3PHY_PHY_BCR>; + reset-names =3D "phy", + "common"; + + refgen-supply =3D <&refgen_pcie>; + + clock-output-names =3D "pcie3_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie1_phy: phy@f4000 { + compatible =3D "qcom,ipq9650-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x000f4000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE1_AUX_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE1_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE1_PHY_BCR>, + <&gcc GCC_PCIE1PHY_PHY_BCR>; + reset-names =3D "phy", + "common"; + + refgen-supply =3D <&refgen_pcie>; + + clock-output-names =3D "pcie1_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + + pcie2_phy: phy@fc000 { + compatible =3D "qcom,ipq9650-qmp-gen3x2-pcie-phy"; + reg =3D <0x0 0x000fc000 0x0 0x2000>; + + clocks =3D <&gcc GCC_PCIE2_AUX_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_PIPE_CLK>; + clock-names =3D "aux", + "cfg_ahb", + "pipe"; + + assigned-clocks =3D <&gcc GCC_PCIE2_AUX_CLK>; + assigned-clock-rates =3D <20000000>; + + resets =3D <&gcc GCC_PCIE2_PHY_BCR>, + <&gcc GCC_PCIE2PHY_PHY_BCR>; + reset-names =3D "phy", + "common"; + + refgen-supply =3D <&refgen_pcie>; + + clock-output-names =3D "pcie2_pipe_clk"; + #clock-cells =3D <0>; + + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq9650-tlmm"; reg =3D <0x0 0x01000000 0x0 0x300000>; @@ -216,11 +371,11 @@ gcc: clock-controller@1800000 { reg =3D <0x0 0x01800000 0x0 0x40000>; clocks =3D <&xo_board>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, - <0>, + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie2_phy>, + <&pcie3_phy>, + <&pcie4_phy>, <0>, <0>; #clock-cells =3D <1>; @@ -371,6 +526,506 @@ frame@f42d000 { status =3D "disabled"; }; }; + + pcie3: pcie@30000000 { + compatible =3D "qcom,pcie-ipq9650", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x30000000 0x0 0xf1d>, + <0x0 0x30000f20 0x0 0xa8>, + <0x0 0x30001000 0x0 0x1000>, + <0x0 0x000b0000 0x0 0x3000>, + <0x0 0x30100000 0x0 0x1000>, + <0x0 0x000b6000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <3>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x00100000>, + <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x0fd00000>; + + msi-map =3D <0x0 &intc 0x0 0x1000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks =3D <&gcc GCC_PCIE3_AXI_M_CLK>, + <&gcc GCC_PCIE3_AXI_S_CLK>, + <&gcc GCC_PCIE3_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE3_RCHNG_CLK>, + <&gcc GCC_PCIE3_AHB_CLK>, + <&gcc GCC_PCIE3_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE3_PIPE_CLK_ARES>, + <&gcc GCC_PCIE3_CORE_STICKY_RESET>, + <&gcc GCC_PCIE3_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE3_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE3_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE3_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE3_AUX_CLK_ARES>, + <&gcc GCC_PCIE3_AHB_CLK_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_ANOC_PCIE3 &gcc SLAVE_ANOC_PCIE3>, + <&gcc MASTER_CNOC_PCIE3 &gcc SLAVE_CNOC_PCIE3>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie3_port0: pcie@0 { + compatible =3D "pciclass,0604"; + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie3_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie2: pcie@40000000 { + compatible =3D "qcom,pcie-ipq9650", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x40000000 0x0 0xf1d>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x1000>, + <0x0 0x000f8000 0x0 0x3000>, + <0x0 0x40100000 0x0 0x1000>, + <0x0 0x000fe000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <2>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x00100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x0fd00000>; + + msi-map =3D <0x0 &intc 0x0 0x1000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks =3D <&gcc GCC_PCIE2_AXI_M_CLK>, + <&gcc GCC_PCIE2_AXI_S_CLK>, + <&gcc GCC_PCIE2_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE2_RCHNG_CLK>, + <&gcc GCC_PCIE2_AHB_CLK>, + <&gcc GCC_PCIE2_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE2_PIPE_CLK_ARES>, + <&gcc GCC_PCIE2_CORE_STICKY_RESET>, + <&gcc GCC_PCIE2_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE2_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE2_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE2_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE2_AUX_CLK_ARES>, + <&gcc GCC_PCIE2_AHB_CLK_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_ANOC_PCIE2 &gcc SLAVE_ANOC_PCIE2>, + <&gcc MASTER_CNOC_PCIE2 &gcc SLAVE_CNOC_PCIE2>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie2_port0: pcie@0 { + compatible =3D "pciclass,0604"; + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie2_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie1: pcie@50000000 { + compatible =3D "qcom,pcie-ipq9650", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x50000000 0x0 0xf1d>, + <0x0 0x50000f20 0x0 0xa8>, + <0x0 0x50001000 0x0 0x1000>, + <0x0 0x000f0000 0x0 0x3000>, + <0x0 0x50100000 0x0 0x1000>, + <0x0 0x000f6000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x50200000 0x0 0x00100000>, + <0x02000000 0x0 0x50300000 0x0 0x50300000 0x0 0x0fd00000>; + + msi-map =3D <0x0 &intc 0x0 0x1000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks =3D <&gcc GCC_PCIE1_AXI_M_CLK>, + <&gcc GCC_PCIE1_AXI_S_CLK>, + <&gcc GCC_PCIE1_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE1_RCHNG_CLK>, + <&gcc GCC_PCIE1_AHB_CLK>, + <&gcc GCC_PCIE1_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE1_PIPE_CLK_ARES>, + <&gcc GCC_PCIE1_CORE_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE1_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE1_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE1_AUX_CLK_ARES>, + <&gcc GCC_PCIE1_AHB_CLK_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_ANOC_PCIE1 &gcc SLAVE_ANOC_PCIE1>, + <&gcc MASTER_CNOC_PCIE1 &gcc SLAVE_CNOC_PCIE1>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie1_port0: pcie@0 { + compatible =3D "pciclass,0604"; + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie1_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie4: pcie@60000000 { + compatible =3D "qcom,pcie-ipq9650", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x60000000 0x0 0xf1d>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x1000>, + <0x0 0x00088000 0x0 0x3000>, + <0x0 0x60100000 0x0 0x1000>, + <0x0 0x0008e000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <4>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x00100000>, + <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x0fd00000>; + + msi-map =3D <0x0 &intc 0x0 0x1000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks =3D <&gcc GCC_PCIE4_AXI_M_CLK>, + <&gcc GCC_PCIE4_AXI_S_CLK>, + <&gcc GCC_PCIE4_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE4_RCHNG_CLK>, + <&gcc GCC_PCIE4_AHB_CLK>, + <&gcc GCC_PCIE4_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE4_PIPE_CLK_ARES>, + <&gcc GCC_PCIE4_CORE_STICKY_RESET>, + <&gcc GCC_PCIE4_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE4_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE4_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE4_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE4_AUX_CLK_ARES>, + <&gcc GCC_PCIE4_AHB_CLK_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_ANOC_PCIE4 &gcc SLAVE_ANOC_PCIE4>, + <&gcc MASTER_CNOC_PCIE4 &gcc SLAVE_CNOC_PCIE4>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie4_port0: pcie@0 { + compatible =3D "pciclass,0604"; + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie4_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; + + pcie0: pcie@70000000 { + compatible =3D "qcom,pcie-ipq9650", "qcom,pcie-ipq9574"; + reg =3D <0x0 0x70000000 0x0 0xf1d>, + <0x0 0x70000f20 0x0 0xa8>, + <0x0 0x70001000 0x0 0x1000>, + <0x0 0x00080000 0x0 0x3000>, + <0x0 0x70100000 0x0 0x1000>, + <0x0 0x00086000 0x0 0x1000>; + reg-names =3D "dbi", + "elbi", + "atu", + "parf", + "config", + "mhi"; + device_type =3D "pci"; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + + ranges =3D <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x00100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x0fd00000>; + + msi-map =3D <0x0 &intc 0x0 0x1000>; + + interrupts =3D , + , + , + , + , + , + , + , + ; + interrupt-names =3D "msi0", + "msi1", + "msi2", + "msi3", + "msi4", + "msi5", + "msi6", + "msi7", + "global"; + + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &intc GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &intc GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>; + + clocks =3D <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, + <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, + <&gcc GCC_PCIE0_RCHNG_CLK>, + <&gcc GCC_PCIE0_AHB_CLK>, + <&gcc GCC_PCIE0_AUX_CLK>; + clock-names =3D "axi_m", + "axi_s", + "axi_bridge", + "rchng", + "ahb", + "aux"; + + resets =3D <&gcc GCC_PCIE0_PIPE_CLK_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_S_CLK_ARES>, + <&gcc GCC_PCIE0_AXI_M_STICKY_RESET>, + <&gcc GCC_PCIE0_AXI_M_CLK_ARES>, + <&gcc GCC_PCIE0_AUX_CLK_ARES>, + <&gcc GCC_PCIE0_AHB_CLK_ARES>; + reset-names =3D "pipe", + "sticky", + "axi_s_sticky", + "axi_s", + "axi_m_sticky", + "axi_m", + "aux", + "ahb"; + + interconnects =3D <&gcc MASTER_ANOC_PCIE0 &gcc SLAVE_ANOC_PCIE0>, + <&gcc MASTER_CNOC_PCIE0 &gcc SLAVE_CNOC_PCIE0>; + interconnect-names =3D "pcie-mem", "cpu-pcie"; + + status =3D "disabled"; + + pcie0_port0: pcie@0 { + compatible =3D "pciclass,0604"; + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + bus-range =3D <0x01 0xff>; + + phys =3D <&pcie0_phy>; + + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges; + }; + }; }; =20 timer { --=20 2.34.1 From nobody Sat Jul 25 20:10:45 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A5AB2DC791 for ; Tue, 14 Jul 2026 04:29:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784003377; cv=none; b=RjHoJxpDSyv2MsbvbEM3NLXn/uo8uWhSNpINP6rlpkhM9bg08cAaJhwM+LqWsIQsxgyj4W7Mut7kcKkGYZkANNFAIKAht/GhnnEXRXqLGBeBg5cWpNAAZjIwx6i/b0MgYxBJLLPuacfEo/BCMqrbu2wQ2EW0UE5fExidX6u129I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784003377; c=relaxed/simple; bh=qBTxNgqvPXIhkW/VgKh1ctAkKcEl9+hhc1jEUBkOmZQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tdi7+11ybbSQaJB3uZLwZHYvvv2DX2ZIZ4qriNTSf+uWrRAKrRiYsnihIfj4jxyL4kAiYej1CQqwm/oRRVvjGtl8fZRWP+dsYXSiZjbgXAebyA7Xz80UVzsGhRbeytj1VMp/a1+nheGJ6eSB6gDWI8KOEQ+qeJitG+wjvIz/gls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=N6uGb7Ky; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=WX9Hnxk/; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="N6uGb7Ky"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="WX9Hnxk/" Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 66E38YTT3417808 for ; Tue, 14 Jul 2026 04:29:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= HFnEH3JcQpHJy4B87D/E5Q6yMrGEkNdhe+JaWg186Oo=; b=N6uGb7KyhCn+X7As R5JokltnNDz+LC/dysV7Ptbz0AM/B4Hlqur7AeyciBN8ClF3Q6nT+9L4YXAWz77A 9MDPs1WDw+TeRSLu7WgP8V+nd3+SrUJbH9tM5kZqgm316q1I3rrrBkSk/y9INjrk pmZodUaeB1asd1Wq32fpUCTncXaJxvCtJAYp/lJVog4L8ivgzvaH/PauqgYwr8jk D9LAEiy0i3XbK30wlhkMse7cFOom2ReBPQcr+pcGtU9PQzI5QwfwLMsoyR07ZdbF scWKB3Pp3HnApOgSGAJwRyXDFj2gr7GNmL1Y8mxq7d74G7pSulHzfk2RsBCnGXAb gneDPg== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4fd44j1y2f-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 14 Jul 2026 04:29:34 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c85798977dcso2957151a12.0 for ; Mon, 13 Jul 2026 21:29:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1784003373; x=1784608173; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=HFnEH3JcQpHJy4B87D/E5Q6yMrGEkNdhe+JaWg186Oo=; b=WX9Hnxk/kgJJpLY4fahoNsF7oKk8Uw1ayPp0X7mnhv/HCOzvUpDpjxFtJO776dAEBa TB4aIhlbsdX6IlHiLL3vdpM1b2qgiHap5vGRb3YLCrMrokgK4zVqBlgimiCc9SNnM1C1 4GxVNx2YYmpkBYGrXOIPckr6ozrxj3+fJ4PxVdbM0T5g81ilIhyKpfp50Zbrpo/kudMI ZzGeu6ZpktFYYBwFo/nzdEwHQsQDlOeYP9GFLnu5+pK0TjVU+HC0cxx+bnuO2unu7rxm 2IrGHhImG2yrYdlBY1zEZpmyvF8tGFenm8QtdxQomB2y52eOgR9SMCWrYAZ1Tv80HbT2 kAqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784003373; x=1784608173; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=HFnEH3JcQpHJy4B87D/E5Q6yMrGEkNdhe+JaWg186Oo=; b=UjiklySdl1oRA/SgJiTCxEEltCzsabU5d3bG9gdaWGbZY9L8Kf6TMiji1xzpbAyOPt aOZFjH4CIdu6ManEQLGaS+MPPX8xZezc9jwaGCjXUfesAySziNhOQ5qotLiLKYCzbruv mIRuhfYcTEMpBctpT5crSNna20j22Wp33kuMi8HHyx75CgDfHRCdIDo+icyYQ0aKfZSF TDRFWQEvG4hQDOyZxdaiKuLwJ6qxZHaE4MPRky3SrT9Gp2wCCf5BFav+OMX8J1dFxeWS pMk7ucSLIjKYe7k3UVx2noXcMtcMM1VtPMSqz2SkQJ4oSsxAfWpyl245rH8U1a15ECqr A07g== X-Forwarded-Encrypted: i=1; AHgh+Rrc9HcPBMz/VUbx3BwhC7ArQ2X3YACDQdNP01bS8ibgKPr90MW0y4Byn775fzvzbdTIMO2rIQYWCgEF1c8=@vger.kernel.org X-Gm-Message-State: AOJu0Yz1cJgdFV5sI45eDgdq/oFFksIMop6/ekkIkURxkvxXtqoneg0J BkLJDOlAa2j69HRwIOBugzklXrk36IT85EWnnX+6Sm+apPhX9gZNlKmvoogeEpiHtaIM6NoM2fV jl2g9oKqeqJlxB+XjYSudZqeyYFfFRuBrVCsej9EUdyu7AxDWMG2uUEybxDzw4Y057do= X-Gm-Gg: AfdE7cnSDv3phgxrPAjXg557VQApHA6i7LUKB0/geCddzZvoFoc6BgdDs3W9KLbfe5Y V2QL3/Q4nSM/CH2HszZ0eOEIGmt9HVvbvASACUd7+dGIiv3vN/xCJoyfmthT+mrxtk8LZHBDmK1 aYoOqRju2kUzOJp/NDPxnHVXRTyPiNZ6sfoOElNzDiEqfvk9aolcu14vRx3KlD55tyvzRdmw4Av gfpXKD/OcaPYk7uOoXLWonXieMfQF12FcBGJcT3hgSBKmF38r+U2kGrQwlyifkOCukmC+6caecl vzb9NR/LXyj4DcWNkcP/PVeJ3or/fMURK3rg6MDwh+JnQTAeh7M3yld4z6jl4cQerWlweSFEKbT xnThG8xhFsX2f0JVOs7P+QVyNDeaeFGa2HmJq/GLri+D9eZpqoKHlaMhcfBg463q7XEvwT/DzTQ RmYyRKeaZskvJKcbv+FusE4VQSAKMTVSKiQrT9f23gRHTYZw== X-Received: by 2002:a05:6300:218c:b0:3bf:6c08:fb82 with SMTP id adf61e73a8af0-3c1109ecd0fmr12883747637.50.1784003373507; Mon, 13 Jul 2026 21:29:33 -0700 (PDT) X-Received: by 2002:a05:6300:218c:b0:3bf:6c08:fb82 with SMTP id adf61e73a8af0-3c1109ecd0fmr12883721637.50.1784003373086; Mon, 13 Jul 2026 21:29:33 -0700 (PDT) Received: from hu-kathirav-blr.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. [103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-313b4cbafa1sm64388999eec.6.2026.07.13.21.29.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 21:29:32 -0700 (PDT) From: Kathiravan Thirumoorthy Date: Tue, 14 Jul 2026 09:59:17 +0530 Subject: [PATCH 2/2] arm64: dts: qcom: ipq9650-rdp488: enable PCIe support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-ipq9650_pcie-v1-2-4197749d06bd@oss.qualcomm.com> References: <20260714-ipq9650_pcie-v1-0-4197749d06bd@oss.qualcomm.com> In-Reply-To: <20260714-ipq9650_pcie-v1-0-4197749d06bd@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Manivannan Sadhasivam X-Mailer: b4 0.15.2 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDA0MyBTYWx0ZWRfX1G7TYR5WUi25 I4oUNOQnfdXexEL74WXnGDdFolAGF0mMzyxDJAp1RErjQCVeTnAdelvfoEyvzZTuXtaK/b7RGUO 4x+jpDosUC8zknD2QR/bS19Fn1MaBhA= X-Authority-Analysis: v=2.4 cv=N4UZ0W9B c=1 sm=1 tr=0 ts=6a55bb2e cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=_o-QRdEJ9KkZi4z5cN8A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: Q2QuFdzVH79Fb1A3RSjs8nIRY_i0_H50 X-Proofpoint-ORIG-GUID: Q2QuFdzVH79Fb1A3RSjs8nIRY_i0_H50 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDA0MyBTYWx0ZWRfX82YvSrlC39Ll Vs7yJGpXsiklrezztZpZd6VAR9kzaJj57iQ1P8Y6U/IMzLSqNefSwhWu72OIf6uGxvBHt5DlwmQ 77h0QtN/oaAIi/GEGZRRCBvxkgx79Mi9HMOtRG8awK/djJSrqf6c1KsrILNum3X2FzeN5+E8S/6 BnAjzaDGBVeGZJimoV5Tjs8pPYsQ4/tyin7CMSksBaJIwqVY+KxWeTxA6kjCnNNsLCTVWoU+yLj Xqyl16LZAGTfDjE4S2NcYduIE8qwgdfENJJCBJnhgOdDsfFqvBZ2KsFsGi++VlgJT8oG1NiBTdh YQdTXAj7zxD6KOJvOuJhOVSigyc/xAnilh5A53FHIr8j8fDdIo+eI8+qO/DeS5waU8lvNxbnBu9 tv0+APEXRGn/g3SDxTPVwYvlsBBBaqZyj228JCmsJD4GSmxY0wA899wNql5pTuNgcmv2v6bgbTi +F1+hIqnArLbccimKYg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_01,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 phishscore=0 priorityscore=1501 suspectscore=0 bulkscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140043 Enable the three dual-lane PCIe controllers supported on RDP488. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 119 ++++++++++++++++++++++++= ++++ 1 file changed, 119 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts b/arch/arm64/boot/= dts/qcom/ipq9650-rdp488.dts index 6871f3dc4eaf..f6411a55c81e 100644 --- a/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts +++ b/arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts @@ -5,6 +5,8 @@ =20 /dts-v1/; =20 +#include + #include "ipq9650.dtsi" =20 / { @@ -20,6 +22,54 @@ chosen { }; }; =20 +&pcie1 { + pinctrl-0 =3D <&pcie1_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie1_phy { + status =3D "okay"; +}; + +&pcie1_port0 { + reset-gpios =3D <&tlmm 28 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 29 GPIO_ACTIVE_LOW>; +}; + +&pcie2 { + pinctrl-0 =3D <&pcie2_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie2_phy { + status =3D "okay"; +}; + +&pcie2_port0 { + reset-gpios =3D <&tlmm 52 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 53 GPIO_ACTIVE_LOW>; +}; + +&pcie3 { + pinctrl-0 =3D <&pcie3_default_state>; + pinctrl-names =3D "default"; + + status =3D "okay"; +}; + +&pcie3_phy { + status =3D "okay"; +}; + +&pcie3_port0 { + reset-gpios =3D <&tlmm 41 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&tlmm 42 GPIO_ACTIVE_LOW>; +}; + &sdhc { max-frequency =3D <192000000>; bus-width =3D <4>; @@ -36,6 +86,75 @@ &sleep_clk { }; =20 &tlmm { + pcie1_default_state: pcie1-default-state { + clkreq-n-pins { + pins =3D "gpio27"; + function =3D "pcie1_clk_req_n"; + drive-strength =3D <8>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio28"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio29"; + function =3D "pcie1_wake"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; + + pcie2_default_state: pcie2-default-state { + clkreq-n-pins { + pins =3D "gpio51"; + function =3D "pcie2_clk_req_n"; + drive-strength =3D <8>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio52"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio53"; + function =3D "pcie2_wake"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; + + pcie3_default_state: pcie3-default-state { + clkreq-n-pins { + pins =3D "gpio40"; + function =3D "pcie3_clk_req_n"; + drive-strength =3D <8>; + bias-pull-up; + }; + + perst-n-pins { + pins =3D "gpio41"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-pull-down; + }; + + wake-n-pins { + pins =3D "gpio42"; + function =3D "pcie3_wake"; + drive-strength =3D <8>; + bias-pull-up; + }; + }; + qup_uart1_default_state: qup-uart1-default-state { pins =3D "gpio43", "gpio44"; function =3D "qup_se6"; --=20 2.34.1