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Tue, 14 Jul 2026 04:10:17 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ccc9d3bc1fsm114514615ad.55.2026.07.14.04.10.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 04:10:17 -0700 (PDT) From: Taniya Das Date: Tue, 14 Jul 2026 16:40:01 +0530 Subject: [PATCH v6] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260714-gpucc_dt_v6-v6-1-16bf5289572d@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIAAgZVmoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyzHQUlJIzE vPSU3UzU4B8JSMDIzMDc0MT3fSC0uTk+JSS+DIzXaM0i0QTAyNjI2MLQyWgjoKi1LTMCrBp0bG 1tQDJ2AJiXQAAAA== X-Change-ID: 20260714-gpucc_dt_v6-2f8a40232381 To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDExNSBTYWx0ZWRfX6YfTMww+O4EJ yl/YJ3mbA3aIKVXJrYrZ0WqCr9xyKtUwfHH+5y2fkWeXrbuONmSInOSQaZOnnm9GwRkhyae0Knm Y2bI02yrX6hITcbRYOOtsmmOuQUi4dI= X-Proofpoint-GUID: nSA_BsnntnJ4A9Blyh5uWa3aXQ1J7H-O X-Proofpoint-ORIG-GUID: nSA_BsnntnJ4A9Blyh5uWa3aXQ1J7H-O X-Authority-Analysis: v=2.4 cv=BZroFLt2 c=1 sm=1 tr=0 ts=6a56191b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=_Kx2gsJmhXA4Nwk0zkQA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDExNSBTYWx0ZWRfX6xqd5EVcGzbl es9vShZmmnO3FdhTb+9u51MUeN1lsM/M0MZ4Xo6Clx76mVgrlEodf54c91uaLdMkugJP4Xzum/Z 7cpi9yplWoTXVRUAbRVGMO5ZWibYFzq5MMPhl8r+EDfIZ+9jgiH/bU4zZa2U8ChgGd1nBaSizdr QOcfBH5RWFztwKk4Vcyk90TGf+hsYaEzR2b7D+4nN1yTINSKhIG1UGWeN6ZXTNrn9KGjOghSwW2 LjHVJ+WsRv4nxaUsq7gNBn4fkAy84LriFIOuzAMRb1VNd7brYpBL7O7xm+wVMyeWmQOD2PVKT40 /nblfuOjZVSCSi+Q5K7QOE3LTftv316S1mbCxKcEoSl8vu2Zwt2d//eVFZNQTaVO/NN/4iqLkVJ nz5J+4MfTavKFMiy5NLdWaBYkSrEVPCGiYIddUTStQPI3vuCEC5hIO9UOKeaJ7XPSRpaxhlAf/V 8O7YEU7MaOBTHGkvJLQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_02,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140115 From: Konrad Dybcio Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this is simply a separate block housing the GX GDSC) nodes, required to power up the graphics-related hardware. Make use of it by enabling the associated IOMMU as well. The GPU itself needs some more work and will be enabled later. Reviewed-by: Abel Vesa Signed-off-by: Konrad Dybcio Co-developed-by: Taniya Das Signed-off-by: Taniya Das --- Support the graphics clock controller for SM8750 for Graphics SW driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. The Graphics GX clock controller is a reuse of the Kaanapali SW driver. The dt-bindings and driver patches from the previous revision were already applied; this revision carries forward only the devicetree change rebased on the linux-next. Changes in v6: - Carry forward only the devicetree patch (rebase on the linux-next); dt-bindings and driver patches were applied from v5. - Link to v5: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-0-78292= b40b053@oss.qualcomm.com Changes in v5: - Update 'fw_name' to index for GPUCC driver [Dmitry]. - Add RB-by [Abel] for code and DT changes. - Link to v4: https://lore.kernel.org/r/20260303-gpucc_sm8750_v2-v4-0-2f285= 62db7c9@oss.qualcomm.com Changes in v4: - Add RB-by [Krzysztof] for GPUCC bindings. - There was a documentation errata update for GPUCC and updated the bindings to capture the MX and CX power-domains and required-opps. - Update the compatible[qcom,sm8750-gxclkctl] in code which was missed in e= arlier patch. - Add the 'use_rpm' for GPUCC. - Update the power-domain/required-opp handles in GPUCC device node. - Link to v3: https://lore.kernel.org/r/20260220-gpucc_sm8750_v2-v3-0-6c540= 8564c3c@oss.qualcomm.com Changes in v3: - SM8750 GX controller is reuse of Kaanapali SW driver, update the bindings. - Remove 'qcom,sm8750-gxcc.yaml' as it reuses the driver. - Cleanup the 'gpucc-sm8750.c' to remove the GX clock controller reference. - Add the corresponding changes in Makefile for gxclkctl-kaanapali.o - Update the device node for GX clock controller. - Link to v2: https://lore.kernel.org/all/20250723-topic-8750_gpucc-v2-0-56= c93b84c390@oss.qualcomm.com/ Changes in v2: - gxcc bindings: remove double colon & list the names for power-domains - Link to v1: https://lore.kernel.org/r/20250708-topic-8750_gpucc-v1-0-86c8= 6a504d47@oss.qualcomm.com --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 68 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 3496f00ac4f5566809252ea0eaeae6cd5c7aac5d..6282730b67e28c6ed05837ec1d8= d2149f9a92537 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -5,10 +5,12 @@ =20 #include #include +#include #include #include #include #include +#include #include #include #include @@ -2180,6 +2182,72 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells =3D <1>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,sm8750-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&rpmhpd RPMHPD_GMXC>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible =3D "qcom,sm8750-gpucc"; + reg =3D <0x0 0x03d90000 0x0 0x9800>; + + clocks =3D <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + power-domains =3D <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_CX>; + required-opps =3D <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + #power-domain-cells =3D <1>; + }; + + adreno_smmu: iommu@3da0000 { + compatible =3D "qcom,sm8750-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg =3D <0x0 0x03da0000 0x0 0x40000>; + #iommu-cells =3D <2>; + #global-interrupts =3D <1>; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + clock-names =3D "hlos"; + power-domains =3D <&gpucc GPU_CC_CX_GDSC>; + dma-coherent; + }; + remoteproc_mpss: remoteproc@4080000 { compatible =3D "qcom,sm8750-mpss-pas"; reg =3D <0x0 0x04080000 0x0 0x10000>; --- base-commit: 49362394dad7df66c274c867a271394c10ca2bb8 change-id: 20260714-gpucc_dt_v6-2f8a40232381 Best regards, --=20 Taniya Das