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Mon, 13 Jul 2026 18:45:57 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 66DIjs0w010050; Mon, 13 Jul 2026 18:45:54 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 4fbewjb42f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jul 2026 18:45:54 +0000 (GMT) Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 66DIjrsX010024; Mon, 13 Jul 2026 18:45:54 GMT Received: from hu-devc-hyd-u22-c.qualcomm.com (hu-pkumpatl-hyd.qualcomm.com [10.147.245.204]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTPS id 66DIjrol010022 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 13 Jul 2026 18:45:53 +0000 (GMT) Received: by hu-devc-hyd-u22-c.qualcomm.com (Postfix, from userid 3914174) id D388563C; Tue, 14 Jul 2026 00:15:51 +0530 (+0530) From: Prasad Kumpatla To: Bjorn Andersson , Bartosz Golaszewski , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liam Girdwood , Mark Brown , Srinivas Kandagatla , Jaroslav Kysela , Takashi Iwai , Prasad Kumpatla Cc: Krzysztof Kozlowski , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sound@vger.kernel.org Subject: [PATCH v2 1/5] pinctrl: qcom: lpass-lpi: make mutex cleanup devm-managed Date: Tue, 14 Jul 2026 00:15:45 +0530 Message-Id: <20260713184549.929569-2-prasad.kumpatla@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713184549.929569-1-prasad.kumpatla@oss.qualcomm.com> References: <20260713184549.929569-1-prasad.kumpatla@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Spam-Info: AW1haW4tMjYwNzEzMDE5NCBTYWx0ZWRfX2JfZwcO8mMB0 aaAoYMMl1dEBetaQjOVaXzqJmhzCCv1PT79MwII1pA4Ua/WXARL9VUdNq9LUu277ayXQ89XA0kh mZGwB0P1ZUaktB2uoXS8B9ChuIJOtOY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzEzMDE5NCBTYWx0ZWRfXxiMj/voqMfFb wZGgLTmW+8BLzC5fOqXyT7pSywN58r2liDRi8ETUbGruKuFBvKVbn2JojxZGjrKLvhjc8LhgGGn H6AoUfcHJX7E5sAbsMd0la/sYmvJIoddc/LSADDn9JZh/ox3HY6kw3GcvpdWkTRkJoVs6inON5i 39j4SF5wbtb1laN62KWmekUCh7SHphQe2VgJn0NmmJnZ9RCogDlkeN8WU7WQCsXJWtNoK+lR+Sa V7pkIshCJqAu0By8ElhawufTuXNRulXkUfafXMiUNR8Fy5TgexYvHQLXdho7di2kCGLlXaZssrh ey8SLWEUyA2HhaJF0+7AgUaS/aeBPH7Ybxi5HaesBweAc3ygEP3xaFNpdj1qMvtUDcwq78arhmP CTv3EU9QJ4xrTB1Aq2e2s/rgk7Xs32o0svjVSO3VCoM0PDV6tpU9dA/3MeiD0ThI4Ess26CxgQl 4r6WefkeCFqbP+VgA3g== X-Proofpoint-ORIG-GUID: Z_JaSbdm9UJJM9_KGelm1gyDW6zu-XTe X-Authority-Analysis: v=2.4 cv=DbcnbPtW c=1 sm=1 tr=0 ts=6a553266 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=KWEuzqUxTflMcmSvMx4A:9 X-Proofpoint-GUID: Z_JaSbdm9UJJM9_KGelm1gyDW6zu-XTe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-13_04,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 phishscore=0 suspectscore=0 bulkscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607130194 Content-Type: text/plain; charset="utf-8" The driver registers its pin controller using devm_pinctrl_register(), which keeps the pinctrl device alive until devres teardown, after .remove() returns. Explicitly destroying pctrl->lock in .remove() and the probe error path leaves the mutex destroyed while the pinctrl device is still accessible, risking a panic on concurrent debugfs access during unbind. Switch to devm_mutex_init() so the mutex lifetime is automatically aligned with the devm-managed pinctrl device, and remove now redundant mutex_destroy() calls and err_pinctrl label. Signed-off-by: Prasad Kumpatla --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 5fd4a4eba..b3e365470 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -559,31 +559,25 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->chip.label =3D dev_name(dev); pctrl->chip.can_sleep =3D true; =20 - mutex_init(&pctrl->lock); + ret =3D devm_mutex_init(&pdev->dev, &pctrl->lock); + if (ret) + return ret; =20 pctrl->ctrl =3D devm_pinctrl_register(dev, &pctrl->desc, pctrl); - if (IS_ERR(pctrl->ctrl)) { - ret =3D PTR_ERR(pctrl->ctrl); - dev_err(dev, "failed to add pin controller\n"); - goto err_pinctrl; - } + if (IS_ERR(pctrl->ctrl)) + return PTR_ERR(pctrl->ctrl); =20 ret =3D lpi_build_pin_desc_groups(pctrl); if (ret) - goto err_pinctrl; + return ret; =20 ret =3D devm_gpiochip_add_data(dev, &pctrl->chip, pctrl); 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charset="utf-8" Add a new clock ID, LPASS_HW_LPR_VOTE, to represent the LPASS low-power resource (LPR) vote through the PRM interface. The LPASS PRM supports a resource voting mechanism to control low-power states via PARAM_ID_RSC_CPU_LPR. Exposing this as a q6prm clock ID allows clients to request the LPR vote using the existing qcom,q6prm clock provider interface. This functionality is required on newer platforms (e.g. Hawi) where LPASS clients need to explicitly manage LPR resource voting via PRM. Also update Q6AFE_MAX_CLK_ID to account for the newly added clock ID. Reviewed-by: Bartosz Golaszewski Signed-off-by: Prasad Kumpatla --- include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h b/include/d= t-bindings/sound/qcom,q6dsp-lpass-ports.h index 45850f2d4..06ca2c287 100644 --- a/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h +++ b/include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h @@ -236,8 +236,9 @@ #define LPASS_HW_AVTIMER_VOTE 101 #define LPASS_HW_MACRO_VOTE 102 #define LPASS_HW_DCODEC_VOTE 103 +#define LPASS_HW_LPR_VOTE 104 =20 -#define Q6AFE_MAX_CLK_ID 104 +#define Q6AFE_MAX_CLK_ID 105 =20 #define LPASS_CLK_ATTRIBUTE_INVALID 0x0 #define LPASS_CLK_ATTRIBUTE_COUPLE_NO 0x1 --=20 2.34.1 From nobody Sat Jul 25 20:47:08 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A29943546C2; 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charset="utf-8" Add support for issuing LPASS low-power resource (LPR) votes through the PRM interface. Some platforms (e.g. Hawi) require the LPASS to be kept active via LPR resource voting instead of the existing hardware core vote mechanism. Handle this by introducing support for PARAM_ID_RSC_CPU_LPR when the LPR vote clock ID is requested. For LPR requests, use the appropriate parameter ID and payload format to disable CPU subsystem sleep, ensuring that the LPASS register space remains accessible. Also add the corresponding clock mapping for LPASS_HW_LPR_VOTE and make the q6dsp clock ID range consistent with the dt-bindings by deriving it from Q6AFE_MAX_CLK_ID. Signed-off-by: Prasad Kumpatla --- sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c | 2 +- sound/soc/qcom/qdsp6/q6prm-clocks.c | 2 ++ sound/soc/qcom/qdsp6/q6prm.c | 17 +++++++++++++---- sound/soc/qcom/qdsp6/q6prm.h | 1 + 4 files changed, 17 insertions(+), 5 deletions(-) diff --git a/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c b/sound/soc/qcom/qds= p6/q6dsp-lpass-clocks.c index 03838582a..79527a367 100644 --- a/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c +++ b/sound/soc/qcom/qdsp6/q6dsp-lpass-clocks.c @@ -12,7 +12,7 @@ #include #include "q6dsp-lpass-clocks.h" =20 -#define Q6DSP_MAX_CLK_ID 104 +#define Q6DSP_MAX_CLK_ID Q6AFE_MAX_CLK_ID #define Q6DSP_LPASS_CLK_ROOT_DEFAULT 0 =20 =20 diff --git a/sound/soc/qcom/qdsp6/q6prm-clocks.c b/sound/soc/qcom/qdsp6/q6p= rm-clocks.c index 4c574b48a..2b2b3872e 100644 --- a/sound/soc/qcom/qdsp6/q6prm-clocks.c +++ b/sound/soc/qcom/qdsp6/q6prm-clocks.c @@ -63,6 +63,8 @@ static const struct q6dsp_clk_init q6prm_clks[] =3D { "LPASS_HW_MACRO"), Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC, "LPASS_HW_DCODEC"), + Q6DSP_VOTE_CLK(LPASS_HW_LPR_VOTE, Q6PRM_HW_LPR_VOTE, + "LPASS_HW_LPR_VOTE"), }; =20 static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused =3D { diff --git a/sound/soc/qcom/qdsp6/q6prm.c b/sound/soc/qcom/qdsp6/q6prm.c index 04892fb44..7a7a1d3d5 100644 --- a/sound/soc/qcom/qdsp6/q6prm.c +++ b/sound/soc/qcom/qdsp6/q6prm.c @@ -31,10 +31,16 @@ struct q6prm { #define PARAM_ID_RSC_HW_CORE 0x08001032 #define PARAM_ID_RSC_LPASS_CORE 0x0800102B #define PARAM_ID_RSC_AUDIO_HW_CLK 0x0800102C +#define PARAM_ID_RSC_CPU_LPR 0x08001A6E + +#define LPR_CPU_SS_SLEEP_DISABLED 0x1 =20 struct prm_cmd_request_hw_core { struct apm_module_param_data param_data; - uint32_t hw_clk_id; + union { + u32 hw_clk_id; + u32 lpr_state; + }; } __packed; =20 struct prm_cmd_request_rsc { @@ -62,6 +68,7 @@ static int q6prm_set_hw_core_req(struct device *dev, uint= 32_t hw_block_id, bool struct prm_cmd_request_hw_core *req; gpr_device_t *gdev =3D prm->gdev; uint32_t opcode, rsp_opcode; + bool lpr_req =3D (hw_block_id =3D=3D Q6PRM_HW_LPR_VOTE); =20 if (enable) { opcode =3D PRM_CMD_REQUEST_HW_RSC; @@ -82,10 +89,13 @@ static int q6prm_set_hw_core_req(struct device *dev, ui= nt32_t hw_block_id, bool =20 param_data->module_instance_id =3D GPR_PRM_MODULE_IID; param_data->error_code =3D 0; - param_data->param_id =3D PARAM_ID_RSC_HW_CORE; + param_data->param_id =3D lpr_req ? PARAM_ID_RSC_CPU_LPR : PARAM_ID_RSC_HW= _CORE; param_data->param_size =3D sizeof(*req) - APM_MODULE_PARAM_DATA_SIZE; =20 - req->hw_clk_id =3D hw_block_id; + if (lpr_req) + req->lpr_state =3D LPR_CPU_SS_SLEEP_DISABLED; + else + req->hw_clk_id =3D hw_block_id; =20 return q6prm_send_cmd_sync(prm, pkt, rsp_opcode); } @@ -94,7 +104,6 @@ int q6prm_vote_lpass_core_hw(struct device *dev, uint32_= t hw_block_id, const char *client_name, uint32_t *client_handle) { return q6prm_set_hw_core_req(dev, hw_block_id, true); - } EXPORT_SYMBOL_GPL(q6prm_vote_lpass_core_hw); =20 diff --git a/sound/soc/qcom/qdsp6/q6prm.h b/sound/soc/qcom/qdsp6/q6prm.h index a988a3208..bd5ee0c40 100644 --- a/sound/soc/qcom/qdsp6/q6prm.h +++ b/sound/soc/qcom/qdsp6/q6prm.h @@ -87,6 +87,7 @@ #define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0 #define Q6PRM_HW_CORE_ID_LPASS 1 #define Q6PRM_HW_CORE_ID_DCODEC 2 +#define Q6PRM_HW_LPR_VOTE 3 =20 int q6prm_set_lpass_clock(struct device *dev, int clk_id, int clk_attr, int clk_root, unsigned int freq); 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charset="utf-8" Add bindings for the pin controller in Low Power Audio SubSystem (LPASS) of Qualcomm Hawi SoC. The controller has 23 GPIOs (gpio0-gpio22) with functions including SoundWire, I2S, DMIC, VA I2S, ext_mclk1, slimbus and lpass_lpi_dbg_clk. Signed-off-by: Prasad Kumpatla --- .../pinctrl/qcom,hawi-lpass-lpi-pinctrl.yaml | 109 ++++++++++++++++++ 1 file changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpa= ss-lpi-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-= pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lp= i-pinctrl.yaml new file mode 100644 index 000000000..af6858175 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,hawi-lpass-lpi-pinctrl= .yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-lpass-lpi-pinctrl.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hawi SoC LPASS LPI TLMM + +maintainers: + - Krzysztof Kozlowski + - Srinivas Kandagatla + - Prasad Kumpatla + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. + +properties: + compatible: + const: qcom,hawi-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + + clocks: + items: + - description: LPASS LPR(Low Power Resource) voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: lpr + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-hawi-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-hawi-lpass-state" + additionalProperties: false + +$defs: + qcom-hawi-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-2])$" + + function: + enum: [dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b, + ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk, + i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, + lpass_lpi_dbg_clk, qca_swr_clk, qca_swr_data, slimbus_clk, + slimbus_data, swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_c= lk1, + swr_tx_data, va_i2s0_clk, va_i2s0_data, va_i2s0_ws, + wsa2_swr_clk, wsa2_swr_data, wsa_swr_clk, wsa_swr_data] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@7f60000 { + compatible =3D "qcom,hawi-lpass-lpi-pinctrl"; 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charset="utf-8" Add pin controller driver for the Low Power Audio SubSystem (LPASS) Low Power Island (LPI) of Qualcomm Hawi SoC. The controller has 23 GPIOs with SoundWire, I2S, DMIC, VA I2S, ext_mclk1 and slimbus mux functions. Two pins (gpio13, gpio22) require 6 mux slots due to a test_bus entry occupying a middle hardware slot. Add LPI_PINGROUP6 macro to pinctrl-lpass-lpi.h to support pins with 5 alternate functions. Reviewed-by: Konrad Dybcio Signed-off-by: Prasad Kumpatla --- drivers/pinctrl/qcom/Kconfig | 10 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c | 244 ++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 17 ++ 4 files changed, 272 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 18db35022..707067b92 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -62,6 +62,16 @@ config PINCTRL_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SoCs. =20 +config PINCTRL_HAWI_LPASS_LPI + tristate "Qualcomm Technologies Inc Hawi LPASS LPI pin controller driver" + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc Hawi + platform. + config PINCTRL_MILOS_LPASS_LPI tristate "Qualcomm Milos LPASS LPI pin controller driver" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 43ecd246a..987a79f9d 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_PINCTRL_APQ8084) +=3D pinctrl-apq8084.o obj-$(CONFIG_PINCTRL_ELIZA) +=3D pinctrl-eliza.o obj-$(CONFIG_PINCTRL_GLYMUR) +=3D pinctrl-glymur.o obj-$(CONFIG_PINCTRL_HAWI) +=3D pinctrl-hawi.o +obj-$(CONFIG_PINCTRL_HAWI_LPASS_LPI) +=3D pinctrl-hawi-lpass-lpi.o obj-$(CONFIG_PINCTRL_IPQ4019) +=3D pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ5018) +=3D pinctrl-ipq5018.o obj-$(CONFIG_PINCTRL_IPQ8064) +=3D pinctrl-ipq8064.o diff --git a/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c b/drivers/pinctr= l/qcom/pinctrl-hawi-lpass-lpi.c new file mode 100644 index 000000000..7036bf4c6 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-hawi-lpass-lpi.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_dmic1_clk, + LPI_MUX_dmic1_data, + LPI_MUX_dmic2_clk, + LPI_MUX_dmic2_data, + LPI_MUX_dmic3_clk, + LPI_MUX_dmic3_data, + LPI_MUX_dmic4_clk, + LPI_MUX_dmic4_data, + LPI_MUX_ext_mclk1_a, + LPI_MUX_ext_mclk1_b, + LPI_MUX_ext_mclk1_c, + LPI_MUX_ext_mclk1_d, + LPI_MUX_ext_mclk1_e, + LPI_MUX_i2s0_clk, + LPI_MUX_i2s0_data, + LPI_MUX_i2s0_ws, + LPI_MUX_i2s1_clk, + LPI_MUX_i2s1_data, + LPI_MUX_i2s1_ws, + LPI_MUX_i2s2_clk, + LPI_MUX_i2s2_data, + LPI_MUX_i2s2_ws, + LPI_MUX_i2s3_clk, + LPI_MUX_i2s3_data, + LPI_MUX_i2s3_ws, + LPI_MUX_lpass_lpi_dbg_clk, + LPI_MUX_qca_swr_clk, + LPI_MUX_qca_swr_data, + LPI_MUX_slimbus_clk, + LPI_MUX_slimbus_data, + LPI_MUX_swr_rx_clk, + LPI_MUX_swr_rx_data, + LPI_MUX_swr_tx_clk, + LPI_MUX_swr_tx_clk1, + LPI_MUX_swr_tx_data, + LPI_MUX_va_i2s0_clk, + LPI_MUX_va_i2s0_data, + LPI_MUX_va_i2s0_ws, + LPI_MUX_wsa2_swr_clk, + LPI_MUX_wsa2_swr_data, + LPI_MUX_wsa_swr_clk, + LPI_MUX_wsa_swr_data, + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const struct pinctrl_pin_desc hawi_lpi_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", +}; + +static const char * const swr_tx_clk_groups[] =3D { "gpio0" }; +static const char * const i2s0_clk_groups[] =3D { "gpio0" }; +static const char * const swr_tx_data_groups[] =3D { "gpio1", "gpio2", "gp= io14" }; +static const char * const i2s0_ws_groups[] =3D { "gpio1" }; +static const char * const swr_rx_clk_groups[] =3D { "gpio3" }; +static const char * const i2s0_data_groups[] =3D { "gpio2", "gpio3", "gpio= 4", "gpio5" }; +static const char * const swr_rx_data_groups[] =3D { "gpio4", "gpio5" }; +static const char * const ext_mclk1_c_groups[] =3D { "gpio5" }; +static const char * const dmic1_clk_groups[] =3D { "gpio6" }; +static const char * const va_i2s0_clk_groups[] =3D { "gpio6" }; +static const char * const dmic1_data_groups[] =3D { "gpio7" }; +static const char * const va_i2s0_ws_groups[] =3D { "gpio7" }; +static const char * const dmic2_clk_groups[] =3D { "gpio8" }; +static const char * const va_i2s0_data_groups[] =3D { "gpio8", "gpio9" }; +static const char * const dmic2_data_groups[] =3D { "gpio9" }; +static const char * const ext_mclk1_b_groups[] =3D { "gpio9" }; +static const char * const i2s1_clk_groups[] =3D { "gpio10" }; +static const char * const wsa_swr_clk_groups[] =3D { "gpio10" }; +static const char * const i2s1_ws_groups[] =3D { "gpio11" }; +static const char * const wsa_swr_data_groups[] =3D { "gpio11", "gpio21" }; +static const char * const dmic3_clk_groups[] =3D { "gpio12" }; +static const char * const i2s3_clk_groups[] =3D { "gpio12" }; +static const char * const dmic3_data_groups[] =3D { "gpio13" }; +static const char * const i2s3_ws_groups[] =3D { "gpio13" }; +static const char * const ext_mclk1_a_groups[] =3D { "gpio13" }; +static const char * const lpass_lpi_dbg_clk_groups[] =3D { "gpio13" }; +static const char * const swr_tx_clk1_groups[] =3D { "gpio14" }; +static const char * const ext_mclk1_d_groups[] =3D { "gpio14" }; +static const char * const i2s1_data_groups[] =3D { "gpio15", "gpio16", "gp= io21", "gpio22" }; +static const char * const wsa2_swr_clk_groups[] =3D { "gpio15" }; +static const char * const wsa2_swr_data_groups[] =3D { "gpio16", "gpio22" = }; +static const char * const dmic4_clk_groups[] =3D { "gpio17" }; +static const char * const i2s3_data_groups[] =3D { "gpio17", "gpio18" }; +static const char * const dmic4_data_groups[] =3D { "gpio18" }; +static const char * const i2s2_clk_groups[] =3D { "gpio19" }; +static const char * const slimbus_clk_groups[] =3D { "gpio19" }; +static const char * const qca_swr_clk_groups[] =3D { "gpio19" }; +static const char * const i2s2_ws_groups[] =3D { "gpio20" }; +static const char * const slimbus_data_groups[] =3D { "gpio20" }; +static const char * const qca_swr_data_groups[] =3D { "gpio20" }; +static const char * const i2s2_data_groups[] =3D { "gpio21", "gpio22" }; +static const char * const ext_mclk1_e_groups[] =3D { "gpio22" }; + +static const struct lpi_pingroup hawi_groups[] =3D { + LPI_PINGROUP(0, 11, swr_tx_clk, i2s0_clk, _, _), + LPI_PINGROUP(1, 11, swr_tx_data, i2s0_ws, _, _), + LPI_PINGROUP(2, 11, swr_tx_data, i2s0_data, _, _), + LPI_PINGROUP(3, 11, swr_rx_clk, i2s0_data, _, _), + LPI_PINGROUP(4, 11, swr_rx_data, i2s0_data, _, _), + LPI_PINGROUP(5, 11, swr_rx_data, ext_mclk1_c, i2s0_data, _), + LPI_PINGROUP(6, LPI_NO_SLEW, dmic1_clk, va_i2s0_clk, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, dmic1_data, va_i2s0_ws, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, dmic2_clk, va_i2s0_data, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, dmic2_data, va_i2s0_data, ext_mclk1_b, _), + LPI_PINGROUP(10, 11, i2s1_clk, wsa_swr_clk, _, _), + LPI_PINGROUP(11, 11, i2s1_ws, wsa_swr_data, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, dmic3_clk, i2s3_clk, _, _), + LPI_PINGROUP6(13, LPI_NO_SLEW, dmic3_data, i2s3_ws, ext_mclk1_a, _, lpass= _lpi_dbg_clk), + LPI_PINGROUP(14, 11, swr_tx_data, swr_tx_clk1, ext_mclk1_d, _), + LPI_PINGROUP(15, 11, i2s1_data, wsa2_swr_clk, _, _), + LPI_PINGROUP(16, 11, i2s1_data, wsa2_swr_data, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, dmic4_clk, i2s3_data, _, _), + LPI_PINGROUP(18, LPI_NO_SLEW, dmic4_data, i2s3_data, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, i2s2_clk, slimbus_clk, qca_swr_clk, _), + LPI_PINGROUP(20, LPI_NO_SLEW, i2s2_ws, slimbus_data, qca_swr_data, _), + LPI_PINGROUP(21, 11, i2s2_data, _, wsa_swr_data, i2s1_data), + LPI_PINGROUP6(22, 11, i2s2_data, ext_mclk1_e, _, i2s1_data, wsa2_swr_data= ), +}; + +static const struct lpi_function hawi_functions[] =3D { + LPI_FUNCTION(gpio), + LPI_FUNCTION(dmic1_clk), + LPI_FUNCTION(dmic1_data), + LPI_FUNCTION(dmic2_clk), + LPI_FUNCTION(dmic2_data), + LPI_FUNCTION(dmic3_clk), + LPI_FUNCTION(dmic3_data), + LPI_FUNCTION(dmic4_clk), + LPI_FUNCTION(dmic4_data), + LPI_FUNCTION(ext_mclk1_a), + LPI_FUNCTION(ext_mclk1_b), + LPI_FUNCTION(ext_mclk1_c), + LPI_FUNCTION(ext_mclk1_d), + LPI_FUNCTION(ext_mclk1_e), + LPI_FUNCTION(i2s0_clk), + LPI_FUNCTION(i2s0_data), + LPI_FUNCTION(i2s0_ws), + LPI_FUNCTION(i2s1_clk), + LPI_FUNCTION(i2s1_data), + LPI_FUNCTION(i2s1_ws), + LPI_FUNCTION(i2s2_clk), + LPI_FUNCTION(i2s2_data), + LPI_FUNCTION(i2s2_ws), + LPI_FUNCTION(i2s3_clk), + LPI_FUNCTION(i2s3_data), + LPI_FUNCTION(i2s3_ws), + LPI_FUNCTION(lpass_lpi_dbg_clk), + LPI_FUNCTION(qca_swr_clk), + LPI_FUNCTION(qca_swr_data), + LPI_FUNCTION(slimbus_clk), + LPI_FUNCTION(slimbus_data), + LPI_FUNCTION(swr_rx_clk), + LPI_FUNCTION(swr_rx_data), + LPI_FUNCTION(swr_tx_clk), + LPI_FUNCTION(swr_tx_clk1), + LPI_FUNCTION(swr_tx_data), + LPI_FUNCTION(va_i2s0_clk), + LPI_FUNCTION(va_i2s0_data), + LPI_FUNCTION(va_i2s0_ws), + LPI_FUNCTION(wsa2_swr_clk), + LPI_FUNCTION(wsa2_swr_data), + LPI_FUNCTION(wsa_swr_clk), + LPI_FUNCTION(wsa_swr_data), +}; + +static const struct lpi_pinctrl_variant_data hawi_lpi_data =3D { + .pins =3D hawi_lpi_pins, + .npins =3D ARRAY_SIZE(hawi_lpi_pins), + .groups =3D hawi_groups, + .ngroups =3D ARRAY_SIZE(hawi_groups), + .functions =3D hawi_functions, + .nfunctions =3D ARRAY_SIZE(hawi_functions), + .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG, +}; + +static const struct of_device_id lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,hawi-lpass-lpi-pinctrl", + .data =3D &hawi_lpi_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); + +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + +static struct platform_driver lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-hawi-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; + +module_platform_driver(lpi_pinctrl_driver); +MODULE_DESCRIPTION("Qualcomm Hawi LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index 6ba0c4eba..056c4a774 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -92,6 +92,23 @@ struct pinctrl_pin_desc; .pin_offset =3D 0, \ } =20 +#define LPI_PINGROUP6(id, soff, f1, f2, f3, f4, f5) \ + { \ + .pin =3D id, \ + .slew_offset =3D soff, \ + .slew_base_spare_1 =3D false, \ + .funcs =3D (int[]){ \ + LPI_MUX_gpio, \ + LPI_MUX_##f1, \ + LPI_MUX_##f2, \ + LPI_MUX_##f3, \ + LPI_MUX_##f4, \ + LPI_MUX_##f5, \ + }, \ + .nfuncs =3D 6, \ + .pin_offset =3D 0, \ + } + /* * Slew rate control is done in the same register as rest of the * pin configuration. --=20 2.34.1