From nobody Sat Jul 25 21:30:55 2026 Received: from canpmsgout09.his.huawei.com (canpmsgout09.his.huawei.com [113.46.200.224]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B2F137756A for ; Mon, 13 Jul 2026 12:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.224 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783947424; cv=none; b=Au1yuqICmbu55RMTq5ezOpqJk6mwvr4d+Qol6Nqgs6fclvdV/CgoCyl2D2H58jSdYIpqIzmaZceYX8xGImxKW+KFeqrSuBALFosgXpu6soDFP5OjIvU713BGQ4L+ybQzr5ijuT4I10zm058cRLqPt7Xm45Kh/CBtdx8WlxcNhHY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783947424; c=relaxed/simple; bh=34goFnNhpKVUmaiOHNLU0shYu9Hnsf8oI0Sl5ZIC45M=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=n/H5xdzRwpM2gdy2+s083dcJmB4fTc+N+oqAAzTff6dnMbgvabGYe705u5uM235SiusyI8XR7t/4HG4DzFlWrGKcafFjJR+HlNH5B106nS/tiz0MXUNWlAcgcwtDMsBadczbv98WA3ZcKKEGboX/wvHbLFKjSMuQB5L3nwMLVl8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=YQlGWrfX; arc=none smtp.client-ip=113.46.200.224 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="YQlGWrfX" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=eSP4O6kYtGfne8Il/CjCmuoq3nF1N/Q9qqIaTB7+HLI=; b=YQlGWrfXFUOHn81hpPFkc4HHysVzJjiWcy+v0P+jCV522D1ZBLBb+6Ijjz5vr8d9KRi6nZgXa MfVO2t0Si5OhucdXOEbMxhvF+fAACHb5R/uDzqZf0AQrgAEUWj7/EB5dka+kge3+7HoriXQZvxL ylMxf3YuzZHH8Ost05Qx8Rg= Received: from mail.maildlp.com (unknown [172.19.163.214]) by canpmsgout09.his.huawei.com (SkyGuard) with ESMTPS id 4gzMfH3K5Yz1cyPY; Mon, 13 Jul 2026 20:47:35 +0800 (CST) Received: from whupemo500002.china.huawei.com (unknown [7.152.185.250]) by mail.maildlp.com (Postfix) with ESMTPS id 384244057C; Mon, 13 Jul 2026 20:56:51 +0800 (CST) Received: from localhost.huawei.com (10.90.31.46) by whupemo500002.china.huawei.com (7.152.185.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 13 Jul 2026 20:56:50 +0800 From: Yushan Wang To: , , , , CC: , , , , , Subject: [PATCH v3 1/2] drivers/perf: hisi: Support uncore ITS PMU Date: Mon, 13 Jul 2026 20:56:46 +0800 Message-ID: <20260713125647.2958626-2-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260713125647.2958626-1-wangyushan12@huawei.com> References: <20260713125647.2958626-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To whupemo500002.china.huawei.com (7.152.185.250) Content-Type: text/plain; charset="utf-8" Support uncore ITS PMU, which provides the capability of counting the number of interrupts routed to ITS by interrupt catagories, and the latency. It also supports collecting statistics of micro-ops of ITS. The driver adapts to HiSilicon uncore PMU framework. It does not support overflow interruption, which is the same as NoC PMU, so a few dummy functions or handling interrupts are left empty. Signed-off-by: Yushan Wang --- Documentation/admin-guide/perf/hisi-pmu.rst | 13 + drivers/perf/hisilicon/Makefile | 2 +- drivers/perf/hisilicon/hisi_uncore_its_pmu.c | 393 +++++++++++++++++++ 3 files changed, 407 insertions(+), 1 deletion(-) create mode 100644 drivers/perf/hisilicon/hisi_uncore_its_pmu.c diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/ad= min-guide/perf/hisi-pmu.rst index d56b2d690709..278bd7e0ae60 100644 --- a/Documentation/admin-guide/perf/hisi-pmu.rst +++ b/Documentation/admin-guide/perf/hisi-pmu.rst @@ -128,6 +128,19 @@ channel with this option. The current supported channe= ls are as follows: 7. tt_en: NoC PMU supports counting only transactions that have tracetag s= et if this option is set. See the 2nd list for more information about traceta= g. =20 +8. int_id: ITS PMU supports filtering by interrupt id, which is defined by +hardware. Interrupt id takes up to 32 bits, and can be divided into 2 part= s: + +- Upper 16 bits: DeviceID if counting LPI, PEID if counting SGI/PPI. +- Lower 16 bits: EventID if counting LPI, IntID if counting SGI/PPI. + +int_id is a global configuration for each PMU instance. If multiple differ= ent +int_id's are specified, the last came in will be effective. And if there a= re +already filtered events running, new filtered events came in will be refus= ed. + +9. int_en: A one-bit flag to tell if int_id is used to filter the statisti= cs. It +allows filtering 0 DeviceID and EventID. + For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are further divided into parts for finer granularity of tracing, each part has= its own dedicated PMU, and all such PMUs together cover the monitoring job of = events diff --git a/drivers/perf/hisilicon/Makefile b/drivers/perf/hisilicon/Makef= ile index 186be3d02238..5f28cfdb8a72 100644 --- a/drivers/perf/hisilicon/Makefile +++ b/drivers/perf/hisilicon/Makefile @@ -2,7 +2,7 @@ obj-$(CONFIG_HISI_PMU) +=3D hisi_uncore_pmu.o hisi_uncore_l3c_pmu.o \ hisi_uncore_hha_pmu.o hisi_uncore_ddrc_pmu.o hisi_uncore_sllc_pmu.o \ hisi_uncore_pa_pmu.o hisi_uncore_cpa_pmu.o hisi_uncore_uc_pmu.o \ - hisi_uncore_noc_pmu.o hisi_uncore_mn_pmu.o + hisi_uncore_noc_pmu.o hisi_uncore_mn_pmu.o hisi_uncore_its_pmu.o =20 obj-$(CONFIG_HISI_PCIE_PMU) +=3D hisi_pcie_pmu.o obj-$(CONFIG_HNS3_PMU) +=3D hns3_pmu.o diff --git a/drivers/perf/hisilicon/hisi_uncore_its_pmu.c b/drivers/perf/hi= silicon/hisi_uncore_its_pmu.c new file mode 100644 index 000000000000..430e2b06cf4d --- /dev/null +++ b/drivers/perf/hisilicon/hisi_uncore_its_pmu.c @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for HiSilicon Uncore ITS PMU device + * + * Copyright (c) 2026 HiSilicon Technologies Co., Ltd. + * Author: Yushan Wang + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hisi_uncore_pmu.h" + +#define ITS_PMU_VERSION 0x21000 +#define ITS_PMU_GLOBAL_CTRL 0x21004 +#define ITS_PMU_GLOBAL_CTRL_PMU_EN BIT(0) +#define ITS_PMU_COUNTER_CTRL 0x21008 +#define ITS_PMU_EVENT_CTRL 0x2100c +#define ITS_PMU_COUNTER0 0x21010 + +#define ITS_PMU_INT_ID_MASK 0x20008 +#define ITS_PMU_INT_ID_CTRL 0x20084 + +#define ITS_PMU_NR_COUNTERS 4 + +#define ITS_PMU_EVENT_CNTRn(cntr0, n) ((cntr0) + 8 * (n)) +#define ITS_PMU_CNTR_CTRL_MASK(n) GENMASK(8 * ((n) + 1) - 1, 8 * (n)) +#define ITS_PMU_CNTR_EVENT_CFG(n, e) ((e) << ((n) * 8)) +#define ITS_PMU_EVENT_CTRL_TYPE GENMASK(12, 0) + +HISI_PMU_EVENT_ATTR_EXTRACTOR(int_id, config1, 31, 0); +HISI_PMU_EVENT_ATTR_EXTRACTOR(int_en, config1, 32, 32); + +/* Dynamic CPU hotplug state used by this PMU driver */ +static enum cpuhp_state hisi_its_pmu_cpuhp_state; + +struct hisi_its_pmu_regs { + u32 version; + u32 pmu_ctrl; + u32 event_ctrl0; + u32 event_cntr0; + u32 cntr_ctrl; +}; + +struct hisi_its_pmu { + struct hisi_pmu pmu; + atomic_t filter_user; +}; + +static void hisi_its_pmu_write_evtype(struct hisi_pmu *pmu, int idx, u32 t= ype) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + u32 reg; + + reg =3D readl(pmu->base + reg_info->event_ctrl0); + reg &=3D ~ITS_PMU_CNTR_CTRL_MASK(idx); + reg |=3D ITS_PMU_CNTR_EVENT_CFG(idx, type); + writel(reg, pmu->base + reg_info->event_ctrl0); +} + +static u64 hisi_its_pmu_read_counter(struct hisi_pmu *pmu, + struct hw_perf_event *hwc) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + + return readq(pmu->base + ITS_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->= idx)); +} + +static void hisi_its_pmu_write_counter(struct hisi_pmu *pmu, + struct hw_perf_event *hwc, u64 val) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + + writeq(val, pmu->base + ITS_PMU_EVENT_CNTRn(reg_info->event_cntr0, hwc->i= dx)); +} + +static void hisi_its_pmu_enable_counter(struct hisi_pmu *pmu, + struct hw_perf_event *hwc) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + u32 reg; + + reg =3D readl(pmu->base + reg_info->cntr_ctrl); + reg |=3D BIT(hwc->idx); + writel(reg, pmu->base + reg_info->cntr_ctrl); +} + +static void hisi_its_pmu_disable_counter(struct hisi_pmu *pmu, + struct hw_perf_event *hwc) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + u32 reg; + + reg =3D readl(pmu->base + reg_info->cntr_ctrl); + reg &=3D ~BIT(hwc->idx); + writel(reg, pmu->base + reg_info->cntr_ctrl); +} + +static void hisi_its_pmu_enable_counter_int(struct hisi_pmu *pmu, + struct hw_perf_event *hwc) +{ + /* We don't support interrupt, so a stub here. */ +} + +static void hisi_its_pmu_disable_counter_int(struct hisi_pmu *pmu, + struct hw_perf_event *hwc) +{ +} + +static void hisi_its_pmu_start_counters(struct hisi_pmu *pmu) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + u32 reg; + + reg =3D readl(pmu->base + reg_info->pmu_ctrl); + reg |=3D ITS_PMU_GLOBAL_CTRL_PMU_EN; + writel(reg, pmu->base + reg_info->pmu_ctrl); +} + +static void hisi_its_pmu_stop_counters(struct hisi_pmu *pmu) +{ + struct hisi_its_pmu_regs *reg_info =3D pmu->dev_info->private; + u32 reg; + + reg =3D readl(pmu->base + reg_info->pmu_ctrl); + reg &=3D ~ITS_PMU_GLOBAL_CTRL_PMU_EN; + writel(reg, pmu->base + reg_info->pmu_ctrl); +} + +static void hisi_its_pmu_enable_filter(struct perf_event *event) +{ + struct hisi_pmu *pmu =3D to_hisi_pmu(event->pmu); + struct hisi_its_pmu *its_pmu =3D container_of(pmu, struct hisi_its_pmu, p= mu); + u32 int_id =3D hisi_get_int_id(event); + u32 int_en =3D hisi_get_int_en(event); + + if (int_en) { + writel(int_id, pmu->base + ITS_PMU_INT_ID_CTRL); + /* Write 0 to this register to enable filtering with int_id. */ + writel(0, pmu->base + ITS_PMU_INT_ID_MASK); + atomic_inc(&its_pmu->filter_user); + } +} + +static void hisi_its_pmu_disable_filter(struct perf_event *event) +{ + struct hisi_pmu *pmu =3D to_hisi_pmu(event->pmu); + struct hisi_its_pmu *its_pmu =3D container_of(pmu, struct hisi_its_pmu, p= mu); + + /* Don't touch global filtering config if this is not the last counter. */ + if (bitmap_weight(pmu->pmu_events.used_mask, pmu->num_counters) > 1) + return; + + if (atomic_read(&its_pmu->filter_user)) { + writel(0, pmu->base + ITS_PMU_INT_ID_CTRL); + writel(-1U, pmu->base + ITS_PMU_INT_ID_MASK); + atomic_dec(&its_pmu->filter_user); + } +} + +static int hisi_its_pmu_check_filter(struct perf_event *event) +{ + struct hisi_pmu *pmu =3D to_hisi_pmu(event->pmu); + struct hisi_its_pmu *its_pmu =3D container_of(pmu, struct hisi_its_pmu, p= mu); + u32 int_en =3D hisi_get_int_en(event); + + /* Refuse filtered event if there's already filtered one running. */ + return atomic_read(&its_pmu->filter_user) && int_en; +} + +static const struct hisi_uncore_ops hisi_uncore_its_ops =3D { + .write_evtype =3D hisi_its_pmu_write_evtype, + .get_event_idx =3D hisi_uncore_pmu_get_event_idx, + .read_counter =3D hisi_its_pmu_read_counter, + .write_counter =3D hisi_its_pmu_write_counter, + .enable_counter =3D hisi_its_pmu_enable_counter, + .disable_counter =3D hisi_its_pmu_disable_counter, + .enable_counter_int =3D hisi_its_pmu_enable_counter_int, + .disable_counter_int =3D hisi_its_pmu_disable_counter_int, + .start_counters =3D hisi_its_pmu_start_counters, + .stop_counters =3D hisi_its_pmu_stop_counters, + .enable_filter =3D hisi_its_pmu_enable_filter, + .disable_filter =3D hisi_its_pmu_disable_filter, + .check_filter =3D hisi_its_pmu_check_filter +}; + +static struct attribute *hisi_its_pmu_format_attrs[] =3D { + HISI_PMU_FORMAT_ATTR(event, "config:0-7"), + HISI_PMU_FORMAT_ATTR(int_id, "config1:0-31"), + HISI_PMU_FORMAT_ATTR(int_en, "config1:32-32"), + NULL +}; + +static const struct attribute_group hisi_its_pmu_format_group =3D { + .name =3D "format", + .attrs =3D hisi_its_pmu_format_attrs, +}; + +static struct attribute *hisi_its_pmu_events_attrs[] =3D { + HISI_PMU_EVENT_ATTR(lpi_num, 0xc0), + HISI_PMU_EVENT_ATTR(lpi_time, 0x80), + HISI_PMU_EVENT_ATTR(sgi_num, 0xc1), + HISI_PMU_EVENT_ATTR(sgi_time, 0x81), + HISI_PMU_EVENT_ATTR(ppi_num, 0xc2), + HISI_PMU_EVENT_ATTR(ppi_time, 0x82), + HISI_PMU_EVENT_ATTR(sl3_lpi_num, 0xc3), + HISI_PMU_EVENT_ATTR(sl3_sgi_num, 0xc4), + HISI_PMU_EVENT_ATTR(sl3_ppi_num, 0xc5), + HISI_PMU_EVENT_ATTR(sl0_ddr_read, 0xc9), + HISI_PMU_EVENT_ATTR(sl0_ddr_time, 0x89), + HISI_PMU_EVENT_ATTR(sl1_ddr_read, 0xca), + HISI_PMU_EVENT_ATTR(sl1_ddr_time, 0x8a), + HISI_PMU_EVENT_ATTR(sl2_ddr_read, 0xcb), + HISI_PMU_EVENT_ATTR(sl2_ddr_time, 0x8b), + HISI_PMU_EVENT_ATTR(cycles, 0xcc), + NULL +}; + +static const struct attribute_group hisi_its_pmu_events_group =3D { + .name =3D "events", + .attrs =3D hisi_its_pmu_events_attrs, +}; + +static const struct attribute_group *hisi_its_pmu_attr_groups[] =3D { + &hisi_its_pmu_format_group, + &hisi_its_pmu_events_group, + &hisi_pmu_cpumask_attr_group, + &hisi_pmu_identifier_group, + NULL +}; + +static int hisi_its_pmu_dev_init(struct platform_device *pdev, + struct hisi_its_pmu *its_pmu) +{ + struct hisi_its_pmu_regs *reg_info; + struct hisi_pmu *pmu =3D &its_pmu->pmu; + + hisi_uncore_pmu_init_topology(pmu, &pdev->dev); + + if (pmu->topo.scl_id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, "failed to get scl-id\n"); + + if (pmu->topo.index_id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, "failed to get idx-id\n"); + + pmu->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmu->base)) + return dev_err_probe(&pdev->dev, PTR_ERR(pmu->base), + "fail to remap io memory\n"); + + pmu->dev_info =3D device_get_match_data(&pdev->dev); + if (!pmu->dev_info) + return -ENODEV; + + pmu->pmu_events.attr_groups =3D pmu->dev_info->attr_groups; + pmu->counter_bits =3D pmu->dev_info->counter_bits; + pmu->check_event =3D pmu->dev_info->check_event; + pmu->num_counters =3D ITS_PMU_NR_COUNTERS; + pmu->ops =3D &hisi_uncore_its_ops; + pmu->dev =3D &pdev->dev; + pmu->on_cpu =3D -1; + + reg_info =3D pmu->dev_info->private; + pmu->identifier =3D readl(pmu->base + reg_info->version); + + return 0; +} + +static void hisi_its_pmu_remove_cpuhp_instance(void *hotplug_node) +{ + cpuhp_state_remove_instance_nocalls(hisi_its_pmu_cpuhp_state, hotplug_nod= e); +} + +static void hisi_its_pmu_unregister_pmu(void *pmu) +{ + perf_pmu_unregister(pmu); +} + +static int hisi_its_pmu_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct hisi_its_pmu *its_pmu; + struct hisi_pmu *pmu; + char *name; + int ret; + + its_pmu =3D devm_kzalloc(dev, sizeof(*its_pmu), GFP_KERNEL); + if (!its_pmu) + return -ENOMEM; + + pmu =3D &its_pmu->pmu; + + /* + * HiSilicon Uncore PMU framework needs to get common hisi_pmu device + * from device's drvdata. + */ + platform_set_drvdata(pdev, its_pmu); + + ret =3D hisi_its_pmu_dev_init(pdev, its_pmu); + if (ret) + return ret; + + ret =3D cpuhp_state_add_instance(hisi_its_pmu_cpuhp_state, &pmu->node); + if (ret) + return dev_err_probe(dev, ret, "Fail to register cpuhp instance\n"); + + ret =3D devm_add_action_or_reset(dev, hisi_its_pmu_remove_cpuhp_instance, + &pmu->node); + if (ret) + return ret; + + hisi_pmu_init(pmu, THIS_MODULE); + + name =3D devm_kasprintf(dev, GFP_KERNEL, "hisi_scl%d_its%d", + pmu->topo.scl_id, pmu->topo.index_id); + if (!name) + return -ENOMEM; + + ret =3D perf_pmu_register(&pmu->pmu, name, -1); + if (ret) + return dev_err_probe(dev, ret, "Fail to register PMU\n"); + + return devm_add_action_or_reset(dev, hisi_its_pmu_unregister_pmu, + &pmu->pmu); +} + +static struct hisi_its_pmu_regs hisi_its_v1_pmu_regs =3D { + .version =3D ITS_PMU_VERSION, + .pmu_ctrl =3D ITS_PMU_GLOBAL_CTRL, + .event_ctrl0 =3D ITS_PMU_EVENT_CTRL, + .event_cntr0 =3D ITS_PMU_COUNTER0, + .cntr_ctrl =3D ITS_PMU_COUNTER_CTRL, +}; + +static const struct hisi_pmu_dev_info hisi_its_v1 =3D { + .attr_groups =3D hisi_its_pmu_attr_groups, + .counter_bits =3D 48, + .check_event =3D ITS_PMU_EVENT_CTRL_TYPE, + .private =3D &hisi_its_v1_pmu_regs, +}; + +static const struct acpi_device_id hisi_its_pmu_ids[] =3D { + { "HISI0591", (kernel_ulong_t)&hisi_its_v1 }, + { } +}; +MODULE_DEVICE_TABLE(acpi, hisi_its_pmu_ids); + +static struct platform_driver hisi_its_pmu_driver =3D { + .driver =3D { + .name =3D "hisi_its_pmu", + .acpi_match_table =3D hisi_its_pmu_ids, + .suppress_bind_attrs =3D true, + }, + .probe =3D hisi_its_pmu_probe, +}; + +static int __init hisi_its_pmu_module_init(void) +{ + int ret =3D cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, + "perf/hisi/its:online", + hisi_uncore_pmu_online_cpu, + hisi_uncore_pmu_offline_cpu); + if (ret < 0) { + pr_err("hisi_its_pmu: Fail to setup cpuhp callbacks, ret =3D %d\n", ret); + return ret; + } + hisi_its_pmu_cpuhp_state =3D ret; + + ret =3D platform_driver_register(&hisi_its_pmu_driver); + if (ret) + cpuhp_remove_multi_state(hisi_its_pmu_cpuhp_state); + + return ret; +} +module_init(hisi_its_pmu_module_init); + +static void __exit hisi_its_pmu_module_exit(void) +{ + platform_driver_unregister(&hisi_its_pmu_driver); + cpuhp_remove_multi_state(hisi_its_pmu_cpuhp_state); +} +module_exit(hisi_its_pmu_module_exit); + +MODULE_IMPORT_NS("HISI_PMU"); +MODULE_DESCRIPTION("HiSilicon SoC Uncore ITS PMU driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Yushan Wang "); --=20 2.33.0 From nobody Sat Jul 25 21:30:55 2026 Received: from canpmsgout06.his.huawei.com (canpmsgout06.his.huawei.com [113.46.200.221]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6FBF521773D for ; Mon, 13 Jul 2026 12:57:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.221 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783947423; 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Mon, 13 Jul 2026 20:56:50 +0800 From: Yushan Wang To: , , , , CC: , , , , , Subject: [PATCH v3 2/2] drivers/perf: hisi: Add new function for HiSilicon MN PMU driver Date: Mon, 13 Jul 2026 20:56:47 +0800 Message-ID: <20260713125647.2958626-3-wangyushan12@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260713125647.2958626-1-wangyushan12@huawei.com> References: <20260713125647.2958626-1-wangyushan12@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems200001.china.huawei.com (7.221.188.67) To whupemo500002.china.huawei.com (7.152.185.250) Content-Type: text/plain; charset="utf-8" From: Yifan Wu MN (Miscellaneous Node) is a hybrid node in ARM CHI. The MN PMU driver using the HiSilicon uncore PMU framework. On HiSilicon HIP13 platform, cycle event is supported on MN PMU. The cycle event is exposed directly in driver and some variables shall be added suffix to distinguish the version. Signed-off-by: Yifan Wu Signed-off-by: Yushan Wang --- drivers/perf/hisilicon/hisi_uncore_mn_pmu.c | 63 ++++++++++++++++++--- 1 file changed, 56 insertions(+), 7 deletions(-) diff --git a/drivers/perf/hisilicon/hisi_uncore_mn_pmu.c b/drivers/perf/his= ilicon/hisi_uncore_mn_pmu.c index 246cc0333099..f38a5880ca18 100644 --- a/drivers/perf/hisilicon/hisi_uncore_mn_pmu.c +++ b/drivers/perf/hisilicon/hisi_uncore_mn_pmu.c @@ -191,7 +191,7 @@ static const struct attribute_group hisi_mn_pmu_format_= group =3D { .attrs =3D hisi_mn_pmu_format_attr, }; =20 -static struct attribute *hisi_mn_pmu_events_attr[] =3D { +static struct attribute *hisi_mn_pmu_events_attr_v1[] =3D { HISI_PMU_EVENT_ATTR(req_eobarrier_num, 0x00), HISI_PMU_EVENT_ATTR(req_ecbarrier_num, 0x01), HISI_PMU_EVENT_ATTR(req_dvmop_num, 0x02), @@ -218,14 +218,55 @@ static struct attribute *hisi_mn_pmu_events_attr[] = =3D { NULL }; =20 -static const struct attribute_group hisi_mn_pmu_events_group =3D { +static const struct attribute_group hisi_mn_pmu_events_group_v1 =3D { .name =3D "events", - .attrs =3D hisi_mn_pmu_events_attr, + .attrs =3D hisi_mn_pmu_events_attr_v1, }; =20 -static const struct attribute_group *hisi_mn_pmu_attr_groups[] =3D { +static const struct attribute_group *hisi_mn_pmu_attr_groups_v1[] =3D { &hisi_mn_pmu_format_group, - &hisi_mn_pmu_events_group, + &hisi_mn_pmu_events_group_v1, + &hisi_pmu_cpumask_attr_group, + &hisi_pmu_identifier_group, + NULL +}; + +static struct attribute *hisi_mn_pmu_events_attr_v2[] =3D { + HISI_PMU_EVENT_ATTR(req_eobarrier_num, 0x00), + HISI_PMU_EVENT_ATTR(req_ecbarrier_num, 0x01), + HISI_PMU_EVENT_ATTR(req_dvmop_num, 0x02), + HISI_PMU_EVENT_ATTR(req_dvmsync_num, 0x03), + HISI_PMU_EVENT_ATTR(req_retry_num, 0x04), + HISI_PMU_EVENT_ATTR(req_writenosnp_num, 0x05), + HISI_PMU_EVENT_ATTR(req_readnosnp_num, 0x06), + HISI_PMU_EVENT_ATTR(snp_dvm_num, 0x07), + HISI_PMU_EVENT_ATTR(snp_dvmsync_num, 0x08), + HISI_PMU_EVENT_ATTR(l3t_req_dvm_num, 0x09), + HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_num, 0x0A), + HISI_PMU_EVENT_ATTR(mn_req_dvm_num, 0x0B), + HISI_PMU_EVENT_ATTR(mn_req_dvmsync_num, 0x0C), + HISI_PMU_EVENT_ATTR(pa_req_dvm_num, 0x0D), + HISI_PMU_EVENT_ATTR(pa_req_dvmsync_num, 0x0E), + HISI_PMU_EVENT_ATTR(cycles, 0x0F), + HISI_PMU_EVENT_ATTR(snp_dvm_latency, 0x80), + HISI_PMU_EVENT_ATTR(snp_dvmsync_latency, 0x81), + HISI_PMU_EVENT_ATTR(l3t_req_dvm_latency, 0x82), + HISI_PMU_EVENT_ATTR(l3t_req_dvmsync_latency, 0x83), + HISI_PMU_EVENT_ATTR(mn_req_dvm_latency, 0x84), + HISI_PMU_EVENT_ATTR(mn_req_dvmsync_latency, 0x85), + HISI_PMU_EVENT_ATTR(pa_req_dvm_latency, 0x86), + HISI_PMU_EVENT_ATTR(pa_req_dvmsync_latency, 0x87), + NULL +}; + +static const struct attribute_group hisi_mn_pmu_events_group_v2 =3D { + .name =3D "events", + .attrs =3D hisi_mn_pmu_events_attr_v2, +}; + +static const struct attribute_group *hisi_mn_pmu_attr_groups_v2[] =3D { + &hisi_mn_pmu_format_group, + &hisi_mn_pmu_events_group_v2, &hisi_pmu_cpumask_attr_group, &hisi_pmu_identifier_group, NULL @@ -350,14 +391,22 @@ static struct hisi_mn_pmu_regs hisi_mn_v1_pmu_regs = =3D { }; =20 static const struct hisi_pmu_dev_info hisi_mn_v1 =3D { - .attr_groups =3D hisi_mn_pmu_attr_groups, + .attr_groups =3D hisi_mn_pmu_attr_groups_v1, + .counter_bits =3D 48, + .check_event =3D HISI_MN_EVTYPE_MASK, + .private =3D &hisi_mn_v1_pmu_regs, +}; + +static const struct hisi_pmu_dev_info hisi_mn_v2 =3D { + .attr_groups =3D hisi_mn_pmu_attr_groups_v2, .counter_bits =3D 48, .check_event =3D HISI_MN_EVTYPE_MASK, .private =3D &hisi_mn_v1_pmu_regs, }; =20 static const struct acpi_device_id hisi_mn_pmu_acpi_match[] =3D { - { "HISI0222", (kernel_ulong_t) &hisi_mn_v1 }, + { "HISI0222", (kernel_ulong_t)&hisi_mn_v1 }, + { "HISI0224", (kernel_ulong_t)&hisi_mn_v2 }, { } }; MODULE_DEVICE_TABLE(acpi, hisi_mn_pmu_acpi_match); --=20 2.33.0