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Mon, 13 Jul 2026 05:29:17 -0700 (PDT) From: Zhanpeng Zhang To: Tomasz Jeznach , Joerg Roedel , Will Deacon Cc: Robin Murphy , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Guo Ren , David Laight , Vivian Wang , Zong Li , cuiyunhui@bytedance.com, yuanzhu@bytedance.com, iommu@lists.linux.dev, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers Date: Mon, 13 Jul 2026 20:29:03 +0800 Message-ID: <20260713122903.9458-1-zhangzhanpeng.jasper@bytedance.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> References: <20260615064855.90316-1-zhangzhanpeng.jasper@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The RISC-V IOMMU specification [1] permits 64-bit registers to be accessed using two 32-bit transactions, high half first, and leaves the single-copy atomicity of 8-byte IOMMU register accesses unspecified. Use the generic hi_lo_readq_relaxed() and hi_lo_writeq_relaxed() helpers for ordinary 64-bit IOMMU registers. For DDTP, poll BUSY in the low half, then read the high half and compose the register value from the polled low half. HPM counter reads require a rollover-aware sequence and remain outside these accessors. This follows the 32-bit access direction proposed by Guo Ren [2] and uses the generic non-atomic MMIO helpers suggested by David Laight. [1] https://docs.riscv.org/reference/iommu/ [2] https://lore.kernel.org/r/20250903144217.837448-1-guoren@kernel.org Suggested-by: Guo Ren Suggested-by: David Laight Signed-off-by: Zhanpeng Zhang Acked-by: Chen Pei Reviewed-by: Guo Ren (Alibaba DAMO Academy) Reviewed-by: Tomasz Jeznach --- Changes in v3: - Use the DDTP access sequence from [1]: retain the low half returned by BUSY polling, read only the high half, and compose the DDTP value from those two 32-bit reads. Changes in v2: - Rework the patch based on Guo Ren's earlier proposal [1]. - Drop the build-time option and use 32-bit accesses unconditionally. - Drop the global lock and use the generic high-low MMIO helpers, as suggested by David Laight. - Poll DDTP.BUSY through its low half. Link to v1: [2] Specification discussion: [3] [1]: https://lore.kernel.org/r/20250903144217.837448-1-guoren@kernel.org [2]: https://lore.kernel.org/r/20260615064855.90316-1-zhangzhanpeng.jasper@= bytedance.com [3]: https://github.com/riscv-non-isa/riscv-iommu/issues/765 drivers/iommu/riscv/iommu.c | 9 ++++++--- drivers/iommu/riscv/iommu.h | 9 +++------ 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cec3ddd7ab1..d647b71ebec 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -670,9 +670,12 @@ void riscv_iommu_disable(struct riscv_iommu_device *io= mmu) =20 #define riscv_iommu_read_ddtp(iommu) ({ \ u64 ddtp; \ - riscv_iommu_readq_timeout((iommu), RISCV_IOMMU_REG_DDTP, ddtp, \ - !(ddtp & RISCV_IOMMU_DDTP_BUSY), 10, \ + u32 ddtp_lo, ddtp_hi; \ + riscv_iommu_readl_timeout((iommu), RISCV_IOMMU_REG_DDTP, ddtp_lo, \ + !(ddtp_lo & RISCV_IOMMU_DDTP_BUSY), 10, \ RISCV_IOMMU_DDTP_TIMEOUT); \ + ddtp_hi =3D riscv_iommu_readl((iommu), RISCV_IOMMU_REG_DDTP + 4); \ + ddtp =3D ((u64)ddtp_hi << 32) | ddtp_lo; \ ddtp; }) =20 static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu) @@ -1501,7 +1504,7 @@ static int riscv_iommu_init_check(struct riscv_iommu_= device *iommu) * regular boot flow and disable translation when we boot into a kexec * kernel and the previous kernel left them enabled. */ - ddtp =3D riscv_iommu_readq(iommu, RISCV_IOMMU_REG_DDTP); + ddtp =3D riscv_iommu_read_ddtp(iommu); if (ddtp & RISCV_IOMMU_DDTP_BUSY) return -EBUSY; =20 diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h index 46df79dd549..1b03790fbe1 100644 --- a/drivers/iommu/riscv/iommu.h +++ b/drivers/iommu/riscv/iommu.h @@ -11,6 +11,7 @@ #ifndef _RISCV_IOMMU_H_ #define _RISCV_IOMMU_H_ =20 +#include #include #include #include @@ -70,17 +71,13 @@ void riscv_iommu_disable(struct riscv_iommu_device *iom= mu); readl_relaxed((iommu)->reg + (addr)) =20 #define riscv_iommu_readq(iommu, addr) \ - readq_relaxed((iommu)->reg + (addr)) + hi_lo_readq_relaxed((iommu)->reg + (addr)) =20 #define riscv_iommu_writel(iommu, addr, val) \ writel_relaxed((val), (iommu)->reg + (addr)) =20 #define riscv_iommu_writeq(iommu, addr, val) \ - writeq_relaxed((val), (iommu)->reg + (addr)) - -#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeou= t_us) \ - readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \ - delay_us, timeout_us) + hi_lo_writeq_relaxed((val), (iommu)->reg + (addr)) =20 #define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeou= t_us) \ readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \ --=20 2.50.1 (Apple Git-155)