From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DC4E3B3898; Mon, 13 Jul 2026 08:33:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931613; cv=none; b=SpFs2m9+rrXzlxXrwTH+7S2uBQN80Zj4VFuuJvR2Sx7K/XH1vPWghe4h8mmn3/dTgq8G4P0UkFcHDav+uKRAM3Ew+J+76+Lnj7TTncv/dEFMrQkYq/d/zNhLFeyJELToLhYsL0VpwaYZ+HlGbWZ0K0aAyQ6W1NyBagN9cxac8Zo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931613; c=relaxed/simple; bh=NOpvoV0D7XtZqO7wwvw/+SVas2ypaGFktFrbrTvP9OY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=XmwA7dyrna0GD+2SykALd265lf23dQHHxZYZXeWUviusuLO0QQPfKBfwCkDk+SRvmzSlDEgG9SY7VkD9nYke2baZesaV9VKe9MU7PadxphVakZE1yv+ZMZO7fpiq6VRG1qE7mRgEzissGjw5dF85u8cM1tKO3V1PVlhCkjCItp4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TZWND6SA; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TZWND6SA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783931609; x=1815467609; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NOpvoV0D7XtZqO7wwvw/+SVas2ypaGFktFrbrTvP9OY=; b=TZWND6SAahE+dEjXFh54cYoq6KBGkHOJxsHEs9ukmOxG+mnq4r4mYhuX LI5MCUZ+3WyKQuXOVuI5T1sj4y97Kq6al6JsGdNzHGfC0MLQ3W5UwLgUT UHc436LTB9rJQH+RlK/sBt0M9kgrcPlaEXEgJzk7+fn79pk6NOh9UyB9k RHv72MLjeSKOwMpNhdCBgIdeHk46VCW+7m167csyzFo/+3hjmn1VETTUi V7hBeAf0cOmC3wAO8q654tIWBacdcaMUiq5DSVdrEKqSvbkT/7fA3iW/Q QWo/1ewBXGeC8gXiPJ/8CJth3+HVxNvSTrFW7vD15VczsjGPI1jKC8GM8 w==; X-CSE-ConnectionGUID: ajxz9tUwTwKlwGSz2YJySQ== X-CSE-MsgGUID: shjNBuxhTQuEgE40fsj9xQ== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84390075" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="84390075" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 01:33:27 -0700 X-CSE-ConnectionGUID: 8K+XRWDIR6m6QlzCSRXC/A== X-CSE-MsgGUID: ZhlxIsP9Q/Sptb5JUZba1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="255560741" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:23 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 1/7] perf/x86: Unregister PMI handler on PMU init failure Date: Mon, 13 Jul 2026 16:27:28 +0800 Message-Id: <20260713082734.3162099-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Fix an NMI handler leak in init_hw_perf_events(). When PMU initialization fails after register_nmi_handler(), the error path exits without calling unregister_nmi_handler(), leaving a stale NMI_LOCAL "PMI" handler registered. Add the missing call before clearing x86_pmu state. Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index af0b67ffb43d..872d07a5fa80 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2219,7 +2219,7 @@ static int __init init_hw_perf_events(void) err =3D cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", x86_pmu_prepare_cpu, x86_pmu_dead_cpu); if (err) - return err; + goto pmi_unregister; =20 err =3D cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, "perf/x86:starting", x86_pmu_starting_cpu, @@ -2273,6 +2273,8 @@ static int __init init_hw_perf_events(void) cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); out: cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); +pmi_unregister: + unregister_nmi_handler(NMI_LOCAL, "PMI"); out_bad_pmu: memset(&x86_pmu, 0, sizeof(x86_pmu)); return err; --=20 2.34.1 From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 139FD3B2FF6; Mon, 13 Jul 2026 08:33:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931616; cv=none; b=PJ8BMjEt+0yJaQW6tKvheX3tF0Qw4DjBtyqoV74S+1cC/nbXXeyJtHrbu1Fk6MCpxM3kz9tXDEp5Sciy1kh2zEVgsyRNbkSFiq9kf1lWJo7gXHLtpmlHrS+x2PqnvFgRtBhiutCWxDXD19SDG6dMe56JEtcbukoaMRkTZOG0N7o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931616; c=relaxed/simple; bh=bEpghCxtBfzbP9JP5pjN4vrrZvyfhYirS4rUH3OCbns=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=SpI8DHtVUu/xM2FgvCfh9c9ehx3yVonUVzyyaYQc+WFuvilIAPJXF79QgO4JrOUEm+nHWX4oPLelXjMeXa0TSzBBy/68kZbiYMOwpc6uS/Gxg9iZCdx5hf2YV74B00otd1vIafJ3MEfO9Kx07H0Rb+aky4OMk4GbkCOzjtRjIG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ntm+Yoff; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ntm+Yoff" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783931613; x=1815467613; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bEpghCxtBfzbP9JP5pjN4vrrZvyfhYirS4rUH3OCbns=; b=ntm+YoffUSykuBcGRzmRTWepMyEV2ktdeThQ3tlK3mexdAdOVsTsrijG XwP6nlIXph92lkgzpALaoO/zhAiXBOubaNnS8uriP20fdCrREft+s3Nkl bQexm6FjXZI41MRahMFFNSOQr8fg2tr3nU4i6EBGTARkK9Ey+zXtZaEQD b1Z81Lj9RB5xjzHbpGexQuKZ5/LaRe/cktw1eaQ1eE/OwRwlIYWtq29hQ 60dmjQT6oDy5KNmC3AY3Rh9Slj0uYb4M6jijjW+FF2eKW+m3yx0Z1QMnp o/DubgSUSA7t1QMdz4o8pi/jD7hiWQOY7xM6ZkTRPRfYUacWqcE/4DZU1 Q==; X-CSE-ConnectionGUID: 2WZDuXpxRUG2SQ6mCSzOLQ== X-CSE-MsgGUID: wiuzzuIyT8K2htFLScLWiw== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84390080" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="84390080" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 01:33:30 -0700 X-CSE-ConnectionGUID: sNJxQKD+RzGiSstIbMqFCQ== X-CSE-MsgGUID: JjI9YlrFQ2yIewQULhVSig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="255560752" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:26 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 2/7] perf/x86: Free hybrid state on PMU init failure Date: Mon, 13 Jul 2026 16:27:29 +0800 Message-Id: <20260713082734.3162099-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If PMU initialization fails, for example in check_hw_exists(), hybrid state can be left partially initialized: x86_pmu.hybrid_pmu is not freed and perf_is_hybrid remains set. This can leak memory and leave stale hybrid state reachable after a failed init path. Add x86_pmu_free_hybrid() and use it on PMU init failure paths so all hybrid-related state is consistently reset. Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/core.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 872d07a5fa80..6c63b27e11e6 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -2130,6 +2130,17 @@ void x86_pmu_show_pmu_cap(struct pmu *pmu) pr_info("... global_ctrl mask: %016llx\n", hybrid(pmu, intel_ctr= l)); } =20 +static void x86_pmu_free_hybrid(void) +{ + if (!x86_pmu.hybrid_pmu) + return; + + static_branch_disable(&perf_is_hybrid); + kfree(x86_pmu.hybrid_pmu); + x86_pmu.hybrid_pmu =3D NULL; + x86_pmu.num_hybrid_pmus =3D 0; +} + static int __init init_hw_perf_events(void) { struct x86_pmu_quirk *quirk; @@ -2258,9 +2269,6 @@ static int __init init_hw_perf_events(void) for (j =3D 0; j < i; j++) perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu); pr_warn("Failed to register hybrid PMUs\n"); - kfree(x86_pmu.hybrid_pmu); - x86_pmu.hybrid_pmu =3D NULL; - x86_pmu.num_hybrid_pmus =3D 0; goto out2; } } @@ -2276,6 +2284,7 @@ static int __init init_hw_perf_events(void) pmi_unregister: unregister_nmi_handler(NMI_LOCAL, "PMI"); out_bad_pmu: + x86_pmu_free_hybrid(); memset(&x86_pmu, 0, sizeof(x86_pmu)); return err; } --=20 2.34.1 From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1ABE43B2FF7; Mon, 13 Jul 2026 08:33:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931619; cv=none; b=PuWdJ9xIU3LdIUlXRS8JJsGUZEQYuoKiAaFAZWmhgSaCkKojxtWbax9Ceh0xE/5vDtwBbQrzi8jxv7PydvStOYJSV5Nf5bsBEmUE3HjLjoQgE2GVyKlrEsNXufpAlRRIY8DNV6OlOWsR5sQ1yJPydq81KBCGa947dvwXZX/j4o8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931619; 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d="scan'208";a="255560756" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:30 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 3/7] perf/x86: Guard intel_pmu_cpu_dead() against invalid hybrid PMU casts Date: Mon, 13 Jul 2026 16:27:30 +0800 Message-Id: <20260713082734.3162099-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In failure paths, cpuc->pmu can still point to the global static pmu instead of an embedded x86_hybrid_pmu::pmu. Calling hybrid_pmu() on that pointer causes an invalid container conversion and may lead to out-of-bounds access. This can happen in at least two cases: - init_hybrid_pmu() fails check_hw_exists() and leaves cpuc->pmu as-is. - CPU hotplug fails between CPUHP_PERF_X86_PREPARE and CPUHP_AP_PERF_X86_STARTING, and rollback invokes intel_pmu_cpu_dead(). Fix both paths by: - Clear cpuc->pmu to NULL when check_hw_exists() fails. - Validat that cpuc->pmu is not the global static pmu before calling hybrid_pmu() in intel_pmu_cpu_dead(). A new helper x86_get_static_pmu() is added to get the global static pmu. Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/core.c | 5 +++++ arch/x86/events/intel/core.c | 7 +++++-- arch/x86/events/perf_event.h | 1 + 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 6c63b27e11e6..a02f303a9151 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -790,6 +790,11 @@ int is_x86_event(struct perf_event *event) return false; } =20 +inline struct pmu *x86_get_static_pmu(void) +{ + return &pmu; +} + struct pmu *x86_get_pmu(unsigned int cpu) { struct cpu_hw_events *cpuc =3D &per_cpu(cpu_hw_events, cpu); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b39c6ce0efb5..a991fc4f1575 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6329,8 +6329,10 @@ static bool init_hybrid_pmu(int cpu) =20 intel_pmu_check_hybrid_pmus(pmu); =20 - if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) + if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) { + cpuc->pmu =3D NULL; return false; + } =20 pr_info("%s PMU driver: ", pmu->name); =20 @@ -6475,11 +6477,12 @@ void intel_cpuc_finish(struct cpu_hw_events *cpuc) static void intel_pmu_cpu_dead(int cpu) { struct cpu_hw_events *cpuc =3D &per_cpu(cpu_hw_events, cpu); + struct pmu *pmu =3D x86_get_static_pmu(); =20 release_arch_pebs_buf_on_cpu(cpu); intel_cpuc_finish(cpuc); =20 - if (is_hybrid() && cpuc->pmu) + if (is_hybrid() && cpuc->pmu && cpuc->pmu !=3D pmu) cpumask_clear_cpu(cpu, &hybrid_pmu(cpuc->pmu)->supported_cpus); } =20 diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index a8afea8d38f0..01ae287cde16 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1161,6 +1161,7 @@ static struct perf_pmu_format_hybrid_attr format_attr= _hybrid_##_name =3D {\ .pmu_type =3D _pmu, \ } =20 +struct pmu *x86_get_static_pmu(void); struct pmu *x86_get_pmu(unsigned int cpu); extern struct x86_pmu x86_pmu __read_mostly; =20 --=20 2.34.1 From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3BE1F3B3BF1; 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X-CSE-ConnectionGUID: hgLsQaFZRoOBrB78Uz3KcQ== X-CSE-MsgGUID: fmwmS2K5SuOELmvf8ysaYA== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84390093" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="84390093" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 01:33:37 -0700 X-CSE-ConnectionGUID: uHBWmmtyRgqkB1d/1mxMuw== X-CSE-MsgGUID: yEV4ZLQpTEGSXUPeW4r6NQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="255560761" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:33 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 4/7] perf/x86/intel: Unwind cpuc state if PEBS buffer setup fails Date: Mon, 13 Jul 2026 16:27:31 +0800 Message-Id: <20260713082734.3162099-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" intel_pmu_cpu_prepare() allocates per-CPU perf state first and then sets up the arch PEBS buffer. If alloc_arch_pebs_buf_on_cpu() fails, the previously allocated cpuc resources are left behind. Make the failure path call intel_cpuc_finish(cpuc) to release the per-CPU state allocated by intel_cpuc_prepare(). Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/intel/core.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a991fc4f1575..b47d2f00ac13 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5924,13 +5924,20 @@ int intel_cpuc_prepare(struct cpu_hw_events *cpuc, = int cpu) =20 static int intel_pmu_cpu_prepare(int cpu) { + struct cpu_hw_events *cpuc =3D &per_cpu(cpu_hw_events, cpu); int ret; =20 - ret =3D intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu); + ret =3D intel_cpuc_prepare(cpuc, cpu); if (ret) return ret; =20 - return alloc_arch_pebs_buf_on_cpu(cpu); + ret =3D alloc_arch_pebs_buf_on_cpu(cpu); + if (ret) { + intel_cpuc_finish(cpuc); + return ret; + } + + return 0; } =20 static void flip_smm_bit(void *data) --=20 2.34.1 From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DF6B3B4E84; Mon, 13 Jul 2026 08:33:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931623; cv=none; b=oxpG8qLKYyoYm5vRWh243CBjknxkOgn2KzcaB/oiNp8xYm3XyiFfIEFFM3cT7hr173RWdYEr81kRW68rG0/MOLXb6k1th5EZTDkzHPLduMGSPdDduzZoU/Quiyxnx5f9JuXZWlDS2mp4Kd9TP0jO0HG7/orx5x0VDMgcI2R3zCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931623; c=relaxed/simple; bh=xUI9F7Bl0hPe5uUi9KsItoNMoInFG3ExQYnKUS7BfMo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=d/jTPFrNht/PgfEU7hmb0Pr4mFBDQ4bD9aM5GIu6hzs33ZLOmLndXIvlZnrl3MMbi5dWPzD7eJCcFXPZgwQ+ai8YTw6JJfy5G24lMTyurf4BfZa2MESiuXo7KnbvKI/WjcQF0vpyxx56MxhoD/h2iKpFjwKR3AAu0FmJXxEXz64= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=iptFlXBm; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="iptFlXBm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783931621; x=1815467621; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xUI9F7Bl0hPe5uUi9KsItoNMoInFG3ExQYnKUS7BfMo=; b=iptFlXBmAG9j2XugATa+2pMVlKQNtF27JhR6zdcCcLe2Jqgyw8kxJREr l6QWCjUkqi5J59mO6qF0uqLOes0eQEp6mR2s6WBVKiM5MSr0QcbqvfqG+ MgOVHb2utC+1nu7lmsaXsJvObywlJc5zXyRGTm/8vW5btkWVyVDNtxjW8 AxDjy9MWakNnabVoP8fgxNdHEB0vgYXJnTuRUnAo/VDssXZSEaj92hxtd Pdpfia9Rf5whFgey1MFrJmpV1FLnYfp4097lk/lgVVsjzBiZM9AwV4Pj8 mx4YhfFtfh0BwNq2YgxMpNyrvMfPbzj9gZtAerue8gdb155YXQZ7uCqcP w==; X-CSE-ConnectionGUID: ZPe8UGiFQM6CoCjRh3lAhQ== X-CSE-MsgGUID: HdohhVhLQiyu2kyoGkwNGg== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84390105" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="84390105" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 01:33:40 -0700 X-CSE-ConnectionGUID: YCYVLq/DRX2I2wqjMr0BqA== X-CSE-MsgGUID: yrpPk2WyTtKLknDxp401sg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="255560764" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:37 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 5/7] perf/x86: Remove stale fixed counter helper and fix hybrid PMU access Date: Mon, 13 Jul 2026 16:27:32 +0800 Message-Id: <20260713082734.3162099-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On hybrid systems, init_hw_perf_events() can call check_hw_exists() with the global PMU pointer after perf_is_hybrid is set. In that case, fixed_counter_disabled() uses hybrid() on a non-hybrid PMU object, so the intel_ctrl access is taken from the wrong layout and can read out of bounds. fixed_counter_disabled() was added in commit 32451614da2a ("perf/x86/intel: Support CPUID 10.ECX to disable fixed counters"), when fixed counters were tracked via num_fixed_counters. Today fixed counters are represented by fixed_cntr_mask, so this helper is obsolete. Remove fixed_counter_disabled() and its callers, and rely directly on the fixed-counter bitmask. With the helper gone, check_hw_exists() no longer needs a PMU argument, so drop that parameter as well. This removes the invalid hybrid access and closes the out-of-bounds read risk. Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/core.c | 8 ++------ arch/x86/events/intel/core.c | 4 +--- arch/x86/events/perf_event.h | 9 +-------- 3 files changed, 4 insertions(+), 17 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index a02f303a9151..143a6e735d9e 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -265,7 +265,7 @@ static void release_pmc_hardware(void) {} =20 #endif =20 -bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask, +bool check_hw_exists(unsigned long *cntr_mask, unsigned long *fixed_cntr_mask) { u64 val, val_fail =3D -1, val_new=3D ~0; @@ -297,8 +297,6 @@ bool check_hw_exists(struct pmu *pmu, unsigned long *cn= tr_mask, if (ret) goto msr_fail; for_each_set_bit(i, fixed_cntr_mask, X86_PMC_IDX_MAX) { - if (fixed_counter_disabled(i, pmu)) - continue; if (val & (0x03ULL << i*4)) { bios_fail =3D 1; val_fail =3D val; @@ -1618,8 +1616,6 @@ void perf_event_print_debug(void) cpu, idx, prev_left); } for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) { - if (fixed_counter_disabled(idx, cpuc->pmu)) - continue; rdmsrq(x86_pmu_fixed_ctr_addr(idx), pmc_count); =20 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", @@ -2180,7 +2176,7 @@ static int __init init_hw_perf_events(void) pmu_check_apic(); =20 /* sanity check that the hardware exists or is emulated */ - if (!check_hw_exists(&pmu, x86_pmu.cntr_mask, x86_pmu.fixed_cntr_mask)) + if (!check_hw_exists(x86_pmu.cntr_mask, x86_pmu.fixed_cntr_mask)) goto out_bad_pmu; =20 pr_cont("%s PMU driver.\n", x86_pmu.name); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index b47d2f00ac13..c418176065f6 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3713,8 +3713,6 @@ static void intel_pmu_reset(void) wrmsrq_safe(x86_pmu_event_addr(idx), 0ull); } for_each_set_bit(idx, fixed_cntr_mask, INTEL_PMC_MAX_FIXED) { - if (fixed_counter_disabled(idx, cpuc->pmu)) - continue; wrmsrq_safe(x86_pmu_fixed_ctr_addr(idx), 0ull); } =20 @@ -6336,7 +6334,7 @@ static bool init_hybrid_pmu(int cpu) =20 intel_pmu_check_hybrid_pmus(pmu); =20 - if (!check_hw_exists(&pmu->pmu, pmu->cntr_mask, pmu->fixed_cntr_mask)) { + if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) { cpuc->pmu =3D NULL; return false; } diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 01ae287cde16..cc9cfaae4f01 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1243,7 +1243,7 @@ static inline int x86_pmu_rdpmc_index(int index) return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index; } =20 -bool check_hw_exists(struct pmu *pmu, unsigned long *cntr_mask, +bool check_hw_exists(unsigned long *cntr_mask, unsigned long *fixed_cntr_mask); =20 int x86_add_exclusive(unsigned int what); @@ -1456,13 +1456,6 @@ ssize_t events_hybrid_sysfs_show(struct device *dev, struct device_attribute *attr, char *page); =20 -static inline bool fixed_counter_disabled(int i, struct pmu *pmu) -{ - u64 intel_ctrl =3D hybrid(pmu, intel_ctrl); - - return !(intel_ctrl >> (i + INTEL_PMC_IDX_FIXED)); -} - #ifdef CONFIG_CPU_SUP_AMD =20 int amd_pmu_init(void); --=20 2.34.1 From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A6543B2FE6; Mon, 13 Jul 2026 08:33:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931631; cv=none; b=seFbPUzZ+oJztn9zHZavOy5v4E5X48rH26LnyZiXD3xkmg7VD38A2pm6xair2RogQijGmPSD6EoyLvFzPh0/zsszwItkCpKij2YzuUMpl0ydY6hVDr1XiWPZl1XYvsmJ5OmCUYesz7q5eQjzuAfd09xIhY5UMvGvh3G3FYyAuvY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931631; c=relaxed/simple; bh=FVSd+tb0+rC2LBuXM1YWEFpMUX0O9+RztOH4QA0tP+8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=N0ms8lsi65PNmJB1yYrJQ0GshV7Ya15xdHp8VrUU8wr2UoBNasYfIbfVYJs3sJvHOabEU7Zo2CZIa5rpMpTWya7WB35OlIePtN9hcJkcR5I4KIq4yTS7056y6BoBh6UjOPVnQTCOGz6j4rdIBZDL9faDv4cJyYSw0d6EgkJqNJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=nTHG6L4w; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="nTHG6L4w" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783931626; x=1815467626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FVSd+tb0+rC2LBuXM1YWEFpMUX0O9+RztOH4QA0tP+8=; b=nTHG6L4wprJtnK8ng0GCZ/U6GluWbuu54CQ8H/RVXgpSdzVgCOJLZqXn R+rqlsxK6+TCIg1Zb054vIw/VcpiY/ARLfqJWybHTkipAwPkAtqpFHrFE M8GPkOCGRGN3DhcmHyseQVNZxt/k/nbQKabNt+GMY0GLHHmdNVfQ3iGLd iJWo4Cb3+WWxSR9NV5rzNcWM5CCPDt3AEX+FluLf/cbvKY4nLACqEI7YL TucxDxiPDpIl96xGTu+2jhUUQIfn3n5A52Akd7BT/W3wKHwrIq52CKPi9 +FaOn9Jx0HCrdhivCaSSdeaxW/VESRkJwqn4r5oy+1u3cwIR12ki8iCgV w==; X-CSE-ConnectionGUID: s3ko5d4jRZ26xUKAGOzUEg== X-CSE-MsgGUID: eC/oQs/lTwCsKZJbf+NIwg== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84390114" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="84390114" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 01:33:44 -0700 X-CSE-ConnectionGUID: FxRI+ogHRWmVy4dOCv78kQ== X-CSE-MsgGUID: iVftmzRjTUWMaAouJFKDwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="255560769" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:40 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 6/7] perf/x86/intel: Fix intel_cap handling on hybrid PMUs Date: Mon, 13 Jul 2026 16:27:33 +0800 Message-Id: <20260713082734.3162099-7-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" intel_cap (IA32_PERF_CAPABILITIES) updates are currently tied to X86_FEATURE_ARCH_PERFMON_EXT, but these are independent feature paths. As a result, hybrid PMU capability state can be updated under the wrong condition. Also, intel_pmu_broken_perf_cap() is too narrow. Per RPL018, the missing PERF_METRICS_AVAILABLE bit affects both Raptor Lake and Meteor Lake parts, not only the currently covered subset. Move intel_cap updates out of the ARCH_PERFMON_EXT-gated path, extend intel_pmu_broken_perf_cap() coverage to both RPL and MTL families, and introduce intel_update_pmu_caps() to centralize PMU capability updates. Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/intel/core.c | 41 ++++++++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c418176065f6..bec92163a09f 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6147,8 +6147,15 @@ static void intel_pmu_check_extra_regs(struct extra_= reg *extra_regs); =20 static inline bool intel_pmu_broken_perf_cap(void) { - /* The Perf Metric (Bit 15) is always cleared */ - if (boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE || + /* + * The Perf Metric (Bit 15) is always cleared on P-core of + * PRL and MTL. Details can be found in RPL018 Errata Details. + * https://edc.intel.com/content/www/us/en/design/products/platforms/deta= ils/raptor-lake-s/13th-generation-core-processor-specification-update/errat= a-details/ + */ + if (boot_cpu_data.x86_vfm =3D=3D INTEL_RAPTORLAKE || + boot_cpu_data.x86_vfm =3D=3D INTEL_RAPTORLAKE_P || + boot_cpu_data.x86_vfm =3D=3D INTEL_RAPTORLAKE_S || + boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE || boot_cpu_data.x86_vfm =3D=3D INTEL_METEORLAKE_L) return true; =20 @@ -6183,7 +6190,7 @@ static inline void __intel_update_large_pebs_flags(st= ruct pmu *pmu) =20 #define counter_mask(_gp, _fixed) ((_gp) | ((u64)(_fixed) << INTEL_PMC_IDX= _FIXED)) =20 -static void update_pmu_cap(struct pmu *pmu) +static void update_pmu_cap_from_perfmonext(struct pmu *pmu) { unsigned int eax, ebx, ecx, edx; union cpuid35_eax eax_0; @@ -6241,10 +6248,24 @@ static void update_pmu_cap(struct pmu *pmu) WARN_ON(x86_pmu.arch_pebs =3D=3D 1); x86_pmu.arch_pebs =3D 0; } +} + +static void intel_update_pmu_caps(struct pmu *pmu) +{ + if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) + update_pmu_cap_from_perfmonext(pmu); =20 - if (!intel_pmu_broken_perf_cap()) { - /* Perf Metric (Bit 15) and PEBS via PT (Bit 16) are hybrid enumeration = */ - rdmsrq(MSR_IA32_PERF_CAPABILITIES, hybrid(pmu, intel_cap).capabilities); + if (is_hybrid() && this_cpu_has(X86_FEATURE_PDCM)) { + rdmsrq(MSR_IA32_PERF_CAPABILITIES, + hybrid(pmu, intel_cap).capabilities); + + /* + * Restore perf_metrics on platforms with broken + * perf_capablities. + */ + if (intel_pmu_broken_perf_cap() && + hybrid_pmu(pmu)->pmu_type =3D=3D hybrid_big) + hybrid(pmu, intel_cap).perf_metrics =3D 1; } } =20 @@ -6329,9 +6350,7 @@ static bool init_hybrid_pmu(int cpu) if (!cpumask_empty(&pmu->supported_cpus)) goto end; =20 - if (this_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) - update_pmu_cap(&pmu->pmu); - + intel_update_pmu_caps(&pmu->pmu); intel_pmu_check_hybrid_pmus(pmu); =20 if (!check_hw_exists(pmu->cntr_mask, pmu->fixed_cntr_mask)) { @@ -8828,8 +8847,8 @@ __init int intel_pmu_init(void) * from the leaf 0xa. The core specific update will be done later * when a new type is online. */ - if (!is_hybrid() && boot_cpu_has(X86_FEATURE_ARCH_PERFMON_EXT)) - update_pmu_cap(NULL); + if (!is_hybrid()) + intel_update_pmu_caps(NULL); =20 if (x86_pmu.arch_pebs) { static_call_update(intel_pmu_disable_event_ext, --=20 2.34.1 From nobody Sat Jul 25 22:02:58 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05FAD3B71B0; Mon, 13 Jul 2026 08:33:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931632; cv=none; b=e3E0bZhEtGCOzMNYSkj7nzqC1G09HWJ+240Dkh3hPX8YROTgpjttXRdkrulYkcvWjTCj2tzOetPii9z7x6jG3Q31Hb2F1S9hoPdaqeqT1YltZ2TvvmyxhltTLp8F4O1tLaa2sSnASOb4BarEZ7+QodAqWtmIRE0K35H4eNyw8iM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783931632; c=relaxed/simple; bh=JjRQDahHvHTmZRvDpD8gV7TkrX5uByr65wUx7EWU3YQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=f6XTCvksnYCSXjD7+24dMz/fcsjPP73dBuikbbn9brROhR6drfJS+mPZC5apH8n3u2prK2OmfiDWYHF3M0r0gWGeGLZToP0dNe9qRVV30L73BZU+7zDc9Dj/Fcwi18s0h6ezl+rtHY80hufcwiG2WJjbeh6FIyxLh5OUTO4jnTg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=OmquFIDA; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="OmquFIDA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1783931630; x=1815467630; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JjRQDahHvHTmZRvDpD8gV7TkrX5uByr65wUx7EWU3YQ=; b=OmquFIDAtXM4fP3VPyePJkn9z8oeufYK2x8A8CCglRRInlOOFlt4+WMj xOGpjfnzNFlyC4YC4WIw+maTf+UQSogPSfiUCg7RwQrebUdHntg4jWUH7 LnTDMk5cgGF5l345WZJQ6C/8/FwGwjn+9R8wT9QwVhKYqOJGWqmjuNLhb LmFjGHIY+788IjaO97FjWXA7vizytEGGZUyRzGal1Z2oIeIwTbgwm8v4g dsQzIXAAH5h3DKcGrVbtf54VKqRKgZ4SREiPfT5rv9uxAIZYhQ3VbPt6g 3hh5Xw4rwyLAdnoxqP2HrgTPhUGCYOsNZhIzMopWXHnjxXmux6BFolApY w==; X-CSE-ConnectionGUID: UZnkJFyfSpSkwfCwg5cGuw== X-CSE-MsgGUID: vH3y29eGRaq/r6bSabWGGg== X-IronPort-AV: E=McAfee;i="6800,10657,11841"; a="84390123" X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="84390123" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Jul 2026 01:33:49 -0700 X-CSE-ConnectionGUID: AgwzRcQCQAWv7Q9Wtp6AHQ== X-CSE-MsgGUID: EmmXzLvPRV6+g6K1HZzL0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,154,1779174000"; d="scan'208";a="255560773" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 13 Jul 2026 01:33:44 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Dapeng Mi Subject: [Patch v2 7/7] perf/x86: Optimize ACR handling in match_prev_assignment() Date: Mon, 13 Jul 2026 16:27:34 +0800 Message-Id: <20260713082734.3162099-8-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> References: <20260713082734.3162099-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" match_prev_assignment() currently forces a mismatch for ACR events, so ACR counter indices are reprogrammed on every scheduling pass. That causes avoidable overhead because disable and enable paths must touch multiple MSRs. The previous ACR assignment is already cached in acr_cfg_b[]. Use that state to compare the newly computed ACR counter indices in hwc->config1 against the cached value in acr_cfg_b[hwc->idx]. If they match, skip unnecessary disable and enable work. Also tighten is_acr_self_reload_event() so it first verifies the event is an ACR event before testing for the self-reload case. Signed-off-by: Dapeng Mi Reviewed-by: Thomas Falcon --- arch/x86/events/core.c | 13 ++++++++++++- arch/x86/events/perf_event.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 143a6e735d9e..8b3ea0adb965 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1297,6 +1297,17 @@ int x86_perf_rdpmc_index(struct perf_event *event) return event->hw.event_base_rdpmc; } =20 +static inline bool acr_match_prev_indices(struct perf_event *event, + struct cpu_hw_events *cpuc) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (!is_acr_event_group(event)) + return true; + /* ACR counter indices don't change. */ + return hwc->config1 =3D=3D cpuc->acr_cfg_b[hwc->idx]; +} + static inline int match_prev_assignment(struct perf_event *event, struct cpu_hw_events *cpuc, int i) @@ -1306,7 +1317,7 @@ static inline int match_prev_assignment(struct perf_e= vent *event, return hwc->idx =3D=3D cpuc->assign[i] && hwc->last_cpu =3D=3D smp_processor_id() && hwc->last_tag =3D=3D cpuc->tags[i] && - !is_acr_event_group(event); + acr_match_prev_indices(event, cpuc); } =20 static void x86_pmu_start(struct perf_event *event, int flags); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index cc9cfaae4f01..fa381110f7a7 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -141,7 +141,7 @@ static inline bool is_acr_self_reload_event(struct perf= _event *event) { struct hw_perf_event *hwc =3D &event->hw; =20 - if (hwc->idx < 0) + if (hwc->idx < 0 || !is_acr_event_group(event)) return false; =20 return test_bit(hwc->idx, (unsigned long *)&hwc->config1); --=20 2.34.1