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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3120c8e41fcsm41874021eec.15.2026.07.13.21.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 21:59:51 -0700 (PDT) From: Qiang Yu Date: Mon, 13 Jul 2026 21:59:36 -0700 Subject: [PATCH v9 1/7] dt-bindings: clock: qcom: Move glymur TCSR to own binding Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260713-tcsr_qref_0714-v9-1-373670ab15f9@oss.qualcomm.com> References: <20260713-tcsr_qref_0714-v9-0-373670ab15f9@oss.qualcomm.com> In-Reply-To: <20260713-tcsr_qref_0714-v9-0-373670ab15f9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Kees Cook , "Gustavo A. R. Silva" , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Qiang Yu , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784005189; l=5632; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=LKAINk67qcWpTEFbooGQl2hvLx8wgZLI8xl/8ZLIRNI=; b=MCSwBzrCoi31GS/AI8EhewAJanmu/dE9dSWBIP4u0je5ksjs3nQmD4+jJcSBOFeBufFPZICKa rhqY/C5MXn8B95xdkvxRk+5FtoTZF+UzXkXc9HjDqOhCwosQnjgscLi X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=FMErAeos c=1 sm=1 tr=0 ts=6a55c248 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=12nZpKSYVJl7DlM_WUUA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDA0NyBTYWx0ZWRfX//tJGE+eQwde NjqpjyBK5PdQuCn9bmEEZUFdb9HBfgpEFXxKL7u457C6RDKucdqbm6VaV5pDxY5yXmz8zfIp/I7 mq+y52pwpTQCMgJmgqFL/n4yjU8Mqf0= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDA0NyBTYWx0ZWRfX/nnGYIKyFkts VTVBZT1++Y3OgEaOZiXxLdVXoZmrOc2DtdbFRtx9PxWOeY0ECXNrhmA/9faOjjC+tRQyh2qh6TG k0e7XrTDC0y460+QP4JA6WDS/tu71jgBdvtnAdtLwZHNbQFies3zE3eXgtxyCsoUImN+uxpOcjm 1NqaODaO971wVzranSVXTnsd9G9vlKe+ItMIX2qjl8i8Fmw8R+6hdT6DDKy68KunmqyiT61rnK4 uYUzBr9zkUg4ATjhDX1J23VUjeXSv5+Q+Y0bCRhw+WnxPlwYC+QEFMRfAaqoJK+9DBXyy8FdMg1 rBuqzj0t/OT/tNz/iH71HgSnpfcGyXYzSs2tqXnieUIDa/UEdepqtdDlcG5QeiBi0s7c0gNg9ol rP+gJMrwBXfeqAhtJN/yC0exLimXnGksqpczu4Auw667lGtp0yv5GrETicNUjcVMa9cb/sRgpn0 c30Uu0QxAPjsQc+JLYQ== X-Proofpoint-ORIG-GUID: sB7j17-11XsbGXOyf-qbWgNmwox3W_JD X-Proofpoint-GUID: sB7j17-11XsbGXOyf-qbWgNmwox3W_JD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_01,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 suspectscore=0 priorityscore=1501 phishscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140047 The QREF block supplies reference clocks to PCIe PHYs and requires dedicated LDO supplies to operate. The digital control interface for QREF (clkref_en registers) resides in TCSR on glymur. Since QREF has no dedicated DT node of its own, these supply properties are placed in the TCSR node which acts as the control interface for QREF. Add a dedicated binding file for qcom,glymur-tcsr and document the supply properties. As this binding will grow to cover more SoCs, mark the required supplies per compatible using an allOf/if/then conditional. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qiang Yu --- .../bindings/clock/qcom,glymur-tcsr.yaml | 126 +++++++++++++++++= ++++ .../bindings/clock/qcom,sm8550-tcsr.yaml | 2 - 2 files changed, 126 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml new file mode 100644 index 000000000000..ec89feff89e4 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on Glymur + +maintainers: + - Bjorn Andersson + - Taniya Das + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on Glymur + + See also: + - include/dt-bindings/clock/qcom,glymur-tcsr.h + +properties: + compatible: + items: + - enum: + - qcom,glymur-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + vdda-qrefrpt5-0p9-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx3-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qrefrx5-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-refgen3-0p9-supply: true + vdda-refgen3-1p2-supply: true + vdda-refgen4-0p9-supply: true + vdda-refgen4-1p2-supply: true + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,glymur-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrx0-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx4-0p9-supply + - vdda-qrefrx5-0p9-supply + - vdda-qreftx0-0p9-supply + - vdda-qreftx0-1p2-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply + - vdda-refgen4-0p9-supply + - vdda-refgen4-1p2-supply + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@1fd5000 { + compatible =3D "qcom,glymur-tcsr", "syscon"; + reg =3D <0x0 0x1fd5000 0x0 0x21000>; + clocks =3D <&rpmhcc RPMH_CXO_CLK>; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + vdda-qrefrpt0-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx4-0p9-supply =3D <&vreg_l1a>; + vdda-qrefrx5-0p9-supply =3D <&vreg_l1a>; + vdda-qreftx0-0p9-supply =3D <&vreg_l1a>; + vdda-qreftx0-1p2-supply =3D <&vreg_l2a>; + vdda-qreftx1-0p9-supply =3D <&vreg_l1a>; + vdda-refgen3-0p9-supply =3D <&vreg_l1a>; + vdda-refgen3-1p2-supply =3D <&vreg_l2a>; + vdda-refgen4-0p9-supply =3D <&vreg_l1a>; + vdda-refgen4-1p2-supply =3D <&vreg_l2a>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 08824f848973..19ae0634b922 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -16,7 +16,6 @@ description: | =20 See also: - include/dt-bindings/clock/qcom,eliza-tcsr.h - - include/dt-bindings/clock/qcom,glymur-tcsr.h - include/dt-bindings/clock/qcom,hawi-tcsrcc.h - include/dt-bindings/clock/qcom,nord-tcsrcc.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h @@ -28,7 +27,6 @@ properties: items: - enum: - qcom,eliza-tcsr - - qcom,glymur-tcsr - qcom,hawi-tcsrcc - qcom,kaanapali-tcsr - qcom,milos-tcsr --=20 2.34.1 From nobody Sat Jul 25 20:10:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5252F2E9730 for ; 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Add qcom,mahua-tcsr compatible and document its required supply properties. Note that REFGEN4 is supplied by regulators vdda-refgen3-1p2 and vdda-refgen3-0p9 on Mahua. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qiang Yu --- .../devicetree/bindings/clock/qcom,glymur-tcsr.yaml | 20 ++++++++++++++++= ++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml index ec89feff89e4..2b6422627165 100644 --- a/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml @@ -22,6 +22,7 @@ properties: items: - enum: - qcom,glymur-tcsr + - qcom,mahua-tcsr - const: syscon =20 clocks: @@ -82,6 +83,25 @@ allOf: - vdda-refgen3-1p2-supply - vdda-refgen4-0p9-supply - vdda-refgen4-1p2-supply + - if: + properties: + compatible: + contains: + const: qcom,mahua-tcsr + then: + required: + - vdda-qrefrpt0-0p9-supply + - vdda-qrefrpt1-0p9-supply + - vdda-qrefrpt2-0p9-supply + - vdda-qrefrpt3-0p9-supply + - vdda-qrefrpt4-0p9-supply + - vdda-qrefrpt5-0p9-supply + - vdda-qrefrx1-0p9-supply + - vdda-qrefrx2-0p9-supply + - vdda-qrefrx3-0p9-supply + - vdda-qreftx1-0p9-supply + - vdda-refgen3-0p9-supply + - vdda-refgen3-1p2-supply =20 required: - compatible --=20 2.34.1 From nobody Sat Jul 25 20:10:44 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A5832F12AB for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3120c8e41fcsm41874021eec.15.2026.07.13.21.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 21:59:53 -0700 (PDT) From: Qiang Yu Date: Mon, 13 Jul 2026 21:59:38 -0700 Subject: [PATCH v9 3/7] clk: qcom: Add generic clkref_en support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260713-tcsr_qref_0714-v9-3-373670ab15f9@oss.qualcomm.com> References: <20260713-tcsr_qref_0714-v9-0-373670ab15f9@oss.qualcomm.com> In-Reply-To: <20260713-tcsr_qref_0714-v9-0-373670ab15f9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Kees Cook , "Gustavo A. R. Silva" , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, Qiang Yu , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1784005189; l=9170; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=acO2MCTs6Urgg6mKi8zA1uUMSJs9SW0vwIJyCHIgems=; b=EMm11caV7rvsrwZ4+VoPF4GwtbAYf/oXqS0UEKRvPBeHzsx+Zz6BuWkVNW8uRHy95LzDPU/pt w/ZZRqdaFnIDMGSign+16tORu5XGLshTk6691Tgl7jMh09XTmXnueTg X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzE0MDA0NyBTYWx0ZWRfX91mAolrGVcz9 krDnriOSuCxQ8JXEwagYhKNeqgcd6zdGwQrWgvKyPqpTdSMx0u/lUj5TNUp0QOUi5HCxFi0hLeV RNilGJo2nBdVpfDjsq1kQFyiV592hcjRSmyjrmtrsfzR+fB745lgRHaCRPMJtxscOwoutDD8Ipp Ilirnw5WKqRi1VrqXIGcT+crLYc0U31H1nuly/A8n9Lrema1wrWAZ5OpzG+8SONo7IKD12RT/0l UYsw9F4GLy7SLgncWt2LlybQ0wUGYt6bNpRt2ke7VTo1vJoFhN49wuIqFwz8zLrdOcEb+fouQ9A 1tIffPf/blzIDCWoUilrXF0U8KfdpdUdhW6J7Mkykx86Kyvqj+rLL7VU4Qx2d29RrE7X6NR1zbW 5w1EqPjDkF2Lu4M8A36arntorhFC5H8ZfcKEADXCpS1c+0E7iXzipgRSwvfpdEGclOHbXix4R1z r9SGwvzhFyCgmG09Qzg== X-Authority-Analysis: v=2.4 cv=HJrz0Itv c=1 sm=1 tr=0 ts=6a55c24a cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=r4lB9QUgC6LPr1KdvdsA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-GUID: L3E4alYDycJvk_xiLFCg8Efy9s2sNg8s X-Proofpoint-Spam-Info: AW1haW4tMjYwNzE0MDA0NyBTYWx0ZWRfX9b1kYiyiG38m OIySAw50xyDdJcUlCUbCKJyq+dlw7ZWuRW5XS2Ksu6AVfedNgS9uLdys6isKYbQdgrVYApDFAmy mQi7nCfyr30oum0+txuerDgUDvwIomo= X-Proofpoint-ORIG-GUID: L3E4alYDycJvk_xiLFCg8Efy9s2sNg8s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-14_01,2026-07-10_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 suspectscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607140047 Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ref.c | 205 +++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/clk/qcom.h | 67 +++++++++++++++ 3 files changed, 273 insertions(+) diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index db7689ee5dc6..fff069da16de 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,6 +8,7 @@ clk-qcom-y +=3D clk-pll.o clk-qcom-y +=3D clk-rcg.o clk-qcom-y +=3D clk-rcg2.o clk-qcom-y +=3D clk-branch.o +clk-qcom-y +=3D clk-ref.o clk-qcom-y +=3D clk-regmap-divider.o clk-qcom-y +=3D clk-regmap-mux.o clk-qcom-y +=3D clk-regmap-mux-div.o diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c new file mode 100644 index 000000000000..3efdf6749770 --- /dev/null +++ b/drivers/clk/qcom/clk-ref.c @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_CLK_REF_EN_MASK BIT(0) + +struct qcom_clk_ref_provider { + size_t num_refs; + struct qcom_clk_ref refs[] __counted_by(num_refs); +}; + +static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw) +{ + return container_of(hw, struct qcom_clk_ref, hw); +} + +static const struct clk_parent_data qcom_clk_ref_parent_data =3D { + .index =3D 0, +}; + +static int qcom_clk_ref_prepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + if (!rclk->desc.num_regulators) + return 0; + + ret =3D regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators= ); + if (ret) + pr_err("Failed to enable regulators for %s: %d\n", + clk_hw_get_name(hw), ret); + + return ret; +} + +static void qcom_clk_ref_unprepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + if (rclk->desc.num_regulators) + regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators); +} + +static int qcom_clk_ref_enable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + ret =3D regmap_set_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_= MASK); + if (ret) + return ret; + + udelay(10); + + return 0; +} + +static void qcom_clk_ref_disable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + regmap_clear_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK); + udelay(10); +} + +static int qcom_clk_ref_is_enabled(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + u32 val; + int ret; + + ret =3D regmap_read(rclk->regmap, rclk->desc.offset, &val); + if (ret) + return 0; + + return !!(val & QCOM_CLK_REF_EN_MASK); +} + +static const struct clk_ops qcom_clk_ref_ops =3D { + .prepare =3D qcom_clk_ref_prepare, + .unprepare =3D qcom_clk_ref_unprepare, + .enable =3D qcom_clk_ref_enable, + .disable =3D qcom_clk_ref_disable, + .is_enabled =3D qcom_clk_ref_is_enabled, +}; + +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap, + struct qcom_clk_ref *clk_refs, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs) +{ + const struct qcom_clk_ref_desc *desc; + struct clk_init_data init_data =3D {}; + struct qcom_clk_ref *clk_ref; + size_t clk_idx; + unsigned int i; + int ret; + + for (clk_idx =3D 0; clk_idx < num_clk_refs; clk_idx++) { + clk_ref =3D &clk_refs[clk_idx]; + desc =3D descs[clk_idx]; + + /* Skip unpopulated indices; the array is indexed by clock ID. */ + if (!desc) + continue; + + if (WARN_ON(!desc->name)) + continue; + + clk_ref->regmap =3D regmap; + clk_ref->desc =3D *desc; + + if (clk_ref->desc.num_regulators) { + clk_ref->regulators =3D devm_kcalloc(dev, clk_ref->desc.num_regulators, + sizeof(*clk_ref->regulators), + GFP_KERNEL); + if (!clk_ref->regulators) + return -ENOMEM; + + for (i =3D 0; i < clk_ref->desc.num_regulators; i++) + clk_ref->regulators[i].supply =3D + clk_ref->desc.regulator_names[i]; + + ret =3D devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators, + clk_ref->regulators); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get regulators for %s\n", + clk_ref->desc.name); + } + + init_data.name =3D clk_ref->desc.name; + init_data.parent_data =3D &qcom_clk_ref_parent_data; + init_data.num_parents =3D 1; + init_data.ops =3D &qcom_clk_ref_ops; + clk_ref->hw.init =3D &init_data; + + ret =3D devm_clk_hw_register(dev, &clk_ref->hw); + if (ret) + return ret; + } + + return 0; +} + +static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *cl= kspec, void *data) +{ + struct qcom_clk_ref_provider *provider =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D provider->num_refs) + return ERR_PTR(-EINVAL); + + if (!provider->refs[idx].regmap) + return ERR_PTR(-ENOENT); + + return &provider->refs[idx].hw; +} + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs) +{ + struct qcom_clk_ref_provider *provider; + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + provider =3D devm_kzalloc(dev, struct_size(provider, refs, num_clk_refs), + GFP_KERNEL); + if (!provider) + return -ENOMEM; + + provider->num_refs =3D num_clk_refs; + + ret =3D qcom_clk_ref_register(dev, regmap, provider->refs, descs, + provider->num_refs); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provid= er); +} +EXPORT_SYMBOL_GPL(qcom_clk_ref_probe); diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h new file mode 100644 index 000000000000..11ac2d42ff9e --- /dev/null +++ b/include/linux/clk/qcom.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __LINUX_CLK_QCOM_H +#define __LINUX_CLK_QCOM_H + +#include +#include +#include +#include +#include + +struct device; +struct platform_device; +struct regulator_bulk_data; + +/** + * struct qcom_clk_ref_desc - descriptor for a clkref_en gate clock + * @name: clock name exposed to the common clock framework + * @offset: clkref_en register offset from the block base + * @regulator_names: optional supply names enabled while preparing the clo= ck + * @num_regulators: number of entries in @regulator_names + */ +struct qcom_clk_ref_desc { + const char *name; + u32 offset; + const char * const *regulator_names; + unsigned int num_regulators; +}; + +/** + * struct qcom_clk_ref - per-clock data for a clkref_en gate clock + * @hw: common clock framework hardware clock handle + * @regmap: register map backing the clkref_en register + * @desc: clock descriptor copied at registration time + * @regulators: optional bulk regulator handles for @desc.regulator_names + */ +struct qcom_clk_ref { + struct clk_hw hw; + struct regmap *regmap; + struct qcom_clk_ref_desc desc; + struct regulator_bulk_data *regulators; +}; + +#if IS_ENABLED(CONFIG_COMMON_CLK_QCOM) + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc * const *descs, + size_t num_clk_refs); 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This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Co-developed-by: Konrad Dybcio Signed-off-by: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 361 +++++++++++++----------------------= ---- 1 file changed, 116 insertions(+), 245 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index b44fccb795c6..e0b545258ba4 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -4,276 +4,145 @@ */ =20 #include +#include #include +#include #include #include =20 #include =20 -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, +static const char * const glymur_tcsr_tx0_rx5_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qrefrx5-0p9", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", }; =20 -static struct clk_branch tcsr_edp_clkref_en =3D { - .halt_reg =3D 0x60, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x60, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_edp_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt0_rx0_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrx0-0p9", }; =20 -static struct clk_branch tcsr_pcie_1_clkref_en =3D { - .halt_reg =3D 0x48, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x48, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt01_rx1_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", }; =20 -static struct clk_branch tcsr_pcie_2_clkref_en =3D { - .halt_reg =3D 0x4c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x4c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt012_rx2_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", }; =20 -static struct clk_branch tcsr_pcie_3_clkref_en =3D { - .halt_reg =3D 0x54, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x54, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const char * const glymur_tcsr_tx1_rpt34_rx4_regulators[] =3D { + "vdda-refgen4-0p9", + "vdda-refgen4-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt3-0p9", + "vdda-qrefrpt4-0p9", + "vdda-qrefrx4-0p9", }; =20 -static struct clk_branch tcsr_pcie_4_clkref_en =3D { - .halt_reg =3D 0x58, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x58, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, - }, +static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x94, + .fast_io =3D true, }; =20 -static struct clk_branch tcsr_usb2_1_clkref_en =3D { - .halt_reg =3D 0x6c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x6c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, +static const struct qcom_clk_ref_desc * const tcsr_cc_glymur_clk_descs[] = =3D { + [TCSR_EDP_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, + .regulator_names =3D glymur_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt0_rx0_regulators), }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en =3D { - .halt_reg =3D 0x70, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x70, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_1_clkref_en", + .offset =3D 0x48, + .regulator_names =3D glymur_tcsr_tx0_rx5_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), }, -}; - -static struct clk_branch tcsr_usb2_3_clkref_en =3D { - .halt_reg =3D 0x74, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x74, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_2_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb2_4_clkref_en =3D { - .halt_reg =3D 0x88, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x88, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_3_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_branch tcsr_usb3_0_clkref_en =3D { - .halt_reg =3D 0x64, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x64, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_0_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_4_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D glymur_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt012_rx2_regulators), }, -}; - -static struct clk_branch tcsr_usb3_1_clkref_en =3D { - .halt_reg =3D 0x68, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x68, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, + .regulator_names =3D glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en =3D { - .halt_reg =3D 0x44, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x44, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_2_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, + .regulator_names =3D glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en =3D { - .halt_reg =3D 0x5c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x5c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_3_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, + .regulator_names =3D glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB2_4_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, + .regulator_names =3D glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB3_0_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, + .regulator_names =3D glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB3_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, + .regulator_names =3D glymur_tcsr_tx1_rpt34_rx4_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt34_rx4_regulators), + }, + [TCSR_USB4_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, + .regulator_names =3D glymur_tcsr_tx0_rx5_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx0_rx5_regulators), + }, + [TCSR_USB4_2_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, + .regulator_names =3D glymur_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(glymur_tcsr_tx1_rpt01_rx1_regulators), }, -}; - -static struct clk_regmap *tcsr_cc_glymur_clocks[] =3D { - [TCSR_EDP_CLKREF_EN] =3D &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, - [TCSR_PCIE_2_CLKREF_EN] =3D &tcsr_pcie_2_clkref_en.clkr, - [TCSR_PCIE_3_CLKREF_EN] =3D &tcsr_pcie_3_clkref_en.clkr, - [TCSR_PCIE_4_CLKREF_EN] =3D &tcsr_pcie_4_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, - [TCSR_USB2_3_CLKREF_EN] =3D &tcsr_usb2_3_clkref_en.clkr, - [TCSR_USB2_4_CLKREF_EN] =3D &tcsr_usb2_4_clkref_en.clkr, - [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, - [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] =3D &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] =3D &tcsr_usb4_2_clkref_en.clkr, -}; - -static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { - .reg_bits =3D 32, - .reg_stride =3D 4, - .val_bits =3D 32, - .max_register =3D 0x94, - .fast_io =3D true, -}; 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Add mahua-specific regulator arrays and clk descriptor table, and use match_data to select the correct descriptor table per compatible string at probe time. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 136 +++++++++++++++++++++++++++++++++++= +++- 1 file changed, 133 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index e0b545258ba4..1791e23739ed 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -12,6 +12,11 @@ =20 #include =20 +struct tcsrcc_glymur_data { + const struct qcom_clk_ref_desc * const *descs; + size_t num_descs; +}; + static const char * const glymur_tcsr_tx0_rx5_regulators[] =3D { "vdda-refgen3-0p9", "vdda-refgen3-1p2", @@ -56,6 +61,43 @@ static const char * const glymur_tcsr_tx1_rpt34_rx4_regu= lators[] =3D { "vdda-qrefrx4-0p9", }; =20 +static const char * const mahua_tcsr_tx1_rpt01_rx1_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt012_rx2_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt0_rx0_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrx0-0p9", +}; + +static const char * const mahua_tcsr_tx1_rpt345_rx3_regulators[] =3D { + "vdda-refgen3-0p9", + "vdda-refgen3-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt3-0p9", + "vdda-qrefrpt4-0p9", + "vdda-qrefrpt5-0p9", + "vdda-qrefrx3-0p9", +}; + static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -145,17 +187,105 @@ static const struct qcom_clk_ref_desc * const tcsr_c= c_glymur_clk_descs[] =3D { }, }; =20 +static const struct qcom_clk_ref_desc * const tcsr_cc_mahua_clk_descs[] = =3D { + [TCSR_EDP_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, + .regulator_names =3D mahua_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators), + }, + [TCSR_PCIE_2_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, + [TCSR_PCIE_3_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D mahua_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators), + }, + [TCSR_PCIE_4_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D mahua_tcsr_tx1_rpt012_rx2_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt012_rx2_regulators), + }, + [TCSR_USB2_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, + .regulator_names =3D mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB2_2_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, + .regulator_names =3D mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB2_3_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, + .regulator_names =3D mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB2_4_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, + .regulator_names =3D mahua_tcsr_tx1_rpt0_rx0_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt0_rx0_regulators), + }, + [TCSR_USB3_0_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, + .regulator_names =3D mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB3_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, + .regulator_names =3D mahua_tcsr_tx1_rpt345_rx3_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt345_rx3_regulators), + }, + [TCSR_USB4_1_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, + }, + [TCSR_USB4_2_CLKREF_EN] =3D &(const struct qcom_clk_ref_desc) { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, + .regulator_names =3D mahua_tcsr_tx1_rpt01_rx1_regulators, + .num_regulators =3D ARRAY_SIZE(mahua_tcsr_tx1_rpt01_rx1_regulators), + }, +}; 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Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 6125617de82a..44766a73b0d1 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -28,3 +28,23 @@ &mdss_dp1 { &mdss_dp1_out { link-frequencies =3D /bits/ 64 <1620000000 2700000000 5400000000 81000000= 00>; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx5-0p9-supply =3D <&vreg_l3f_e0_0p72>; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3120c8e41fcsm41874021eec.15.2026.07.13.21.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jul 2026 21:59:57 -0700 (PDT) From: Qiang Yu Date: Mon, 13 Jul 2026 21:59:42 -0700 Subject: [PATCH v9 7/7] arm64: dts: qcom: mahua: Add QREF regulator supplies to TCSR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260713-tcsr_qref_0714-v9-7-373670ab15f9@oss.qualcomm.com> References: <20260713-tcsr_qref_0714-v9-0-373670ab15f9@oss.qualcomm.com> In-Reply-To: <20260713-tcsr_qref_0714-v9-0-373670ab15f9@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Kees Cook , "Gustavo A. R. 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Override the TCSR compatible to qcom,mahua-tcsr in mahua.dtsi, and wire up the required LDO supplies on the CRD board. Unlike the other PCIe controllers, PCIe5 PHY on Mahua gets its refclk from the CXO0 pad directly and requires no QREF clkref_en voting. Hence, point its ref clock at RPMH_CXO_CLK. Reviewed-by: Konrad Dybcio Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/mahua-crd.dts | 16 ++++++++++++++++ arch/arm64/boot/dts/qcom/mahua.dtsi | 13 +++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/mahua-crd.dts b/arch/arm64/boot/dts/q= com/mahua-crd.dts index 9c8244e892dd..fa5229064b10 100644 --- a/arch/arm64/boot/dts/qcom/mahua-crd.dts +++ b/arch/arm64/boot/dts/qcom/mahua-crd.dts @@ -19,3 +19,19 @@ / { model =3D "Qualcomm Technologies, Inc. Mahua CRD"; compatible =3D "qcom,mahua-crd", "qcom,mahua"; }; + +&tcsr { + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt5-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen3-1p2-supply =3D <&vreg_l4f_e1_1p08>; +}; diff --git a/arch/arm64/boot/dts/qcom/mahua.dtsi b/arch/arm64/boot/dts/qcom= /mahua.dtsi index 22822b6b2e8b..e6c059708912 100644 --- a/arch/arm64/boot/dts/qcom/mahua.dtsi +++ b/arch/arm64/boot/dts/qcom/mahua.dtsi @@ -115,6 +115,15 @@ &oobm_ss_noc { compatible =3D "qcom,mahua-oobm-ss-noc", "qcom,glymur-oobm-ss-noc"; }; =20 +&pcie5_phy { + clocks =3D <&gcc GCC_PCIE_PHY_5_AUX_CLK>, + <&gcc GCC_PCIE_5_CFG_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_5_PIPE_CLK>, + <&gcc GCC_PCIE_5_PIPE_DIV2_CLK>; +}; + &pcie_east_anoc { compatible =3D "qcom,mahua-pcie-east-anoc", "qcom,glymur-pcie-east-anoc"; }; @@ -286,6 +295,10 @@ gpuss-4-critical { }; }; =20 +&tcsr { + compatible =3D "qcom,mahua-tcsr", "syscon"; +}; + &tlmm { compatible =3D "qcom,mahua-tlmm"; }; --=20 2.34.1