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Qualcomm Shikra uses DPU 6.5 hardware (same as QCM2290). Platform-specific compatible strings are used as the primary match with QCM2290 fallbacks to reuse the existing driver support. The dispcc clock inputs for the DSI byte and pixel PLLs are wired from mdss_dsi0_phy. Reviewed-by: Konrad Dybcio Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/shikra.dtsi | 206 +++++++++++++++++++++++++++++++= +++- 1 file changed, 204 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qco= m/shikra.dtsi index e67fe047a683..9169356cac05 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -1990,6 +1991,207 @@ gpucc: clock-controller@5990000 { #power-domain-cells =3D <1>; }; =20 + mdss: display-subsystem@5e00000 { + compatible =3D "qcom,shikra-mdss", "qcom,qcm2290-mdss"; + reg =3D <0x0 0x05e00000 0x0 0x1000>; + reg-names =3D "mdss"; + interrupts =3D ; + interrupt-controller; + #interrupt-cells =3D <1>; + + clocks =3D <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names =3D "iface", + "bus", + "core"; + + resets =3D <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains =3D <&dispcc MDSS_GDSC>; + + iommus =3D <&apps_smmu 0x420 0x2>; + interconnects =3D <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>, + <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + status =3D "disabled"; + + mdp: display-controller@5e01000 { + compatible =3D "qcom,shikra-dpu", "qcom,qcm2290-dpu"; + reg =3D <0x0 0x05e01000 0x0 0x8f000>, + <0x0 0x05eb0000 0x0 0x3000>; + reg-names =3D "mdp", + "vbif"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <0>; + + clocks =3D <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names =3D "bus", + "iface", + "core", + "lut", + "vsync"; + + operating-points-v2 =3D <&mdp_opp_table>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz =3D /bits/ 64 <256000000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz =3D /bits/ 64 <307200000>; + required-opps =3D <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz =3D /bits/ 64 <384000000>; + required-opps =3D <&rpmpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@5e94000 { + compatible =3D "qcom,shikra-dsi-ctrl", + "qcom,qcm2290-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg =3D <0x0 0x05e94000 0x0 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupt-parent =3D <&mdss>; + interrupts =3D <4>; + + clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks =3D <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents =3D <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 =3D <&dsi_opp_table>; + power-domains =3D <&rpmpd RPMPD_VDDCX>; + phys =3D <&mdss_dsi0_phy>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + status =3D "disabled"; + + dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmpd_opp_min_svs>; + }; + + opp-164000000 { + opp-hz =3D /bits/ 64 <164000000>; + required-opps =3D <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmpd_opp_svs>; + }; + }; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@5e94400 { + compatible =3D "qcom,dsi-phy-14nm-2290"; + reg =3D <0x0 0x05e94400 0x0 0x100>, + <0x0 0x05e94500 0x0 0x300>, + <0x0 0x05e94800 0x0 0x188>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names =3D "iface", + "ref"; + + power-domains =3D <&rpmpd RPMPD_VDDMX>; + required-opps =3D <&rpmpd_opp_nom>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + + status =3D "disabled"; + }; + }; + dispcc: clock-controller@5f00000 { compatible =3D "qcom,shikra-dispcc", "qcom,qcm2290-dispcc"; reg =3D <0x0 0x05f00000 0x0 0x20000>; @@ -1997,8 +2199,8 @@ dispcc: clock-controller@5f00000 { <&rpmcc RPM_SMD_XO_A_CLK_SRC>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, - <0>, - <0>, + <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, <0>, <0>, <&sleep_clk>; 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Signed-off-by: Arpit Saini Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 118 ++++++++++++++++++++++++= ++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqs-evk.dts index 26ff8007a819..e2b4f3ac7feb 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts @@ -23,6 +23,31 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + lcd_bias: regulator-lcd-bias { + compatible =3D "regulator-fixed"; + regulator-name =3D "lcd_bias"; + gpio =3D <&tlmm 151 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 =3D <&lcd_bias_en>; + pinctrl-names =3D "default"; + }; + + vreg_disp_n: regulator-vreg-disp-n { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_disp_n"; + regulator-min-microvolt =3D <5500000>; + regulator-max-microvolt =3D <5500000>; + vin-supply =3D <&lcd_bias>; + }; + + vreg_disp_p: regulator-vreg-disp-p { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_disp_p"; + regulator-min-microvolt =3D <5500000>; + regulator-max-microvolt =3D <5500000>; + vin-supply =3D <&lcd_bias>; + }; + wcn3988-pmu { compatible =3D "qcom,wcn3988-pmu"; =20 @@ -60,6 +85,53 @@ vreg_pmu_ch1: ldo4 { }; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&pm4125_l5>; + + status =3D "okay"; + + panel@0 { + compatible =3D "dlc,dlc0697", "ilitek,ili7807s"; + reg =3D <0>; + + reset-gpios =3D <&tlmm 3 GPIO_ACTIVE_LOW>; + + vddi-supply =3D <&pm4125_l15>; + avdd-supply =3D <&vreg_disp_p>; + avee-supply =3D <&vreg_disp_n>; + + pinctrl-0 =3D <&panel_rst_n &panel_te_pin &panel_bl_en>; + pinctrl-1 =3D <&panel_rst_n_suspend &panel_bl_en_suspend>; + pinctrl-names =3D "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status =3D "okay"; +}; + +&pm4125_l5 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt =3D <1232000>; + regulator-max-microvolt =3D <1232000>; + regulator-allow-set-load; +}; + &remoteproc_cdsp { firmware-name =3D "qcom/shikra/cdsp.mbn"; =20 @@ -95,6 +167,52 @@ &sdhc_1 { status =3D "okay"; }; =20 +&tlmm { + panel_rst_n: panel-rst-n-state { + pins =3D "gpio3"; + function =3D "gpio"; + drive-strength =3D <8>; + bias-disable; + }; + + panel_rst_n_suspend: panel-rst-n-suspend-state { + pins =3D "gpio3"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + }; + + panel_te_pin: panel-te-pin-state { + pins =3D "gpio86"; + function =3D "mdp_vsync_p"; + drive-strength =3D <2>; + bias-pull-down; + }; + + panel_bl_en: panel-bl-en-state { + pins =3D "gpio91"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + output-high; + }; + + panel_bl_en_suspend: panel-bl-en-suspend-state { + pins =3D "gpio91"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-pull-down; + output-low; + }; + + lcd_bias_en: lcd-bias-en-state { + pins =3D "gpio151"; + function =3D "gpio"; + drive-strength =3D <2>; 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Pin pm4125_l5 to 1.232V with regulator-allow-set-load for DSI PHY PLL stability. Signed-off-by: Arpit Saini Signed-off-by: Nabige Aala --- arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 118 ++++++++++++++++++++++++= ++++ 1 file changed, 118 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/= dts/qcom/shikra-cqm-evk.dts index 683b5245923b..0418774bcad8 100644 --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts @@ -23,6 +23,31 @@ chosen { stdout-path =3D "serial0:115200n8"; }; =20 + lcd_bias: regulator-lcd-bias { + compatible =3D "regulator-fixed"; + regulator-name =3D "lcd_bias"; + gpio =3D <&tlmm 151 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 =3D <&lcd_bias_en>; + pinctrl-names =3D "default"; + }; + + vreg_disp_n: regulator-vreg-disp-n { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_disp_n"; + regulator-min-microvolt =3D <5500000>; + regulator-max-microvolt =3D <5500000>; + vin-supply =3D <&lcd_bias>; + }; + + vreg_disp_p: regulator-vreg-disp-p { + compatible =3D "regulator-fixed"; + regulator-name =3D "vreg_disp_p"; + regulator-min-microvolt =3D <5500000>; + regulator-max-microvolt =3D <5500000>; + vin-supply =3D <&lcd_bias>; + }; + wcn3988-pmu { compatible =3D "qcom,wcn3988-pmu"; =20 @@ -60,6 +85,53 @@ vreg_pmu_ch1: ldo4 { }; }; =20 +&mdss { + status =3D "okay"; +}; + +&mdss_dsi0 { + vdda-supply =3D <&pm4125_l5>; + + status =3D "okay"; + + panel@0 { + compatible =3D "dlc,dlc0697", "ilitek,ili7807s"; + reg =3D <0>; + + reset-gpios =3D <&tlmm 3 GPIO_ACTIVE_LOW>; + + vddi-supply =3D <&pm4125_l15>; + avdd-supply =3D <&vreg_disp_p>; + avee-supply =3D <&vreg_disp_n>; + + pinctrl-0 =3D <&panel_rst_n &panel_te_pin &panel_bl_en>; + pinctrl-1 =3D <&panel_rst_n_suspend &panel_bl_en_suspend>; + pinctrl-names =3D "default", "sleep"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint =3D <&panel_in>; + data-lanes =3D <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status =3D "okay"; +}; + +&pm4125_l5 { + /* DSI VDDA - must be at NOM voltage for PHY PLL lock */ + regulator-min-microvolt =3D <1232000>; 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Signed-off-by: Arpit Saini Signed-off-by: Nabige Aala --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f2e6ae93e533..53f7b3d104ba 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1013,6 +1013,7 @@ CONFIG_DRM_PANEL_LVDS=3Dm CONFIG_DRM_PANEL_HIMAX_HX8279=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112A=3Dm CONFIG_DRM_PANEL_HIMAX_HX83112B=3Dm +CONFIG_DRM_PANEL_ILITEK_ILI7807S=3Dm CONFIG_DRM_PANEL_ILITEK_ILI9882T=3Dm CONFIG_DRM_PANEL_KHADAS_TS050=3Dm CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=3Dm --=20 2.34.1