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[61.228.44.142]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b93ae3b45sm12329887c88.15.2026.07.12.09.25.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jul 2026 09:25:14 -0700 (PDT) From: Shih-Yuan Lee To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Shih-Yuan Lee Subject: [PATCH 1/2] spi: pxa2xx: disable DMA and fix runtime PM for Apple MacBook8,1 Date: Mon, 13 Jul 2026 00:24:19 +0800 Message-Id: <20260712162420.7453-2-fourdollars@debian.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260712162420.7453-1-fourdollars@debian.org> References: <20260712162420.7453-1-fourdollars@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at 00:15.4 has two related problems: 1. The DMA handshake and interrupt routing frequently fail or time out, causing the keyboard and trackpad (driven by the applespi driver via SPI) to become unresponsive. Force PIO mode to avoid this. 2. When DMA is disabled, pm_runtime_allow() must not be called for the controller, because runtime autosuspend clock-gates the LPSS block between transfers. Accessing its MMIO registers while clock-gated triggers a PCIe Completion Timeout which causes a watchdog reset. Move the force-PIO quirk to spi-pxa2xx-pci.c (the LPSS host controller driver) to avoid layering violations in the client driver, and guard pm_runtime_allow() with the same pxa2xx_spi_pci_can_dma() check used to set enable_dma so that PIO-mode controllers stay permanently active. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D108331 Signed-off-by: Shih-Yuan Lee --- drivers/spi/spi-pxa2xx-pci.c | 38 +++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c index cae77ac18520..cb61f1d2d9e6 100644 --- a/drivers/spi/spi-pxa2xx-pci.c +++ b/drivers/spi/spi-pxa2xx-pci.c @@ -18,9 +18,14 @@ =20 #include #include +#include =20 #include "spi-pxa2xx.h" =20 +static bool spi_pxa2xx_force_pio; +module_param_named(force_pio, spi_pxa2xx_force_pio, bool, 0444); +MODULE_PARM_DESC(force_pio, "Force PIO mode (disables DMA) for SPI transfe= rs. ([0] =3D disabled, 1 =3D enabled)"); + #define PCI_DEVICE_ID_INTEL_QUARK_X1000 0x0935 #define PCI_DEVICE_ID_INTEL_BYT 0x0f0e #define PCI_DEVICE_ID_INTEL_MRFLD 0x1194 @@ -93,6 +98,32 @@ static void lpss_dma_put_device(void *dma_dev) pci_dev_put(dma_dev); } =20 +static const struct dmi_system_id pxa2xx_spi_pci_dmi_table[] =3D { + { + .ident =3D "Apple MacBook8,1", + .matches =3D { + DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), + DMI_MATCH(DMI_PRODUCT_NAME, "MacBook8,1"), + }, + }, + { } +}; + +static bool pxa2xx_spi_pci_can_dma(struct pci_dev *dev) +{ + if (spi_pxa2xx_force_pio) { + pci_info(dev, "Forcing PIO mode (disabling DMA)\n"); + return false; + } + + if (dmi_check_system(pxa2xx_spi_pci_dmi_table)) { + pci_info(dev, "MacBook8,1 detected: disabling DMA to force PIO mode\n"); + return false; + } + + return true; +} + static int lpss_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controlle= r *c) { struct ssp_device *ssp =3D &c->ssp; @@ -166,7 +197,7 @@ static int lpss_spi_setup(struct pci_dev *dev, struct p= xa2xx_spi_controller *c) =20 c->dma_filter =3D lpss_dma_filter; c->dma_burst_size =3D 1; - c->enable_dma =3D 1; + c->enable_dma =3D pxa2xx_spi_pci_can_dma(dev); return 0; } =20 @@ -238,7 +269,7 @@ static int mrfld_spi_setup(struct pci_dev *dev, struct = pxa2xx_spi_controller *c) =20 c->dma_filter =3D lpss_dma_filter; c->dma_burst_size =3D 8; - c->enable_dma =3D 1; + c->enable_dma =3D pxa2xx_spi_pci_can_dma(dev); return 0; } =20 @@ -303,7 +334,8 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev, pm_runtime_set_autosuspend_delay(&dev->dev, 50); pm_runtime_use_autosuspend(&dev->dev); pm_runtime_put_autosuspend(&dev->dev); - pm_runtime_allow(&dev->dev); + if (pxa2xx_spi_pci_can_dma(dev)) + pm_runtime_allow(&dev->dev); =20 return 0; } --=20 2.39.5 From nobody Sat Jul 25 22:32:23 2026 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73A6D356A37 for ; Sun, 12 Jul 2026 16:25:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[61.228.44.142]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13b93ae3b45sm12329887c88.15.2026.07.12.09.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Jul 2026 09:25:16 -0700 (PDT) From: Shih-Yuan Lee To: Mark Brown Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, Shih-Yuan Lee Subject: [PATCH 2/2] spi: pxa2xx: restore LPSS private and IDMA registers on S3 resume Date: Mon, 13 Jul 2026 00:24:20 +0800 Message-Id: <20260712162420.7453-3-fourdollars@debian.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20260712162420.7453-1-fourdollars@debian.org> References: <20260712162420.7453-1-fourdollars@debian.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel LPSS SPI controllers lose all private register state across S3 suspend because the LPSS power domain is fully removed. On resume the driver only re-enables the SSP clock but leaves the LPSS private registers (BAR0 0x200-0x2ff) and the IDMA registers (0x800-0x814) in their power-on-reset state, which causes two separate problems: 1. LPSS_PRIV_RESETS (0x204) stays zero, keeping the functional block and IDMA in reset. Writing 7 to de-assert both resets before any register access is mandatory; accessing MMIO while in reset causes a PCIe Completion Timeout and a watchdog-triggered system reset. 2. The IDMA block shares the SPI interrupt line. With its registers zeroed the IDMA asserts a spurious interrupt that masks the real SPI interrupt, causing every subsequent SPI transfer to time out (-110). 3. The LPSS software chip-select control register (0x224) must *not* be blindly restored from its suspend-time snapshot: if CS was asserted at the moment of suspend, restoring that state corrupts the first post-resume SPI transaction. Instead, call lpss_ssp_setup() which unconditionally writes SW_MODE | CS_HIGH (idle/deasserted), matching the state established at probe time. Fix all three issues by: - Saving the four LPSS clock/LTR/SSP private registers and six IDMA registers in pxa2xx_spi_suspend(). - In pxa2xx_spi_resume(), writing LPSS_PRIV_RESETS first, then restoring the saved private registers (excluding 0x204 and 0x224), then calling lpss_ssp_setup() to re-initialise CS to idle-high, and finally restoring the IDMA registers. Signed-off-by: Shih-Yuan Lee --- drivers/spi/spi-pxa2xx.c | 57 ++++++++++++++++++++++++++++++++++++++++ drivers/spi/spi-pxa2xx.h | 4 +++ 2 files changed, 61 insertions(+) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 6291d7c2e06f..e8a83c818328 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1479,12 +1479,35 @@ void pxa2xx_spi_remove(struct device *dev) } EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx"); =20 +/* + * LPSS private registers to save across S3 suspend. + * NOTE: 0x224 (CS control) is intentionally excluded - it is re-initialis= ed + * by lpss_ssp_setup() on resume to ensure CS starts deasserted (idle-high= ). + */ +static const unsigned int lpss_saved_regs[] =3D { + 0x200, + 0x204, + 0x220, + 0x238, +}; + static int pxa2xx_spi_suspend(struct device *dev) { struct driver_data *drv_data =3D dev_get_drvdata(dev); struct ssp_device *ssp =3D drv_data->ssp; int status; =20 + if (is_lpss_ssp(drv_data) && !pm_runtime_suspended(dev)) { + struct pxa2xx_spi_controller *pdata =3D drv_data->controller_info; + int i; + + for (i =3D 0; i < ARRAY_SIZE(lpss_saved_regs); i++) + pdata->lpss_priv_ctx[i] =3D readl(ssp->mmio_base + lpss_saved_regs[i]); + + for (i =3D 0; i < 6; i++) + pdata->lpss_idma_ctx[i] =3D readl(ssp->mmio_base + 0x800 + i * 4); + } + status =3D spi_controller_suspend(drv_data->controller); if (status) return status; @@ -1508,6 +1531,40 @@ static int pxa2xx_spi_resume(struct device *dev) status =3D clk_prepare_enable(ssp->clk); if (status) return status; + + if (is_lpss_ssp(drv_data)) { + struct pxa2xx_spi_controller *pdata =3D drv_data->controller_info; + int i; + + /* First de-assert resets by writing 7 to 0x204 (LPSS_PRIV_RESETS) */ + writel(7, ssp->mmio_base + 0x204); + + /* + * Restore clock/LTR/SSP private registers. + * 0x204 (resets) is skipped - already written above. + * 0x224 (CS control) is skipped - re-initialised by + * lpss_ssp_setup() below to ensure CS starts idle-high. + */ + for (i =3D 0; i < ARRAY_SIZE(lpss_saved_regs); i++) { + if (lpss_saved_regs[i] =3D=3D 0x204) + continue; + writel(pdata->lpss_priv_ctx[i], + ssp->mmio_base + lpss_saved_regs[i]); + } + + /* + * Re-initialise SW chip-select control so CS starts + * deasserted (SW_MODE | CS_HIGH) regardless of the + * state it was in at suspend time. + */ + lpss_ssp_setup(drv_data); + + /* Restore IDMA registers */ + for (i =3D 0; i < 6; i++) { + writel(pdata->lpss_idma_ctx[i], + ssp->mmio_base + 0x800 + i * 4); + } + } } =20 /* Start the queue running */ diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h index 447be0369384..423cef5118e7 100644 --- a/drivers/spi/spi-pxa2xx.h +++ b/drivers/spi/spi-pxa2xx.h @@ -34,6 +34,10 @@ struct pxa2xx_spi_controller { =20 /* For non-PXA arches */ struct ssp_device ssp; + + /* LPSS private registers context */ + u32 lpss_priv_ctx[4]; + u32 lpss_idma_ctx[6]; }; =20 struct spi_controller; --=20 2.39.5